hc
2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f
kernel/tools/arch/x86/include/asm/cpufeatures.h
....@@ -96,7 +96,7 @@
9696 #define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in IA32 userspace */
9797 #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */
9898 #define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */
99
-#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" MFENCE synchronizes RDTSC */
99
+#define X86_FEATURE_SME_COHERENT ( 3*32+17) /* "" AMD hardware-enforced cache coherency */
100100 #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */
101101 #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */
102102 #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
....@@ -108,6 +108,7 @@
108108 #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* Extended APICID (8 bits) */
109109 #define X86_FEATURE_AMD_DCM ( 3*32+27) /* AMD multi-node processor */
110110 #define X86_FEATURE_APERFMPERF ( 3*32+28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */
111
+/* free ( 3*32+29) */
111112 #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */
112113 #define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */
113114
....@@ -202,8 +203,8 @@
202203 #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
203204 #define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */
204205 #define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table Isolation enabled */
205
-#define X86_FEATURE_RETPOLINE ( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
206
-#define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* "" AMD Retpoline mitigation for Spectre variant 2 */
206
+#define X86_FEATURE_KERNEL_IBRS ( 7*32+12) /* "" Set/clear IBRS on kernel entry/exit */
207
+#define X86_FEATURE_RSB_VMEXIT ( 7*32+13) /* "" Fill RSB on VM-Exit */
207208 #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */
208209 #define X86_FEATURE_CDP_L2 ( 7*32+15) /* Code and Data Prioritization L2 */
209210 #define X86_FEATURE_MSR_SPEC_CTRL ( 7*32+16) /* "" MSR SPEC_CTRL is implemented */
....@@ -218,9 +219,10 @@
218219 #define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */
219220 #define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */
220221 #define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */
221
-#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */
222
+#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 or above (Zen) */
222223 #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */
223224 #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */
225
+#define X86_FEATURE_MSR_IA32_FEAT_CTL ( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */
224226
225227 /* Virtualization flags: Linux defined, word 8 */
226228 #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
....@@ -232,6 +234,9 @@
232234 #define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer VMMCALL to VMCALL */
233235 #define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */
234236 #define X86_FEATURE_EPT_AD ( 8*32+17) /* Intel Extended Page Table access-dirty bit */
237
+#define X86_FEATURE_VMCALL ( 8*32+18) /* "" Hypervisor supports the VMCALL instruction */
238
+#define X86_FEATURE_VMW_VMMCALL ( 8*32+19) /* "" VMware prefers VMMCALL hypercall instruction */
239
+#define X86_FEATURE_SEV_ES ( 8*32+20) /* AMD Secure Encrypted Virtualization - Encrypted State */
235240
236241 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
237242 #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
....@@ -239,12 +244,14 @@
239244 #define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */
240245 #define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */
241246 #define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */
247
+#define X86_FEATURE_FDP_EXCPTN_ONLY ( 9*32+ 6) /* "" FPU data pointer updated only on x87 exceptions */
242248 #define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */
243249 #define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */
244250 #define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB instructions */
245251 #define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */
246252 #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */
247253 #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */
254
+#define X86_FEATURE_ZERO_FCS_FDS ( 9*32+13) /* "" Zero out FPU CS and FPU DS */
248255 #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */
249256 #define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */
250257 #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */
....@@ -269,24 +276,46 @@
269276 #define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 instruction */
270277 #define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS instructions */
271278
272
-/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (EDX), word 11 */
273
-#define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */
279
+/*
280
+ * Extended auxiliary flags: Linux defined - for features scattered in various
281
+ * CPUID levels like 0xf, etc.
282
+ *
283
+ * Reuse free bits when adding new feature flags!
284
+ */
285
+#define X86_FEATURE_CQM_LLC (11*32+ 0) /* LLC QoS if 1 */
286
+#define X86_FEATURE_CQM_OCCUP_LLC (11*32+ 1) /* LLC occupancy monitoring */
287
+#define X86_FEATURE_CQM_MBM_TOTAL (11*32+ 2) /* LLC Total MBM monitoring */
288
+#define X86_FEATURE_CQM_MBM_LOCAL (11*32+ 3) /* LLC Local MBM monitoring */
289
+#define X86_FEATURE_FENCE_SWAPGS_USER (11*32+ 4) /* "" LFENCE in user entry SWAPGS path */
290
+#define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */
291
+#define X86_FEATURE_SPLIT_LOCK_DETECT (11*32+ 6) /* #AC for split lock */
292
+#define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */
293
+#define X86_FEATURE_ENTRY_IBPB (11*32+10) /* "" Issue an IBPB on kernel entry */
294
+#define X86_FEATURE_RRSBA_CTRL (11*32+11) /* "" RET prediction control */
295
+#define X86_FEATURE_RETPOLINE (11*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
296
+#define X86_FEATURE_RETPOLINE_LFENCE (11*32+13) /* "" Use LFENCE for Spectre variant 2 */
297
+#define X86_FEATURE_RETHUNK (11*32+14) /* "" Use REturn THUNK */
298
+#define X86_FEATURE_UNRET (11*32+15) /* "" AMD BTB untrain return */
299
+#define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM-Exit when EIBRS is enabled */
274300
275
-/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (EDX), word 12 */
276
-#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring */
277
-#define X86_FEATURE_CQM_MBM_TOTAL (12*32+ 1) /* LLC Total MBM monitoring */
278
-#define X86_FEATURE_CQM_MBM_LOCAL (12*32+ 2) /* LLC Local MBM monitoring */
301
+/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
302
+#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
279303
280304 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
281305 #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
282306 #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */
283307 #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */
308
+#define X86_FEATURE_RDPRU (13*32+ 4) /* Read processor register at user level */
309
+#define X86_FEATURE_WBNOINVD (13*32+ 9) /* WBNOINVD instruction */
284310 #define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */
285311 #define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */
286312 #define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */
313
+#define X86_FEATURE_AMD_STIBP_ALWAYS_ON (13*32+17) /* "" Single Thread Indirect Branch Predictors always-on preferred */
314
+#define X86_FEATURE_AMD_PPIN (13*32+23) /* Protected Processor Inventory Number */
287315 #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */
288316 #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */
289317 #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
318
+#define X86_FEATURE_BTC_NO (13*32+29) /* "" Not vulnerable to Branch Type Confusion */
290319
291320 /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
292321 #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
....@@ -320,6 +349,7 @@
320349 #define X86_FEATURE_UMIP (16*32+ 2) /* User Mode Instruction Protection */
321350 #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */
322351 #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */
352
+#define X86_FEATURE_WAITPKG (16*32+ 5) /* UMONITOR/UMWAIT/TPAUSE Instructions */
323353 #define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
324354 #define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */
325355 #define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */
....@@ -331,6 +361,9 @@
331361 #define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */
332362 #define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */
333363 #define X86_FEATURE_CLDEMOTE (16*32+25) /* CLDEMOTE instruction */
364
+#define X86_FEATURE_MOVDIRI (16*32+27) /* MOVDIRI instruction */
365
+#define X86_FEATURE_MOVDIR64B (16*32+28) /* MOVDIR64B instruction */
366
+#define X86_FEATURE_ENQCMD (16*32+29) /* ENQCMD and ENQCMDS instructions */
334367
335368 /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
336369 #define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* MCA overflow recovery support */
....@@ -340,11 +373,20 @@
340373 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
341374 #define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */
342375 #define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
376
+#define X86_FEATURE_FSRM (18*32+ 4) /* Fast Short Rep Mov */
377
+#define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* AVX-512 Intersect for D/Q */
378
+#define X86_FEATURE_SRBDS_CTRL (18*32+ 9) /* "" SRBDS mitigation MSR available */
379
+#define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */
380
+#define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */
381
+#define X86_FEATURE_SERIALIZE (18*32+14) /* SERIALIZE instruction */
382
+#define X86_FEATURE_TSXLDTRK (18*32+16) /* TSX Suspend Load Address Tracking */
343383 #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */
384
+#define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */
344385 #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
345386 #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
346387 #define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */
347388 #define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
389
+#define X86_FEATURE_CORE_CAPABILITIES (18*32+30) /* "" IA32_CORE_CAPABILITIES MSR */
348390 #define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */
349391
350392 /*
....@@ -377,5 +419,13 @@
377419 #define X86_BUG_SPECTRE_V2 X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */
378420 #define X86_BUG_SPEC_STORE_BYPASS X86_BUG(17) /* CPU is affected by speculative store bypass attack */
379421 #define X86_BUG_L1TF X86_BUG(18) /* CPU is affected by L1 Terminal Fault */
422
+#define X86_BUG_MDS X86_BUG(19) /* CPU is affected by Microarchitectural data sampling */
423
+#define X86_BUG_MSBDS_ONLY X86_BUG(20) /* CPU is only affected by the MSDBS variant of BUG_MDS */
424
+#define X86_BUG_SWAPGS X86_BUG(21) /* CPU is affected by speculation through SWAPGS */
425
+#define X86_BUG_TAA X86_BUG(22) /* CPU is affected by TSX Async Abort(TAA) */
426
+#define X86_BUG_ITLB_MULTIHIT X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */
427
+#define X86_BUG_SRBDS X86_BUG(24) /* CPU may leak RNG bits if not mitigated */
428
+#define X86_BUG_MMIO_STALE_DATA X86_BUG(25) /* CPU is affected by Processor MMIO Stale Data vulnerabilities */
429
+#define X86_BUG_RETBLEED X86_BUG(26) /* CPU is affected by RETBleed */
380430
381431 #endif /* _ASM_X86_CPUFEATURES_H */