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96 | 96 | #define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in IA32 userspace */ |
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97 | 97 | #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */ |
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98 | 98 | #define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */ |
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99 | | -#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" MFENCE synchronizes RDTSC */ |
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| 99 | +#define X86_FEATURE_SME_COHERENT ( 3*32+17) /* "" AMD hardware-enforced cache coherency */ |
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100 | 100 | #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */ |
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101 | 101 | #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ |
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102 | 102 | #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ |
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108 | 108 | #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* Extended APICID (8 bits) */ |
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109 | 109 | #define X86_FEATURE_AMD_DCM ( 3*32+27) /* AMD multi-node processor */ |
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110 | 110 | #define X86_FEATURE_APERFMPERF ( 3*32+28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */ |
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| 111 | +/* free ( 3*32+29) */ |
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111 | 112 | #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */ |
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112 | 113 | #define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */ |
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113 | 114 | |
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202 | 203 | #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ |
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203 | 204 | #define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */ |
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204 | 205 | #define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table Isolation enabled */ |
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205 | | -#define X86_FEATURE_RETPOLINE ( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */ |
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206 | | -#define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* "" AMD Retpoline mitigation for Spectre variant 2 */ |
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| 206 | +#define X86_FEATURE_KERNEL_IBRS ( 7*32+12) /* "" Set/clear IBRS on kernel entry/exit */ |
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| 207 | +#define X86_FEATURE_RSB_VMEXIT ( 7*32+13) /* "" Fill RSB on VM-Exit */ |
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207 | 208 | #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ |
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208 | 209 | #define X86_FEATURE_CDP_L2 ( 7*32+15) /* Code and Data Prioritization L2 */ |
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209 | 210 | #define X86_FEATURE_MSR_SPEC_CTRL ( 7*32+16) /* "" MSR SPEC_CTRL is implemented */ |
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218 | 219 | #define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */ |
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219 | 220 | #define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */ |
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220 | 221 | #define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */ |
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221 | | -#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */ |
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| 222 | +#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 or above (Zen) */ |
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222 | 223 | #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */ |
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223 | 224 | #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */ |
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| 225 | +#define X86_FEATURE_MSR_IA32_FEAT_CTL ( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */ |
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224 | 226 | |
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225 | 227 | /* Virtualization flags: Linux defined, word 8 */ |
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226 | 228 | #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ |
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232 | 234 | #define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer VMMCALL to VMCALL */ |
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233 | 235 | #define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */ |
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234 | 236 | #define X86_FEATURE_EPT_AD ( 8*32+17) /* Intel Extended Page Table access-dirty bit */ |
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| 237 | +#define X86_FEATURE_VMCALL ( 8*32+18) /* "" Hypervisor supports the VMCALL instruction */ |
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| 238 | +#define X86_FEATURE_VMW_VMMCALL ( 8*32+19) /* "" VMware prefers VMMCALL hypercall instruction */ |
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| 239 | +#define X86_FEATURE_SEV_ES ( 8*32+20) /* AMD Secure Encrypted Virtualization - Encrypted State */ |
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235 | 240 | |
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236 | 241 | /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */ |
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237 | 242 | #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/ |
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239 | 244 | #define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ |
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240 | 245 | #define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ |
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241 | 246 | #define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */ |
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| 247 | +#define X86_FEATURE_FDP_EXCPTN_ONLY ( 9*32+ 6) /* "" FPU data pointer updated only on x87 exceptions */ |
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242 | 248 | #define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */ |
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243 | 249 | #define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */ |
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244 | 250 | #define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB instructions */ |
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245 | 251 | #define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ |
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246 | 252 | #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ |
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247 | 253 | #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ |
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| 254 | +#define X86_FEATURE_ZERO_FCS_FDS ( 9*32+13) /* "" Zero out FPU CS and FPU DS */ |
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248 | 255 | #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ |
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249 | 256 | #define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */ |
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250 | 257 | #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ |
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269 | 276 | #define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 instruction */ |
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270 | 277 | #define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS instructions */ |
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271 | 278 | |
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272 | | -/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (EDX), word 11 */ |
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273 | | -#define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */ |
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| 279 | +/* |
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| 280 | + * Extended auxiliary flags: Linux defined - for features scattered in various |
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| 281 | + * CPUID levels like 0xf, etc. |
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| 282 | + * |
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| 283 | + * Reuse free bits when adding new feature flags! |
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| 284 | + */ |
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| 285 | +#define X86_FEATURE_CQM_LLC (11*32+ 0) /* LLC QoS if 1 */ |
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| 286 | +#define X86_FEATURE_CQM_OCCUP_LLC (11*32+ 1) /* LLC occupancy monitoring */ |
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| 287 | +#define X86_FEATURE_CQM_MBM_TOTAL (11*32+ 2) /* LLC Total MBM monitoring */ |
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| 288 | +#define X86_FEATURE_CQM_MBM_LOCAL (11*32+ 3) /* LLC Local MBM monitoring */ |
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| 289 | +#define X86_FEATURE_FENCE_SWAPGS_USER (11*32+ 4) /* "" LFENCE in user entry SWAPGS path */ |
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| 290 | +#define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */ |
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| 291 | +#define X86_FEATURE_SPLIT_LOCK_DETECT (11*32+ 6) /* #AC for split lock */ |
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| 292 | +#define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */ |
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| 293 | +#define X86_FEATURE_ENTRY_IBPB (11*32+10) /* "" Issue an IBPB on kernel entry */ |
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| 294 | +#define X86_FEATURE_RRSBA_CTRL (11*32+11) /* "" RET prediction control */ |
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| 295 | +#define X86_FEATURE_RETPOLINE (11*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */ |
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| 296 | +#define X86_FEATURE_RETPOLINE_LFENCE (11*32+13) /* "" Use LFENCE for Spectre variant 2 */ |
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| 297 | +#define X86_FEATURE_RETHUNK (11*32+14) /* "" Use REturn THUNK */ |
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| 298 | +#define X86_FEATURE_UNRET (11*32+15) /* "" AMD BTB untrain return */ |
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| 299 | +#define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM-Exit when EIBRS is enabled */ |
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274 | 300 | |
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275 | | -/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (EDX), word 12 */ |
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276 | | -#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring */ |
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277 | | -#define X86_FEATURE_CQM_MBM_TOTAL (12*32+ 1) /* LLC Total MBM monitoring */ |
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278 | | -#define X86_FEATURE_CQM_MBM_LOCAL (12*32+ 2) /* LLC Local MBM monitoring */ |
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| 301 | +/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ |
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| 302 | +#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ |
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279 | 303 | |
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280 | 304 | /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ |
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281 | 305 | #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ |
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282 | 306 | #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ |
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283 | 307 | #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ |
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| 308 | +#define X86_FEATURE_RDPRU (13*32+ 4) /* Read processor register at user level */ |
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| 309 | +#define X86_FEATURE_WBNOINVD (13*32+ 9) /* WBNOINVD instruction */ |
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284 | 310 | #define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */ |
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285 | 311 | #define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */ |
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286 | 312 | #define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */ |
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| 313 | +#define X86_FEATURE_AMD_STIBP_ALWAYS_ON (13*32+17) /* "" Single Thread Indirect Branch Predictors always-on preferred */ |
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| 314 | +#define X86_FEATURE_AMD_PPIN (13*32+23) /* Protected Processor Inventory Number */ |
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287 | 315 | #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */ |
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288 | 316 | #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ |
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289 | 317 | #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ |
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| 318 | +#define X86_FEATURE_BTC_NO (13*32+29) /* "" Not vulnerable to Branch Type Confusion */ |
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290 | 319 | |
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291 | 320 | /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ |
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292 | 321 | #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ |
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320 | 349 | #define X86_FEATURE_UMIP (16*32+ 2) /* User Mode Instruction Protection */ |
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321 | 350 | #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ |
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322 | 351 | #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ |
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| 352 | +#define X86_FEATURE_WAITPKG (16*32+ 5) /* UMONITOR/UMWAIT/TPAUSE Instructions */ |
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323 | 353 | #define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */ |
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324 | 354 | #define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */ |
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325 | 355 | #define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */ |
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331 | 361 | #define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */ |
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332 | 362 | #define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */ |
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333 | 363 | #define X86_FEATURE_CLDEMOTE (16*32+25) /* CLDEMOTE instruction */ |
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| 364 | +#define X86_FEATURE_MOVDIRI (16*32+27) /* MOVDIRI instruction */ |
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| 365 | +#define X86_FEATURE_MOVDIR64B (16*32+28) /* MOVDIR64B instruction */ |
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| 366 | +#define X86_FEATURE_ENQCMD (16*32+29) /* ENQCMD and ENQCMDS instructions */ |
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334 | 367 | |
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335 | 368 | /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */ |
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336 | 369 | #define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* MCA overflow recovery support */ |
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340 | 373 | /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ |
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341 | 374 | #define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */ |
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342 | 375 | #define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */ |
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| 376 | +#define X86_FEATURE_FSRM (18*32+ 4) /* Fast Short Rep Mov */ |
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| 377 | +#define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* AVX-512 Intersect for D/Q */ |
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| 378 | +#define X86_FEATURE_SRBDS_CTRL (18*32+ 9) /* "" SRBDS mitigation MSR available */ |
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| 379 | +#define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */ |
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| 380 | +#define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */ |
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| 381 | +#define X86_FEATURE_SERIALIZE (18*32+14) /* SERIALIZE instruction */ |
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| 382 | +#define X86_FEATURE_TSXLDTRK (18*32+16) /* TSX Suspend Load Address Tracking */ |
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343 | 383 | #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */ |
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| 384 | +#define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */ |
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344 | 385 | #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */ |
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345 | 386 | #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */ |
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346 | 387 | #define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */ |
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347 | 388 | #define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */ |
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| 389 | +#define X86_FEATURE_CORE_CAPABILITIES (18*32+30) /* "" IA32_CORE_CAPABILITIES MSR */ |
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348 | 390 | #define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */ |
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349 | 391 | |
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350 | 392 | /* |
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377 | 419 | #define X86_BUG_SPECTRE_V2 X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */ |
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378 | 420 | #define X86_BUG_SPEC_STORE_BYPASS X86_BUG(17) /* CPU is affected by speculative store bypass attack */ |
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379 | 421 | #define X86_BUG_L1TF X86_BUG(18) /* CPU is affected by L1 Terminal Fault */ |
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| 422 | +#define X86_BUG_MDS X86_BUG(19) /* CPU is affected by Microarchitectural data sampling */ |
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| 423 | +#define X86_BUG_MSBDS_ONLY X86_BUG(20) /* CPU is only affected by the MSDBS variant of BUG_MDS */ |
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| 424 | +#define X86_BUG_SWAPGS X86_BUG(21) /* CPU is affected by speculation through SWAPGS */ |
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| 425 | +#define X86_BUG_TAA X86_BUG(22) /* CPU is affected by TSX Async Abort(TAA) */ |
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| 426 | +#define X86_BUG_ITLB_MULTIHIT X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */ |
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| 427 | +#define X86_BUG_SRBDS X86_BUG(24) /* CPU may leak RNG bits if not mitigated */ |
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| 428 | +#define X86_BUG_MMIO_STALE_DATA X86_BUG(25) /* CPU is affected by Processor MMIO Stale Data vulnerabilities */ |
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| 429 | +#define X86_BUG_RETBLEED X86_BUG(26) /* CPU is affected by RETBleed */ |
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380 | 430 | |
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381 | 431 | #endif /* _ASM_X86_CPUFEATURES_H */ |
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