.. | .. |
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131 | 131 | struct { |
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132 | 132 | __u8 serror_pending; |
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133 | 133 | __u8 serror_has_esr; |
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| 134 | + __u8 ext_dabt_pending; |
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134 | 135 | /* Align it to 8 bytes */ |
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135 | | - __u8 pad[6]; |
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| 136 | + __u8 pad[5]; |
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136 | 137 | __u64 serror_esr; |
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137 | 138 | } exception; |
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138 | 139 | __u32 reserved[12]; |
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.. | .. |
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214 | 215 | #define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM | KVM_REG_SIZE_U64 | \ |
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215 | 216 | KVM_REG_ARM_FW | ((r) & 0xffff)) |
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216 | 217 | #define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0) |
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| 218 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1) |
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| 219 | + /* Higher values mean better protection. */ |
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| 220 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0 |
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| 221 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL 1 |
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| 222 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED 2 |
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| 223 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2) |
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| 224 | + /* Higher values mean better protection. */ |
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| 225 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0 |
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| 226 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN 1 |
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| 227 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL 2 |
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| 228 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3 |
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| 229 | +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4) |
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217 | 230 | |
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218 | 231 | /* Device Control API: ARM VGIC */ |
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219 | 232 | #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 |
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254 | 267 | #define KVM_DEV_ARM_ITS_CTRL_RESET 4 |
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255 | 268 | |
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256 | 269 | /* KVM_IRQ_LINE irq field index values */ |
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| 270 | +#define KVM_ARM_IRQ_VCPU2_SHIFT 28 |
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| 271 | +#define KVM_ARM_IRQ_VCPU2_MASK 0xf |
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257 | 272 | #define KVM_ARM_IRQ_TYPE_SHIFT 24 |
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258 | | -#define KVM_ARM_IRQ_TYPE_MASK 0xff |
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| 273 | +#define KVM_ARM_IRQ_TYPE_MASK 0xf |
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259 | 274 | #define KVM_ARM_IRQ_VCPU_SHIFT 16 |
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260 | 275 | #define KVM_ARM_IRQ_VCPU_MASK 0xff |
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261 | 276 | #define KVM_ARM_IRQ_NUM_SHIFT 0 |
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