forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f 
 kernel/sound/soc/rockchip/rockchip_sai.c
....@@ -22,6 +22,7 @@
2222 
2323 #define DRV_NAME		"rockchip-sai"
2424 
25
+#define CLK_SHIFT_RATE_HZ_MAX	1 /* 1 Hz */
2526 #define FW_RATIO_MAX		8
2627 #define FW_RATIO_MIN		1
2728 #define MAXBURST_PER_FIFO	8
....@@ -496,9 +497,10 @@
496497 		if (sai->is_clk_auto)
497498 			clk_set_rate(sai->mclk, bclk_rate);
498499 		mclk_rate = clk_get_rate(sai->mclk);
499
-		if (mclk_rate < bclk_rate) {
500
-			dev_err(sai->dev, "Mismatch mclk: %u, expected %u at least\n",
501
-				mclk_rate, bclk_rate);
500
+		if (mclk_rate < bclk_rate - CLK_SHIFT_RATE_HZ_MAX ||
501
+		    mclk_rate > bclk_rate + CLK_SHIFT_RATE_HZ_MAX) {
502
+			dev_err(sai->dev, "Mismatch mclk: %u, expected %u (+/- %dHz)\n",
503
+				mclk_rate, bclk_rate, CLK_SHIFT_RATE_HZ_MAX);
502504 			return -EINVAL;
503505 		}
504506 
....@@ -506,6 +508,17 @@
506508 
507509 		regmap_update_bits(sai->regmap, SAI_CKR, SAI_CKR_MDIV_MASK,
508510 				   SAI_CKR_MDIV(div_bclk));
511
+	}
512
+
513
+	return 0;
514
+}
515
+
516
+static int rockchip_sai_prepare(struct snd_pcm_substream *substream,
517
+				struct snd_soc_dai *dai)
518
+{
519
+	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
520
+
521
+	if (sai->is_master_mode) {
509522 		/*
510523 		 * Should wait for one BCLK ready after DIV and then ungate
511524 		 * output clk to achieve the clean clk.
....@@ -628,6 +641,7 @@
628641 	.hw_params = rockchip_sai_hw_params,
629642 	.set_sysclk = rockchip_sai_set_sysclk,
630643 	.set_fmt = rockchip_sai_set_fmt,
644
+	.prepare = rockchip_sai_prepare,
631645 	.trigger = rockchip_sai_trigger,
632646 	.set_tdm_slot = rockchip_sai_set_tdm_slot,
633647 };
....@@ -783,8 +797,8 @@
783797 	if (sai->has_playback) {
784798 		dai->playback.stream_name = "Playback";
785799 		dai->playback.channels_min = 1;
786
-		dai->playback.channels_max = 128;
787
-		dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
800
+		dai->playback.channels_max = 512;
801
+		dai->playback.rates = SNDRV_PCM_RATE_8000_384000;
788802 		dai->playback.formats = SNDRV_PCM_FMTBIT_S8 |
789803 					SNDRV_PCM_FMTBIT_S16_LE |
790804 					SNDRV_PCM_FMTBIT_S24_LE |
....@@ -799,8 +813,8 @@
799813 	if (sai->has_capture) {
800814 		dai->capture.stream_name = "Capture";
801815 		dai->capture.channels_min = 1;
802
-		dai->capture.channels_max = 128;
803
-		dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
816
+		dai->capture.channels_max = 512;
817
+		dai->capture.rates = SNDRV_PCM_RATE_8000_384000;
804818 		dai->capture.formats = SNDRV_PCM_FMTBIT_S8 |
805819 				       SNDRV_PCM_FMTBIT_S16_LE |
806820 				       SNDRV_PCM_FMTBIT_S24_LE |
....@@ -855,14 +869,14 @@
855869 	"From SDO0", "From SDO1", "From SDO2", "From SDO3" };
856870 
857871 static const char * const lps_text[] = { "Disable", "Enable" };
858
-static const char * const sync_out_text[] = { "External", "Internal" };
859
-static const char * const sync_in_text[] = { "External", "Internal" };
872
+static const char * const sync_out_text[] = { "From CRU", "From IO" };
873
+static const char * const sync_in_text[] = { "From IO", "From Sync Port" };
860874 
861875 static const char * const rpaths_text[] = {
862876 	"From SDI0", "From SDI1", "From SDI2", "From SDI3" };
863877 
864878 static const char * const tpaths_text[] = {
865
-	"To SDO0", "To SDO1", "To SDO2", "To SDO3" };
879
+	"From PATH0", "From PATH1", "From PATH2", "From PATH3" };
866880 
867881 /* TXCR */
868882 static SOC_ENUM_SINGLE_DECL(tsft_enum, SAI_TXCR, 22, edge_shift_text);
....@@ -919,8 +933,8 @@
919933 static SOC_ENUM_SINGLE_DECL(tpath1_enum, SAI_PATH_SEL, 2, tpaths_text);
920934 static SOC_ENUM_SINGLE_DECL(tpath0_enum, SAI_PATH_SEL, 0, tpaths_text);
921935 
922
-static int rockchip_sai_fpw_get(struct snd_kcontrol *kcontrol,
923
-				struct snd_ctl_elem_value *ucontrol)
936
+static int __maybe_unused rockchip_sai_fpw_get(struct snd_kcontrol *kcontrol,
937
+					       struct snd_ctl_elem_value *ucontrol)
924938 {
925939 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
926940 	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
....@@ -930,8 +944,8 @@
930944 	return 0;
931945 }
932946 
933
-static int rockchip_sai_fpw_put(struct snd_kcontrol *kcontrol,
934
-				struct snd_ctl_elem_value *ucontrol)
947
+static int __maybe_unused rockchip_sai_fpw_put(struct snd_kcontrol *kcontrol,
948
+					       struct snd_ctl_elem_value *ucontrol)
935949 {
936950 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
937951 	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
....@@ -946,8 +960,8 @@
946960 	return 1;
947961 }
948962 
949
-static int rockchip_sai_fw_ratio_get(struct snd_kcontrol *kcontrol,
950
-				     struct snd_ctl_elem_value *ucontrol)
963
+static int __maybe_unused rockchip_sai_fw_ratio_get(struct snd_kcontrol *kcontrol,
964
+						    struct snd_ctl_elem_value *ucontrol)
951965 {
952966 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
953967 	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
....@@ -957,8 +971,8 @@
957971 	return 0;
958972 }
959973 
960
-static int rockchip_sai_fw_ratio_put(struct snd_kcontrol *kcontrol,
961
-				     struct snd_ctl_elem_value *ucontrol)
974
+static int __maybe_unused rockchip_sai_fw_ratio_put(struct snd_kcontrol *kcontrol,
975
+						    struct snd_ctl_elem_value *ucontrol)
962976 {
963977 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
964978 	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
....@@ -1026,8 +1040,8 @@
10261040 	return 1;
10271041 }
10281042 
1029
-static int rockchip_sai_mss_get(struct snd_kcontrol *kcontrol,
1030
-				struct snd_ctl_elem_value *ucontrol)
1043
+static int __maybe_unused rockchip_sai_mss_get(struct snd_kcontrol *kcontrol,
1044
+					       struct snd_ctl_elem_value *ucontrol)
10311045 {
10321046 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
10331047 	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
....@@ -1037,8 +1051,8 @@
10371051 	return 0;
10381052 }
10391053 
1040
-static int rockchip_sai_mss_put(struct snd_kcontrol *kcontrol,
1041
-				struct snd_ctl_elem_value *ucontrol)
1054
+static int __maybe_unused rockchip_sai_mss_put(struct snd_kcontrol *kcontrol,
1055
+					       struct snd_ctl_elem_value *ucontrol)
10421056 {
10431057 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
10441058 	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
....@@ -1174,21 +1188,17 @@
11741188 	.info = rockchip_sai_wait_time_info,			\
11751189 	.get = xhandler_get, .put = xhandler_put }
11761190 
1177
-static DECLARE_TLV_DB_SCALE(fs_shift_tlv, 0, 8192, 0);
1191
+static __maybe_unused DECLARE_TLV_DB_SCALE(fs_shift_tlv, 0, 8192, 0);
11781192 
11791193 static const struct snd_kcontrol_new rockchip_sai_controls[] = {
1180
-
1194
+#ifdef CONFIG_SND_SOC_ROCKCHIP_SAI_VERBOSE
11811195 	SOC_ENUM("Transmit Edge Shift", tsft_enum),
1182
-	SOC_ENUM_EXT("Transmit SDOx Select", tx_lanes_enum,
1183
-		     rockchip_sai_tx_lanes_get, rockchip_sai_tx_lanes_put),
11841196 	SOC_ENUM("Transmit Store Justified Mode", tsjm_enum),
11851197 	SOC_ENUM("Transmit First Bit Mode", tfbm_enum),
11861198 	SOC_ENUM("Transmit Valid Data Justified", tvdj_enum),
11871199 	SOC_ENUM("Transmit Slot Bit Width", tsbw_enum),
11881200 
11891201 	SOC_ENUM("Receive Edge Shift", rsft_enum),
1190
-	SOC_ENUM_EXT("Receive SDIx Select", rx_lanes_enum,
1191
-		     rockchip_sai_rx_lanes_get, rockchip_sai_rx_lanes_put),
11921202 	SOC_ENUM("Receive Store Justified Mode", rsjm_enum),
11931203 	SOC_ENUM("Receive First Bit Mode", rfbm_enum),
11941204 	SOC_ENUM("Receive Valid Data Justified", rvdj_enum),
....@@ -1200,15 +1210,24 @@
12001210 	SOC_ENUM_EXT("Frame Width Ratio", fw_ratio_enum,
12011211 		     rockchip_sai_fw_ratio_get, rockchip_sai_fw_ratio_put),
12021212 
1213
+	SOC_ENUM_EXT("Master Slave Mode Select", mss_switch,
1214
+		     rockchip_sai_mss_get, rockchip_sai_mss_put),
1215
+	SOC_ENUM("Sclk Polarity", sp_switch),
1216
+	SOC_ENUM("Frame Sync Polarity", fp_switch),
1217
+
1218
+	SOC_SINGLE_TLV("Transmit Frame Shift Select", SAI_TX_SHIFT,
1219
+		       0, 8192, 0, fs_shift_tlv),
1220
+	SOC_SINGLE_TLV("Receive Frame Shift Select", SAI_RX_SHIFT,
1221
+		       0, 8192, 0, fs_shift_tlv),
1222
+#endif
1223
+	SOC_ENUM_EXT("Transmit SDOx Select", tx_lanes_enum,
1224
+		     rockchip_sai_tx_lanes_get, rockchip_sai_tx_lanes_put),
1225
+	SOC_ENUM_EXT("Receive SDIx Select", rx_lanes_enum,
1226
+		     rockchip_sai_rx_lanes_get, rockchip_sai_rx_lanes_put),
12031227 	SOC_SINGLE_TLV("Receive Mono Slot Select", SAI_MONO_CR,
12041228 		       2, 128, 0, rmss_tlv),
12051229 	SOC_ENUM("Receive Mono Switch", rmono_switch),
12061230 	SOC_ENUM("Transmit Mono Switch", tmono_switch),
1207
-
1208
-	SOC_ENUM_EXT("Master / Slave Mode Select", mss_switch,
1209
-		     rockchip_sai_mss_get, rockchip_sai_mss_put),
1210
-	SOC_ENUM("Sclk Polarity", sp_switch),
1211
-	SOC_ENUM("Frame Sync Polarity", fp_switch),
12121231 
12131232 	SOC_ENUM("SDI3 Loopback Src Select", lp3_enum),
12141233 	SOC_ENUM("SDI2 Loopback Src Select", lp2_enum),
....@@ -1224,15 +1243,10 @@
12241243 	SOC_ENUM("Receive PATH2 Source Select", rpath2_enum),
12251244 	SOC_ENUM("Receive PATH1 Source Select", rpath1_enum),
12261245 	SOC_ENUM("Receive PATH0 Source Select", rpath0_enum),
1227
-	SOC_ENUM("Transmit PATH3 Sink Select", tpath3_enum),
1228
-	SOC_ENUM("Transmit PATH2 Sink Select", tpath2_enum),
1229
-	SOC_ENUM("Transmit PATH1 Sink Select", tpath1_enum),
1230
-	SOC_ENUM("Transmit PATH0 Sink Select", tpath0_enum),
1231
-
1232
-	SOC_SINGLE_TLV("Transmit Frame Shift Select", SAI_TX_SHIFT,
1233
-		       0, 8192, 0, fs_shift_tlv),
1234
-	SOC_SINGLE_TLV("Receive Frame Shift Select", SAI_RX_SHIFT,
1235
-		       0, 8192, 0, fs_shift_tlv),
1246
+	SOC_ENUM("Transmit SDO3 Source Select", tpath3_enum),
1247
+	SOC_ENUM("Transmit SDO2 Source Select", tpath2_enum),
1248
+	SOC_ENUM("Transmit SDO1 Source Select", tpath1_enum),
1249
+	SOC_ENUM("Transmit SDO0 Source Select", tpath0_enum),
12361250 
12371251 	SOC_SINGLE_BOOL_EXT("Clk Auto Switch", 0,
12381252 			    rockchip_sai_clk_auto_get,
....@@ -1263,6 +1277,9 @@
12631277 		dev_warn_ratelimited(sai->dev, "TX FIFO Underrun\n");
12641278 		regmap_update_bits(sai->regmap, SAI_INTCR,
12651279 				   SAI_INTCR_TXUIC, SAI_INTCR_TXUIC);
1280
+		regmap_update_bits(sai->regmap, SAI_INTCR,
1281
+				   SAI_INTCR_TXUIE_MASK,
1282
+				   SAI_INTCR_TXUIE(0));
12661283 		substream = sai->substreams[SNDRV_PCM_STREAM_PLAYBACK];
12671284 		if (substream)
12681285 			snd_pcm_stop_xrun(substream);
....@@ -1272,6 +1289,9 @@
12721289 		dev_warn_ratelimited(sai->dev, "RX FIFO Overrun\n");
12731290 		regmap_update_bits(sai->regmap, SAI_INTCR,
12741291 				   SAI_INTCR_RXOIC, SAI_INTCR_RXOIC);
1292
+		regmap_update_bits(sai->regmap, SAI_INTCR,
1293
+				   SAI_INTCR_RXOIE_MASK,
1294
+				   SAI_INTCR_RXOIE(0));
12751295 		substream = sai->substreams[SNDRV_PCM_STREAM_CAPTURE];
12761296 		if (substream)
12771297 			snd_pcm_stop_xrun(substream);
....@@ -1386,16 +1406,26 @@
13861406 	if (ret)
13871407 		return ret;
13881408 
1409
+	ret = rockchip_sai_init_dai(sai, res, &dai);
1410
+	if (ret)
1411
+		return ret;
1412
+
1413
+	/*
1414
+	 * MUST: after pm_runtime_enable step, any register R/W
1415
+	 * should be wrapped with pm_runtime_get_sync/put.
1416
+	 *
1417
+	 * Another approach is to enable the regcache true to
1418
+	 * avoid access HW registers.
1419
+	 *
1420
+	 * Alternatively, performing the registers R/W before
1421
+	 * pm_runtime_enable is also a good option.
1422
+	 */
13891423 	pm_runtime_enable(&pdev->dev);
13901424 	if (!pm_runtime_enabled(&pdev->dev)) {
13911425 		ret = rockchip_sai_runtime_resume(&pdev->dev);
13921426 		if (ret)
13931427 			goto err_runtime_disable;
13941428 	}
1395
-
1396
-	ret = rockchip_sai_init_dai(sai, res, &dai);
1397
-	if (ret)
1398
-		goto err_runtime_suspend;
13991429 
14001430 	ret = devm_snd_soc_register_component(&pdev->dev,
14011431 					      &rockchip_sai_component,
....@@ -1432,33 +1462,9 @@
14321462 	return 0;
14331463 }
14341464 
1435
-#ifdef CONFIG_PM_SLEEP
1436
-static int rockchip_sai_suspend(struct device *dev)
1437
-{
1438
-	struct rk_sai_dev *sai = dev_get_drvdata(dev);
1439
-
1440
-	regcache_mark_dirty(sai->regmap);
1441
-
1442
-	return 0;
1443
-}
1444
-
1445
-static int rockchip_sai_resume(struct device *dev)
1446
-{
1447
-	struct rk_sai_dev *sai = dev_get_drvdata(dev);
1448
-	int ret = pm_runtime_resume_and_get(dev);
1449
-
1450
-	if (ret < 0)
1451
-		return ret;
1452
-	ret = regcache_sync(sai->regmap);
1453
-	pm_runtime_put(dev);
1454
-
1455
-	return ret;
1456
-}
1457
-#endif /* CONFIG_PM_SLEEP */
1458
-
14591465 static const struct dev_pm_ops rockchip_sai_pm_ops = {
14601466 	SET_RUNTIME_PM_OPS(rockchip_sai_runtime_suspend, rockchip_sai_runtime_resume, NULL)
1461
-	SET_SYSTEM_SLEEP_PM_OPS(rockchip_sai_suspend, rockchip_sai_resume)
1467
+	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
14621468 };
14631469 
14641470 static struct platform_driver rockchip_sai_driver = {