~hc/RK356X_SDK_RELEASE.git

..	..	@@ -19,6 +19,7 @@
19	19	#include <linux/clk.h>
20	20	#include <linux/clk-provider.h>
21	21	#include <linux/clk/rockchip.h>
	22	+#include <linux/pinctrl/consumer.h>
22	23	#include <linux/pm_runtime.h>
23	24	#include <linux/regmap.h>
24	25	#include <linux/reset.h>
..	..	@@ -35,6 +36,34 @@
35	36	#define HAVE_SYNC_RESET
36	37	#endif
37	38
	39	+#ifdef CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES
	40	+/*
	41	+ * Example: RK3588
	42	+ *
	43	+ * Use I2S2_2CH as Clk-Gen to serve TDM_MULTI_LANES
	44	+ *
	45	+ * I2S2_2CH ----> BCLK,I2S_LRCK --------> I2S0_8CH_TX (Slave TRCM-TXONLY)
	46	+ * \|
	47	+ * \|--------> BCLK,TDM_SYNC --------> TDM Device (Slave)
	48	+ *
	49	+ * Note:
	50	+ *
	51	+ * I2S2_2CH_MCLK: BCLK
	52	+ * I2S2_2CH_SCLK: I2S_LRCK (GPIO2_B7)
	53	+ * I2S2_2CH_LRCK: TDM_SYNC (GPIO2_C0)
	54	+ *
	55	+ */
	56	+
	57	+#define CLK_MAX_COUNT 1000
	58	+#define NSAMPLES 4
	59	+#define XFER_EN 0x3
	60	+#define XFER_DIS 0x0
	61	+#define CKR_V(m, r, t) ((m - 1) << 16 \| (r - 1) << 8 \| (t - 1) << 0)
	62	+#define I2S_XCR_IBM_V(v) ((v) & I2S_TXCR_IBM_MASK)
	63	+#define I2S_XCR_IBM_NORMAL I2S_TXCR_IBM_NORMAL
	64	+#define I2S_XCR_IBM_LSJM I2S_TXCR_IBM_LSJM
	65	+#endif
	66	+
38	67	#define DEFAULT_MCLK_FS 256
39	68	#define DEFAULT_FS 48000
40	69	#define CH_GRP_MAX 4 /* The max channel 8 / 2 */
..	..	@@ -42,6 +71,7 @@
42	71	#define CLK_PPM_MIN (-1000)
43	72	#define CLK_PPM_MAX (1000)
44	73	#define MAXBURST_PER_FIFO 8
	74	+#define WAIT_TIME_MS_MAX 10000
45	75
46	76	#define QUIRK_ALWAYS_ON BIT(0)
47	77	#define QUIRK_HDMI_PATH BIT(1)
..	..	@@ -86,8 +116,11 @@
86	116	struct snd_dmaengine_dai_dma_data capture_dma_data;
87	117	struct snd_dmaengine_dai_dma_data playback_dma_data;
88	118	struct snd_pcm_substream *substreams[SNDRV_PCM_STREAM_LAST + 1];
	119	+ unsigned int wait_time[SNDRV_PCM_STREAM_LAST + 1];
89	120	struct reset_control *tx_reset;
90	121	struct reset_control *rx_reset;
	122	+ struct pinctrl *pinctrl;
	123	+ struct pinctrl_state *clk_state;
91	124	const struct rk_i2s_soc_data *soc_data;
92	125	#ifdef HAVE_SYNC_RESET
93	126	void __iomem *cru_base;
..	..	@@ -99,6 +132,7 @@
99	132	bool mclk_calibrate;
100	133	bool tdm_mode;
101	134	bool tdm_fsync_half_frame;
	135	+ bool is_dma_active[SNDRV_PCM_STREAM_LAST + 1];
102	136	unsigned int mclk_rx_freq;
103	137	unsigned int mclk_tx_freq;
104	138	unsigned int mclk_root0_freq;
..	..	@@ -110,9 +144,19 @@
110	144	unsigned int i2s_sdis[CH_GRP_MAX];
111	145	unsigned int i2s_sdos[CH_GRP_MAX];
112	146	unsigned int quirks;
	147	+ unsigned int lrck_ratio;
113	148	int clk_ppm;
114	149	atomic_t refcount;
115	150	spinlock_t lock; /* xfer lock */
	151	+#ifdef CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES
	152	+ struct snd_soc_dai *clk_src_dai;
	153	+ struct gpio_desc *i2s_lrck_gpio;
	154	+ struct gpio_desc *tdm_fsync_gpio;
	155	+ unsigned int tx_lanes;
	156	+ unsigned int rx_lanes;
	157	+ void __iomem *clk_src_base;
	158	+ bool is_tdm_multi_lanes;
	159	+#endif
116	160	};
117	161
118	162	static struct i2s_of_quirks {
..	..	@@ -160,6 +204,20 @@
160	204	clk_disable_unprepare(i2s_tdm->mclk_tx);
161	205	clk_disable_unprepare(i2s_tdm->mclk_rx);
162	206
	207	+ pinctrl_pm_select_idle_state(dev);
	208	+
	209	+ return 0;
	210	+}
	211	+
	212	+static int rockchip_i2s_tdm_pinctrl_select_clk_state(struct device *dev)
	213	+{
	214	+ struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
	215	+
	216	+ if (IS_ERR_OR_NULL(i2s_tdm->pinctrl) \|\| !i2s_tdm->clk_state)
	217	+ return 0;
	218	+
	219	+ pinctrl_select_state(i2s_tdm->pinctrl, i2s_tdm->clk_state);
	220	+
163	221	return 0;
164	222	}
165	223
..	..	@@ -167,6 +225,13 @@
167	225	{
168	226	struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
169	227	int ret;
	228	+
	229	+ /*
	230	+ * pinctrl default state is invoked by ASoC framework, so,
	231	+ * we just handle clk state here if DT assigned.
	232	+ */
	233	+ if (i2s_tdm->is_master_mode)
	234	+ rockchip_i2s_tdm_pinctrl_select_clk_state(dev);
170	235
171	236	ret = clk_prepare_enable(i2s_tdm->mclk_tx);
172	237	if (ret)
..	..	@@ -181,6 +246,13 @@
181	246	ret = regcache_sync(i2s_tdm->regmap);
182	247	if (ret)
183	248	goto err_regmap;
	249	+
	250	+ /*
	251	+ * should be placed after regcache sync done to back
	252	+ * to the slave mode and then enable clk state.
	253	+ */
	254	+ if (!i2s_tdm->is_master_mode)
	255	+ rockchip_i2s_tdm_pinctrl_select_clk_state(dev);
184	256
185	257	return 0;
186	258
..	..	@@ -207,6 +279,18 @@
207	279	return (val & I2S_XFER_TXS_START);
208	280	else
209	281	return (val & I2S_XFER_RXS_START);
	282	+}
	283	+
	284	+static inline bool is_dma_active(struct rk_i2s_tdm_dev *i2s_tdm, int stream)
	285	+{
	286	+ unsigned int val;
	287	+
	288	+ regmap_read(i2s_tdm->regmap, I2S_DMACR, &val);
	289	+
	290	+ if (stream == SNDRV_PCM_STREAM_PLAYBACK)
	291	+ return (val & I2S_DMACR_TDE_MASK);
	292	+ else
	293	+ return (val & I2S_DMACR_RDE_MASK);
210	294	}
211	295
212	296	#ifdef HAVE_SYNC_RESET
..	..	@@ -515,9 +599,289 @@
515	599	rockchip_i2s_tdm_fifo_xrun_detect(i2s_tdm, stream, 1);
516	600	}
517	601
	602	+#ifdef CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES
	603	+static const char * const tx_lanes_text[] = { "Auto", "SDOx1", "SDOx2", "SDOx3", "SDOx4" };
	604	+static const char * const rx_lanes_text[] = { "Auto", "SDIx1", "SDIx2", "SDIx3", "SDIx4" };
	605	+static const struct soc_enum tx_lanes_enum =
	606	+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_lanes_text), tx_lanes_text);
	607	+static const struct soc_enum rx_lanes_enum =
	608	+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_lanes_text), rx_lanes_text);
	609	+
	610	+static int rockchip_i2s_tdm_tx_lanes_get(struct snd_kcontrol *kcontrol,
	611	+ struct snd_ctl_elem_value *ucontrol)
	612	+{
	613	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	614	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
	615	+
	616	+ ucontrol->value.enumerated.item[0] = i2s_tdm->tx_lanes;
	617	+
	618	+ return 0;
	619	+}
	620	+
	621	+static int rockchip_i2s_tdm_tx_lanes_put(struct snd_kcontrol *kcontrol,
	622	+ struct snd_ctl_elem_value *ucontrol)
	623	+{
	624	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	625	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
	626	+ int num;
	627	+
	628	+ num = ucontrol->value.enumerated.item[0];
	629	+ if (num >= ARRAY_SIZE(tx_lanes_text))
	630	+ return -EINVAL;
	631	+
	632	+ i2s_tdm->tx_lanes = num;
	633	+
	634	+ return 1;
	635	+}
	636	+
	637	+static int rockchip_i2s_tdm_rx_lanes_get(struct snd_kcontrol *kcontrol,
	638	+ struct snd_ctl_elem_value *ucontrol)
	639	+{
	640	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	641	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
	642	+
	643	+ ucontrol->value.enumerated.item[0] = i2s_tdm->rx_lanes;
	644	+
	645	+ return 0;
	646	+}
	647	+
	648	+static int rockchip_i2s_tdm_rx_lanes_put(struct snd_kcontrol *kcontrol,
	649	+ struct snd_ctl_elem_value *ucontrol)
	650	+{
	651	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	652	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
	653	+ int num;
	654	+
	655	+ num = ucontrol->value.enumerated.item[0];
	656	+ if (num >= ARRAY_SIZE(rx_lanes_text))
	657	+ return -EINVAL;
	658	+
	659	+ i2s_tdm->rx_lanes = num;
	660	+
	661	+ return 1;
	662	+}
	663	+
	664	+static int rockchip_i2s_tdm_get_lanes(struct rk_i2s_tdm_dev *i2s_tdm, int stream)
	665	+{
	666	+ unsigned int lanes = 1;
	667	+
	668	+ if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
	669	+ if (i2s_tdm->tx_lanes)
	670	+ lanes = i2s_tdm->tx_lanes;
	671	+ } else {
	672	+ if (i2s_tdm->rx_lanes)
	673	+ lanes = i2s_tdm->rx_lanes;
	674	+ }
	675	+
	676	+ return lanes;
	677	+}
	678	+
	679	+static struct snd_soc_dai rockchip_i2s_tdm_find_dai(struct device_node np)
	680	+{
	681	+ struct snd_soc_dai_link_component dai_component = { 0 };
	682	+
	683	+ dai_component.of_node = np;
	684	+
	685	+ return snd_soc_find_dai_with_mutex(&dai_component);
	686	+}
	687	+
	688	+static int rockchip_i2s_tdm_multi_lanes_set_clk(struct snd_pcm_substream *substream,
	689	+ struct snd_pcm_hw_params *params,
	690	+ struct snd_soc_dai *cpu_dai)
	691	+{
	692	+ struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
	693	+ struct snd_soc_dai *dai = i2s_tdm->clk_src_dai;
	694	+ unsigned int div, mclk_rate;
	695	+ unsigned int lanes, ch_per_lane;
	696	+
	697	+ lanes = rockchip_i2s_tdm_get_lanes(i2s_tdm, substream->stream);
	698	+ ch_per_lane = params_channels(params) / lanes;
	699	+ mclk_rate = ch_per_lane * params_rate(params) * 32;
	700	+ div = ch_per_lane / 2;
	701	+
	702	+ /* Do nothing when use external clk src */
	703	+ if (dai && dai->driver->ops) {
	704	+ if (dai->driver->ops->set_sysclk)
	705	+ dai->driver->ops->set_sysclk(dai, substream->stream, mclk_rate, 0);
	706	+
	707	+ writel(XFER_DIS, i2s_tdm->clk_src_base + I2S_XFER);
	708	+ writel(CKR_V(64, div, div), i2s_tdm->clk_src_base + I2S_CKR);
	709	+ writel(XFER_EN, i2s_tdm->clk_src_base + I2S_XFER);
	710	+ }
	711	+
	712	+ i2s_tdm->lrck_ratio = div;
	713	+ i2s_tdm->mclk_tx_freq = mclk_rate;
	714	+ i2s_tdm->mclk_rx_freq = mclk_rate;
	715	+
	716	+ return 0;
	717	+}
	718	+
	719	+static inline int tdm_multi_lanes_clk_assert_h(const struct gpio_desc *desc)
	720	+{
	721	+ int cnt = CLK_MAX_COUNT;
	722	+
	723	+ while (gpiod_get_raw_value(desc) && --cnt)
	724	+ ;
	725	+
	726	+ return cnt;
	727	+}
	728	+
	729	+static inline int tdm_multi_lanes_clk_assert_l(const struct gpio_desc *desc)
	730	+{
	731	+ int cnt = CLK_MAX_COUNT;
	732	+
	733	+ while (!gpiod_get_raw_value(desc) && --cnt)
	734	+ ;
	735	+
	736	+ return cnt;
	737	+}
	738	+
	739	+static inline bool rockchip_i2s_tdm_clk_valid(struct rk_i2s_tdm_dev *i2s_tdm)
	740	+{
	741	+ int dc_h = CLK_MAX_COUNT, dc_l = CLK_MAX_COUNT;
	742	+
	743	+ /*
	744	+ * TBD: optimize debounce and get value
	745	+ *
	746	+ * debounce at least one cycle found, otherwise, the clk ref maybe
	747	+ * not on the fly.
	748	+ */
	749	+
	750	+ /* check HIGH-Level */
	751	+ dc_h = tdm_multi_lanes_clk_assert_h(i2s_tdm->i2s_lrck_gpio);
	752	+ if (!dc_h)
	753	+ return false;
	754	+
	755	+ /* check LOW-Level */
	756	+ dc_l = tdm_multi_lanes_clk_assert_l(i2s_tdm->i2s_lrck_gpio);
	757	+ if (!dc_l)
	758	+ return false;
	759	+
	760	+ /* check HIGH-Level */
	761	+ dc_h = tdm_multi_lanes_clk_assert_h(i2s_tdm->tdm_fsync_gpio);
	762	+ if (!dc_h)
	763	+ return false;
	764	+
	765	+ /* check LOW-Level */
	766	+ dc_l = tdm_multi_lanes_clk_assert_l(i2s_tdm->tdm_fsync_gpio);
	767	+ if (!dc_l)
	768	+ return false;
	769	+
	770	+ return true;
	771	+}
	772	+
	773	+static void __maybe_unused rockchip_i2s_tdm_gpio_clk_meas(struct rk_i2s_tdm_dev *i2s_tdm,
	774	+ const struct gpio_desc *desc,
	775	+ const char *name)
	776	+{
	777	+ int h[NSAMPLES], l[NSAMPLES], i;
	778	+
	779	+ dev_dbg(i2s_tdm->dev, "%s:\n", name);
	780	+
	781	+ if (!rockchip_i2s_tdm_clk_valid(i2s_tdm))
	782	+ return;
	783	+
	784	+ for (i = 0; i < NSAMPLES; i++) {
	785	+ h[i] = tdm_multi_lanes_clk_assert_h(desc);
	786	+ l[i] = tdm_multi_lanes_clk_assert_l(desc);
	787	+ }
	788	+
	789	+ for (i = 0; i < NSAMPLES; i++)
	790	+ dev_dbg(i2s_tdm->dev, "H[%d]: %2d, L[%d]: %2d\n",
	791	+ i, CLK_MAX_COUNT - h[i], i, CLK_MAX_COUNT - l[i]);
	792	+}
	793	+
	794	+static int rockchip_i2s_tdm_multi_lanes_start(struct rk_i2s_tdm_dev *i2s_tdm, int stream)
	795	+{
	796	+ unsigned int tdm_h = 0, tdm_l = 0, i2s_h = 0, i2s_l = 0;
	797	+ unsigned int msk, val, reg, fmt;
	798	+ unsigned long flags;
	799	+
	800	+ if (!i2s_tdm->tdm_fsync_gpio \|\| !i2s_tdm->i2s_lrck_gpio)
	801	+ return -ENOSYS;
	802	+
	803	+ if (i2s_tdm->lrck_ratio != 4 && i2s_tdm->lrck_ratio != 8)
	804	+ return -EINVAL;
	805	+
	806	+ if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
	807	+ msk = I2S_XFER_TXS_MASK;
	808	+ val = I2S_XFER_TXS_START;
	809	+ reg = I2S_TXCR;
	810	+ } else {
	811	+ msk = I2S_XFER_RXS_MASK;
	812	+ val = I2S_XFER_RXS_START;
	813	+ reg = I2S_RXCR;
	814	+ }
	815	+
	816	+ regmap_read(i2s_tdm->regmap, reg, &fmt);
	817	+ fmt = I2S_XCR_IBM_V(fmt);
	818	+
	819	+ local_irq_save(flags);
	820	+
	821	+ if (!rockchip_i2s_tdm_clk_valid(i2s_tdm)) {
	822	+ local_irq_restore(flags);
	823	+ dev_err(i2s_tdm->dev, "Invalid LRCK / FSYNC measured by ref IO\n");
	824	+ return -EINVAL;
	825	+ }
	826	+
	827	+ switch (fmt) {
	828	+ case I2S_XCR_IBM_NORMAL:
	829	+ tdm_h = tdm_multi_lanes_clk_assert_h(i2s_tdm->tdm_fsync_gpio);
	830	+ tdm_l = tdm_multi_lanes_clk_assert_l(i2s_tdm->tdm_fsync_gpio);
	831	+
	832	+ if (i2s_tdm->lrck_ratio == 8) {
	833	+ tdm_multi_lanes_clk_assert_l(i2s_tdm->i2s_lrck_gpio);
	834	+ tdm_multi_lanes_clk_assert_h(i2s_tdm->i2s_lrck_gpio);
	835	+ tdm_multi_lanes_clk_assert_l(i2s_tdm->i2s_lrck_gpio);
	836	+ tdm_multi_lanes_clk_assert_h(i2s_tdm->i2s_lrck_gpio);
	837	+ }
	838	+
	839	+ i2s_l = tdm_multi_lanes_clk_assert_l(i2s_tdm->i2s_lrck_gpio);
	840	+
	841	+ if (stream == SNDRV_PCM_STREAM_CAPTURE)
	842	+ i2s_h = tdm_multi_lanes_clk_assert_h(i2s_tdm->i2s_lrck_gpio);
	843	+ break;
	844	+ case I2S_XCR_IBM_LSJM:
	845	+ tdm_l = tdm_multi_lanes_clk_assert_l(i2s_tdm->tdm_fsync_gpio);
	846	+ tdm_h = tdm_multi_lanes_clk_assert_h(i2s_tdm->tdm_fsync_gpio);
	847	+
	848	+ if (i2s_tdm->lrck_ratio == 8) {
	849	+ tdm_multi_lanes_clk_assert_h(i2s_tdm->i2s_lrck_gpio);
	850	+ tdm_multi_lanes_clk_assert_l(i2s_tdm->i2s_lrck_gpio);
	851	+ tdm_multi_lanes_clk_assert_h(i2s_tdm->i2s_lrck_gpio);
	852	+ tdm_multi_lanes_clk_assert_l(i2s_tdm->i2s_lrck_gpio);
	853	+ }
	854	+
	855	+ tdm_multi_lanes_clk_assert_h(i2s_tdm->i2s_lrck_gpio);
	856	+
	857	+ i2s_l = tdm_multi_lanes_clk_assert_l(i2s_tdm->i2s_lrck_gpio);
	858	+ i2s_h = tdm_multi_lanes_clk_assert_h(i2s_tdm->i2s_lrck_gpio);
	859	+ break;
	860	+ default:
	861	+ local_irq_restore(flags);
	862	+ return -EINVAL;
	863	+ }
	864	+
	865	+ regmap_update_bits(i2s_tdm->regmap, I2S_XFER, msk, val);
	866	+ local_irq_restore(flags);
	867	+
	868	+ dev_dbg(i2s_tdm->dev, "STREAM[%d]: TDM-H: %d, TDM-L: %d, I2S-H: %d, I2S-L: %d\n", stream,
	869	+ CLK_MAX_COUNT - tdm_h, CLK_MAX_COUNT - tdm_l,
	870	+ CLK_MAX_COUNT - i2s_h, CLK_MAX_COUNT - i2s_l);
	871	+
	872	+ return 0;
	873	+}
	874	+#endif
	875	+
518	876	static void rockchip_i2s_tdm_xfer_start(struct rk_i2s_tdm_dev *i2s_tdm,
519	877	int stream)
520	878	{
	879	+#ifdef CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES
	880	+ if (i2s_tdm->is_tdm_multi_lanes) {
	881	+ if (rockchip_i2s_tdm_multi_lanes_start(i2s_tdm, stream) != -ENOSYS)
	882	+ return;
	883	+ }
	884	+#endif
521	885	if (i2s_tdm->clk_trcm) {
522	886	rockchip_i2s_tdm_reset_assert(i2s_tdm);
523	887	regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
..	..	@@ -593,6 +957,9 @@
593	957	int stream = substream->stream;
594	958	int bstream = SNDRV_PCM_STREAM_LAST - stream;
595	959
	960	+ /* store the current state, prepare for resume if necessary */
	961	+ i2s_tdm->is_dma_active[bstream] = is_dma_active(i2s_tdm, bstream);
	962	+
596	963	/* disable dma for both tx and rx */
597	964	rockchip_i2s_tdm_dma_ctrl(i2s_tdm, stream, 0);
598	965	rockchip_i2s_tdm_dma_ctrl(i2s_tdm, bstream, 0);
..	..	@@ -608,7 +975,8 @@
608	975	* just resume bstream, because current stream will be
609	976	* startup in the trigger-cmd-START
610	977	*/
611		- rockchip_i2s_tdm_dma_ctrl(i2s_tdm, bstream, 1);
	978	+ if (i2s_tdm->is_dma_active[bstream])
	979	+ rockchip_i2s_tdm_dma_ctrl(i2s_tdm, bstream, 1);
612	980	rockchip_i2s_tdm_xfer_start(i2s_tdm, bstream);
613	981	}
614	982
..	..	@@ -1235,6 +1603,32 @@
1235	1603	unsigned int reg_fmt, fmt;
1236	1604	int ret = 0;
1237	1605
	1606	+#ifdef CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES
	1607	+ if (i2s_tdm->is_tdm_multi_lanes) {
	1608	+ unsigned int lanes = rockchip_i2s_tdm_get_lanes(i2s_tdm,
	1609	+ substream->stream);
	1610	+
	1611	+ switch (lanes) {
	1612	+ case 4:
	1613	+ ret = I2S_CHN_8;
	1614	+ break;
	1615	+ case 3:
	1616	+ ret = I2S_CHN_6;
	1617	+ break;
	1618	+ case 2:
	1619	+ ret = I2S_CHN_4;
	1620	+ break;
	1621	+ case 1:
	1622	+ ret = I2S_CHN_2;
	1623	+ break;
	1624	+ default:
	1625	+ ret = -EINVAL;
	1626	+ break;
	1627	+ }
	1628	+
	1629	+ return ret;
	1630	+ }
	1631	+#endif
1238	1632	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1239	1633	reg_fmt = I2S_TXCR;
1240	1634	else
..	..	@@ -1293,8 +1687,12 @@
1293	1687	struct clk *mclk;
1294	1688	int ret = 0;
1295	1689	unsigned int val = 0;
1296		- unsigned int mclk_rate, bclk_rate, div_bclk = 4, div_lrck = 64;
	1690	+ unsigned int mclk_rate, bclk_rate, lrck_rate, div_bclk = 4, div_lrck = 64;
1297	1691
	1692	+#ifdef CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES
	1693	+ if (i2s_tdm->is_tdm_multi_lanes)
	1694	+ rockchip_i2s_tdm_multi_lanes_set_clk(substream, params, dai);
	1695	+#endif
1298	1696	dma_data = snd_soc_dai_get_dma_data(dai, substream);
1299	1697	dma_data->maxburst = MAXBURST_PER_FIFO * params_channels(params) / 2;
1300	1698
..	..	@@ -1307,13 +1705,14 @@
1307	1705	goto err;
1308	1706
1309	1707	mclk_rate = clk_get_rate(mclk);
1310		- bclk_rate = i2s_tdm->bclk_fs * params_rate(params);
	1708	+ lrck_rate = params_rate(params) * i2s_tdm->lrck_ratio;
	1709	+ bclk_rate = i2s_tdm->bclk_fs * lrck_rate;
1311	1710	if (!bclk_rate) {
1312	1711	ret = -EINVAL;
1313	1712	goto err;
1314	1713	}
1315	1714	div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
1316		- div_lrck = bclk_rate / params_rate(params);
	1715	+ div_lrck = bclk_rate / lrck_rate;
1317	1716
1318	1717	switch (params_format(params)) {
1319	1718	case SNDRV_PCM_FORMAT_S8:
..	..	@@ -1542,10 +1941,116 @@
1542	1941	return 0;
1543	1942	}
1544	1943
	1944	+static const char * const rpaths_text[] = {
	1945	+ "From SDI0", "From SDI1", "From SDI2", "From SDI3" };
	1946	+
	1947	+static const char * const tpaths_text[] = {
	1948	+ "From PATH0", "From PATH1", "From PATH2", "From PATH3" };
	1949	+
	1950	+/* TXCR */
	1951	+static SOC_ENUM_SINGLE_DECL(tpath3_enum, I2S_TXCR, 29, tpaths_text);
	1952	+static SOC_ENUM_SINGLE_DECL(tpath2_enum, I2S_TXCR, 27, tpaths_text);
	1953	+static SOC_ENUM_SINGLE_DECL(tpath1_enum, I2S_TXCR, 25, tpaths_text);
	1954	+static SOC_ENUM_SINGLE_DECL(tpath0_enum, I2S_TXCR, 23, tpaths_text);
	1955	+
	1956	+/* RXCR */
	1957	+static SOC_ENUM_SINGLE_DECL(rpath3_enum, I2S_RXCR, 23, rpaths_text);
	1958	+static SOC_ENUM_SINGLE_DECL(rpath2_enum, I2S_RXCR, 21, rpaths_text);
	1959	+static SOC_ENUM_SINGLE_DECL(rpath1_enum, I2S_RXCR, 19, rpaths_text);
	1960	+static SOC_ENUM_SINGLE_DECL(rpath0_enum, I2S_RXCR, 17, rpaths_text);
	1961	+
	1962	+static int rockchip_i2s_tdm_wait_time_info(struct snd_kcontrol *kcontrol,
	1963	+ struct snd_ctl_elem_info *uinfo)
	1964	+{
	1965	+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
	1966	+ uinfo->count = 1;
	1967	+ uinfo->value.integer.min = 0;
	1968	+ uinfo->value.integer.max = WAIT_TIME_MS_MAX;
	1969	+ uinfo->value.integer.step = 1;
	1970	+
	1971	+ return 0;
	1972	+}
	1973	+
	1974	+static int rockchip_i2s_tdm_rd_wait_time_get(struct snd_kcontrol *kcontrol,
	1975	+ struct snd_ctl_elem_value *ucontrol)
	1976	+{
	1977	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1978	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
	1979	+
	1980	+ ucontrol->value.integer.value[0] = i2s_tdm->wait_time[SNDRV_PCM_STREAM_CAPTURE];
	1981	+
	1982	+ return 0;
	1983	+}
	1984	+
	1985	+static int rockchip_i2s_tdm_rd_wait_time_put(struct snd_kcontrol *kcontrol,
	1986	+ struct snd_ctl_elem_value *ucontrol)
	1987	+{
	1988	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	1989	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
	1990	+
	1991	+ if (ucontrol->value.integer.value[0] > WAIT_TIME_MS_MAX)
	1992	+ return -EINVAL;
	1993	+
	1994	+ i2s_tdm->wait_time[SNDRV_PCM_STREAM_CAPTURE] = ucontrol->value.integer.value[0];
	1995	+
	1996	+ return 1;
	1997	+}
	1998	+
	1999	+static int rockchip_i2s_tdm_wr_wait_time_get(struct snd_kcontrol *kcontrol,
	2000	+ struct snd_ctl_elem_value *ucontrol)
	2001	+{
	2002	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	2003	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
	2004	+
	2005	+ ucontrol->value.integer.value[0] = i2s_tdm->wait_time[SNDRV_PCM_STREAM_PLAYBACK];
	2006	+
	2007	+ return 0;
	2008	+}
	2009	+
	2010	+static int rockchip_i2s_tdm_wr_wait_time_put(struct snd_kcontrol *kcontrol,
	2011	+ struct snd_ctl_elem_value *ucontrol)
	2012	+{
	2013	+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
	2014	+ struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
	2015	+
	2016	+ if (ucontrol->value.integer.value[0] > WAIT_TIME_MS_MAX)
	2017	+ return -EINVAL;
	2018	+
	2019	+ i2s_tdm->wait_time[SNDRV_PCM_STREAM_PLAYBACK] = ucontrol->value.integer.value[0];
	2020	+
	2021	+ return 1;
	2022	+}
	2023	+
	2024	+#define SAI_PCM_WAIT_TIME(xname, xhandler_get, xhandler_put) \
	2025	+{ .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, \
	2026	+ .info = rockchip_i2s_tdm_wait_time_info, \
	2027	+ .get = xhandler_get, .put = xhandler_put }
	2028	+
1545	2029	static const struct snd_kcontrol_new rockchip_i2s_tdm_snd_controls[] = {
	2030	+ SOC_ENUM("Receive PATH3 Source Select", rpath3_enum),
	2031	+ SOC_ENUM("Receive PATH2 Source Select", rpath2_enum),
	2032	+ SOC_ENUM("Receive PATH1 Source Select", rpath1_enum),
	2033	+ SOC_ENUM("Receive PATH0 Source Select", rpath0_enum),
	2034	+ SOC_ENUM("Transmit SDO3 Source Select", tpath3_enum),
	2035	+ SOC_ENUM("Transmit SDO2 Source Select", tpath2_enum),
	2036	+ SOC_ENUM("Transmit SDO1 Source Select", tpath1_enum),
	2037	+ SOC_ENUM("Transmit SDO0 Source Select", tpath0_enum),
	2038	+
1546	2039	SOC_ENUM_EXT("I2STDM Digital Loopback Mode", loopback_mode,
1547	2040	rockchip_i2s_tdm_loopback_get,
1548	2041	rockchip_i2s_tdm_loopback_put),
	2042	+#ifdef CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES
	2043	+ SOC_ENUM_EXT("Transmit SDOx Select", tx_lanes_enum,
	2044	+ rockchip_i2s_tdm_tx_lanes_get, rockchip_i2s_tdm_tx_lanes_put),
	2045	+ SOC_ENUM_EXT("Receive SDIx Select", rx_lanes_enum,
	2046	+ rockchip_i2s_tdm_rx_lanes_get, rockchip_i2s_tdm_rx_lanes_put),
	2047	+#endif
	2048	+ SAI_PCM_WAIT_TIME("PCM Read Wait Time MS",
	2049	+ rockchip_i2s_tdm_rd_wait_time_get,
	2050	+ rockchip_i2s_tdm_rd_wait_time_put),
	2051	+ SAI_PCM_WAIT_TIME("PCM Write Wait Time MS",
	2052	+ rockchip_i2s_tdm_wr_wait_time_get,
	2053	+ rockchip_i2s_tdm_wr_wait_time_put),
1549	2054	};
1550	2055
1551	2056	static int rockchip_i2s_tdm_dai_probe(struct snd_soc_dai *dai)
..	..	@@ -1556,7 +2061,9 @@
1556	2061	dai->playback_dma_data = &i2s_tdm->playback_dma_data;
1557	2062
1558	2063	if (i2s_tdm->mclk_calibrate)
1559		- snd_soc_add_dai_controls(dai, &rockchip_i2s_tdm_compensation_control, 1);
	2064	+ snd_soc_add_component_controls(dai->component,
	2065	+ &rockchip_i2s_tdm_compensation_control,
	2066	+ 1);
1560	2067
1561	2068	return 0;
1562	2069	}
..	..	@@ -1587,11 +2094,15 @@
1587	2094	struct snd_soc_dai *dai)
1588	2095	{
1589	2096	struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
	2097	+ int stream = substream->stream;
1590	2098
1591		- if (i2s_tdm->substreams[substream->stream])
	2099	+ if (i2s_tdm->substreams[stream])
1592	2100	return -EBUSY;
1593	2101
1594		- i2s_tdm->substreams[substream->stream] = substream;
	2102	+ if (i2s_tdm->wait_time[stream])
	2103	+ substream->wait_time = msecs_to_jiffies(i2s_tdm->wait_time[stream]);
	2104	+
	2105	+ i2s_tdm->substreams[stream] = substream;
1595	2106
1596	2107	return 0;
1597	2108	}
..	..	@@ -1862,7 +2373,7 @@
1862	2373	.playback = {
1863	2374	.stream_name = "Playback",
1864	2375	.channels_min = 2,
1865		- .channels_max = 16,
	2376	+ .channels_max = 64,
1866	2377	.rates = SNDRV_PCM_RATE_8000_192000,
1867	2378	.formats = (SNDRV_PCM_FMTBIT_S8 \|
1868	2379	SNDRV_PCM_FMTBIT_S16_LE \|
..	..	@@ -1874,7 +2385,7 @@
1874	2385	.capture = {
1875	2386	.stream_name = "Capture",
1876	2387	.channels_min = 2,
1877		- .channels_max = 16,
	2388	+ .channels_max = 64,
1878	2389	.rates = SNDRV_PCM_RATE_8000_192000,
1879	2390	.formats = (SNDRV_PCM_FMTBIT_S8 \|
1880	2391	SNDRV_PCM_FMTBIT_S16_LE \|
..	..	@@ -2070,6 +2581,9 @@
2070	2581	dev_warn_ratelimited(i2s_tdm->dev, "TX FIFO Underrun\n");
2071	2582	regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
2072	2583	I2S_INTCR_TXUIC, I2S_INTCR_TXUIC);
	2584	+ regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
	2585	+ I2S_INTCR_TXUIE_MASK,
	2586	+ I2S_INTCR_TXUIE(0));
2073	2587	substream = i2s_tdm->substreams[SNDRV_PCM_STREAM_PLAYBACK];
2074	2588	if (substream)
2075	2589	snd_pcm_stop_xrun(substream);
..	..	@@ -2079,12 +2593,53 @@
2079	2593	dev_warn_ratelimited(i2s_tdm->dev, "RX FIFO Overrun\n");
2080	2594	regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
2081	2595	I2S_INTCR_RXOIC, I2S_INTCR_RXOIC);
	2596	+ regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
	2597	+ I2S_INTCR_RXOIE_MASK,
	2598	+ I2S_INTCR_RXOIE(0));
2082	2599	substream = i2s_tdm->substreams[SNDRV_PCM_STREAM_CAPTURE];
2083	2600	if (substream)
2084	2601	snd_pcm_stop_xrun(substream);
2085	2602	}
2086	2603
2087	2604	return IRQ_HANDLED;
	2605	+}
	2606	+
	2607	+static int rockchip_i2s_tdm_keep_clk_always_on(struct rk_i2s_tdm_dev *i2s_tdm)
	2608	+{
	2609	+ unsigned int mclk_rate = DEFAULT_FS * DEFAULT_MCLK_FS;
	2610	+ unsigned int bclk_rate = i2s_tdm->bclk_fs * DEFAULT_FS;
	2611	+ unsigned int div_lrck = i2s_tdm->bclk_fs;
	2612	+ unsigned int div_bclk;
	2613	+ int ret;
	2614	+
	2615	+ div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
	2616	+
	2617	+ /* assign generic freq */
	2618	+ clk_set_rate(i2s_tdm->mclk_rx, mclk_rate);
	2619	+ clk_set_rate(i2s_tdm->mclk_tx, mclk_rate);
	2620	+
	2621	+ ret = rockchip_i2s_tdm_mclk_reparent(i2s_tdm);
	2622	+ if (ret)
	2623	+ return ret;
	2624	+
	2625	+ regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
	2626	+ I2S_CLKDIV_RXM_MASK \| I2S_CLKDIV_TXM_MASK,
	2627	+ I2S_CLKDIV_RXM(div_bclk) \| I2S_CLKDIV_TXM(div_bclk));
	2628	+ regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
	2629	+ I2S_CKR_RSD_MASK \| I2S_CKR_TSD_MASK,
	2630	+ I2S_CKR_RSD(div_lrck) \| I2S_CKR_TSD(div_lrck));
	2631	+
	2632	+ if (i2s_tdm->clk_trcm)
	2633	+ rockchip_i2s_tdm_xfer_trcm_start(i2s_tdm);
	2634	+ else
	2635	+ rockchip_i2s_tdm_xfer_start(i2s_tdm, SNDRV_PCM_STREAM_PLAYBACK);
	2636	+
	2637	+ pm_runtime_forbid(i2s_tdm->dev);
	2638	+
	2639	+ dev_info(i2s_tdm->dev, "CLK-ALWAYS-ON: mclk: %d, bclk: %d, fsync: %d\n",
	2640	+ mclk_rate, bclk_rate, DEFAULT_FS);
	2641	+
	2642	+ return 0;
2088	2643	}
2089	2644
2090	2645	static int rockchip_i2s_tdm_probe(struct platform_device *pdev)
..	..	@@ -2109,10 +2664,63 @@
2109	2664	return -ENOMEM;
2110	2665
2111	2666	i2s_tdm->dev = &pdev->dev;
	2667	+ i2s_tdm->lrck_ratio = 1;
2112	2668
2113	2669	of_id = of_match_device(rockchip_i2s_tdm_match, &pdev->dev);
2114	2670	if (!of_id)
2115	2671	return -EINVAL;
	2672	+
	2673	+#ifdef CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES
	2674	+ i2s_tdm->is_tdm_multi_lanes =
	2675	+ device_property_read_bool(i2s_tdm->dev, "rockchip,tdm-multi-lanes");
	2676	+
	2677	+ if (i2s_tdm->is_tdm_multi_lanes) {
	2678	+ struct device_node *clk_src_node = NULL;
	2679	+
	2680	+ i2s_tdm->tx_lanes = 1;
	2681	+ i2s_tdm->rx_lanes = 1;
	2682	+
	2683	+ if (!device_property_read_u32(i2s_tdm->dev, "rockchip,tdm-tx-lanes", &val)) {
	2684	+ if ((val >= 1) && (val <= 4))
	2685	+ i2s_tdm->tx_lanes = val;
	2686	+ }
	2687	+
	2688	+ if (!device_property_read_u32(i2s_tdm->dev, "rockchip,tdm-rx-lanes", &val)) {
	2689	+ if ((val >= 1) && (val <= 4))
	2690	+ i2s_tdm->rx_lanes = val;
	2691	+ }
	2692	+
	2693	+ i2s_tdm->i2s_lrck_gpio = devm_gpiod_get_optional(&pdev->dev, "i2s-lrck", GPIOD_IN);
	2694	+ if (IS_ERR(i2s_tdm->i2s_lrck_gpio)) {
	2695	+ ret = PTR_ERR(i2s_tdm->i2s_lrck_gpio);
	2696	+ dev_err(&pdev->dev, "Failed to get i2s_lrck_gpio %d\n", ret);
	2697	+ return ret;
	2698	+ }
	2699	+
	2700	+ i2s_tdm->tdm_fsync_gpio = devm_gpiod_get_optional(&pdev->dev, "tdm-fsync", GPIOD_IN);
	2701	+ if (IS_ERR(i2s_tdm->tdm_fsync_gpio)) {
	2702	+ ret = PTR_ERR(i2s_tdm->tdm_fsync_gpio);
	2703	+ dev_err(&pdev->dev, "Failed to get tdm_fsync_gpio %d\n", ret);
	2704	+ return ret;
	2705	+ }
	2706	+
	2707	+ /* It's optional, required when use soc clk src, such as: i2s2_2ch */
	2708	+ clk_src_node = of_parse_phandle(node, "rockchip,clk-src", 0);
	2709	+ if (clk_src_node) {
	2710	+ i2s_tdm->clk_src_base = of_iomap(clk_src_node, 0);
	2711	+ if (!i2s_tdm->clk_src_base)
	2712	+ return -ENOENT;
	2713	+
	2714	+ i2s_tdm->clk_src_dai = rockchip_i2s_tdm_find_dai(clk_src_node);
	2715	+ if (!i2s_tdm->clk_src_dai)
	2716	+ return -EPROBE_DEFER;
	2717	+
	2718	+ pm_runtime_forbid(i2s_tdm->clk_src_dai->dev);
	2719	+ }
	2720	+
	2721	+ dev_info(&pdev->dev, "Used as TDM_MULTI_LANES mode\n");
	2722	+ }
	2723	+#endif
2116	2724
2117	2725	spin_lock_init(&i2s_tdm->lock);
2118	2726	i2s_tdm->soc_data = (const struct rk_i2s_soc_data *)of_id->data;
..	..	@@ -2145,6 +2753,15 @@
2145	2753	soc_dai->playback.channels_min = 0;
2146	2754
2147	2755	i2s_tdm->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
	2756	+
	2757	+ i2s_tdm->pinctrl = devm_pinctrl_get(&pdev->dev);
	2758	+ if (!IS_ERR_OR_NULL(i2s_tdm->pinctrl)) {
	2759	+ i2s_tdm->clk_state = pinctrl_lookup_state(i2s_tdm->pinctrl, "clk");
	2760	+ if (IS_ERR(i2s_tdm->clk_state)) {
	2761	+ i2s_tdm->clk_state = NULL;
	2762	+ dev_dbg(i2s_tdm->dev, "Have no clk pinctrl state\n");
	2763	+ }
	2764	+ }
2148	2765
2149	2766	#ifdef HAVE_SYNC_RESET
2150	2767	sync = of_device_is_compatible(node, "rockchip,px30-i2s-tdm") \|\|
..	..	@@ -2264,43 +2881,6 @@
2264	2881	atomic_set(&i2s_tdm->refcount, 0);
2265	2882	dev_set_drvdata(&pdev->dev, i2s_tdm);
2266	2883
2267		- pm_runtime_enable(&pdev->dev);
2268		- if (!pm_runtime_enabled(&pdev->dev)) {
2269		- ret = i2s_tdm_runtime_resume(&pdev->dev);
2270		- if (ret)
2271		- goto err_pm_disable;
2272		- }
2273		-
2274		- if (i2s_tdm->quirks & QUIRK_ALWAYS_ON) {
2275		- unsigned int rate = DEFAULT_FS * DEFAULT_MCLK_FS;
2276		- unsigned int div_bclk = DEFAULT_FS * DEFAULT_MCLK_FS;
2277		- unsigned int div_lrck = i2s_tdm->bclk_fs;
2278		-
2279		- div_bclk = DIV_ROUND_CLOSEST(rate, div_lrck * DEFAULT_FS);
2280		-
2281		- /* assign generic freq */
2282		- clk_set_rate(i2s_tdm->mclk_rx, rate);
2283		- clk_set_rate(i2s_tdm->mclk_tx, rate);
2284		-
2285		- ret = rockchip_i2s_tdm_mclk_reparent(i2s_tdm);
2286		- if (ret)
2287		- goto err_pm_disable;
2288		-
2289		- regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
2290		- I2S_CLKDIV_RXM_MASK \| I2S_CLKDIV_TXM_MASK,
2291		- I2S_CLKDIV_RXM(div_bclk) \| I2S_CLKDIV_TXM(div_bclk));
2292		- regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
2293		- I2S_CKR_RSD_MASK \| I2S_CKR_TSD_MASK,
2294		- I2S_CKR_RSD(div_lrck) \| I2S_CKR_TSD(div_lrck));
2295		-
2296		- if (i2s_tdm->clk_trcm)
2297		- rockchip_i2s_tdm_xfer_trcm_start(i2s_tdm);
2298		- else
2299		- rockchip_i2s_tdm_xfer_start(i2s_tdm, SNDRV_PCM_STREAM_PLAYBACK);
2300		-
2301		- pm_runtime_forbid(&pdev->dev);
2302		- }
2303		-
2304	2884	regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
2305	2885	I2S_DMACR_TDL(16));
2306	2886	regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
..	..	@@ -2311,6 +2891,34 @@
2311	2891	if (i2s_tdm->soc_data && i2s_tdm->soc_data->init)
2312	2892	i2s_tdm->soc_data->init(&pdev->dev, res->start);
2313	2893
	2894	+ /*
	2895	+ * CLK_ALWAYS_ON should be placed after all registers write done,
	2896	+ * because this situation will enable XFER bit which will make
	2897	+ * some registers(depend on XFER) write failed.
	2898	+ */
	2899	+ if (i2s_tdm->quirks & QUIRK_ALWAYS_ON) {
	2900	+ ret = rockchip_i2s_tdm_keep_clk_always_on(i2s_tdm);
	2901	+ if (ret)
	2902	+ return ret;
	2903	+ }
	2904	+
	2905	+ /*
	2906	+ * MUST: after pm_runtime_enable step, any register R/W
	2907	+ * should be wrapped with pm_runtime_get_sync/put.
	2908	+ *
	2909	+ * Another approach is to enable the regcache true to
	2910	+ * avoid access HW registers.
	2911	+ *
	2912	+ * Alternatively, performing the registers R/W before
	2913	+ * pm_runtime_enable is also a good option.
	2914	+ */
	2915	+ pm_runtime_enable(&pdev->dev);
	2916	+ if (!pm_runtime_enabled(&pdev->dev)) {
	2917	+ ret = i2s_tdm_runtime_resume(&pdev->dev);
	2918	+ if (ret)
	2919	+ goto err_pm_disable;
	2920	+ }
	2921	+
2314	2922	ret = devm_snd_soc_register_component(&pdev->dev,
2315	2923	&rockchip_i2s_tdm_component,
2316	2924	soc_dai, 1);