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48 | 48 | #define SPI_TX_QUAD 0x200 |
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49 | 49 | #define SPI_RX_DUAL 0x400 |
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50 | 50 | #define SPI_RX_QUAD 0x800 |
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| 51 | +#define SPI_CS_WORD 0x1000 |
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| 52 | +#define SPI_TX_OCTAL 0x2000 |
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| 53 | +#define SPI_RX_OCTAL 0x4000 |
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| 54 | +#define SPI_3WIRE_HIZ 0x8000 |
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51 | 55 | |
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52 | 56 | /*---------------------------------------------------------------------------*/ |
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53 | 57 | |
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.. | .. |
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66 | 70 | * @delay_usecs: If nonzero, how long to delay after the last bit transfer |
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67 | 71 | * before optionally deselecting the device before the next transfer. |
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68 | 72 | * @cs_change: True to deselect device before starting the next transfer. |
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| 73 | + * @word_delay_usecs: If nonzero, how long to wait between words within one |
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| 74 | + * transfer. This property needs explicit support in the SPI controller, |
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| 75 | + * otherwise it is silently ignored. |
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69 | 76 | * |
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70 | 77 | * This structure is mapped directly to the kernel spi_transfer structure; |
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71 | 78 | * the fields have the same meanings, except of course that the pointers |
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.. | .. |
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100 | 107 | __u8 cs_change; |
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101 | 108 | __u8 tx_nbits; |
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102 | 109 | __u8 rx_nbits; |
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103 | | - __u16 pad; |
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| 110 | + __u8 word_delay_usecs; |
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| 111 | + __u8 pad; |
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104 | 112 | |
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105 | 113 | /* If the contents of 'struct spi_ioc_transfer' ever change |
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106 | 114 | * incompatibly, then the ioctl number (currently 0) must change; |
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