forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f 
 kernel/drivers/video/rockchip/rga3/rga3_reg_info.c
....@@ -390,9 +390,9 @@
390390 	 */
391391 
392392 	/* do not use win0 src size except fbcd */
393
-	*bRGA3_WIN0_SRC_SIZE = (msg->win0.src_act_w +
394
-		msg->win0.x_offset) | ((msg->win0.y_offset +
395
-		msg->win0.src_act_h) << 16);
393
+	/* in FBCD, src_width needs to be aligned at 16 */
394
+	*bRGA3_WIN0_SRC_SIZE = ALIGN(msg->win0.src_act_w + msg->win0.x_offset, 16) |
395
+			       (ALIGN(msg->win0.y_offset + msg->win0.src_act_h, 16) << 16);
396396 	*bRGA3_WIN0_ACT_SIZE =
397397 		msg->win0.src_act_w | (msg->win0.src_act_h << 16);
398398 	*bRGA3_WIN0_DST_SIZE =
....@@ -1028,6 +1028,9 @@
10281028 	u32 *bRGA3_OVLP_OFF;
10291029 
10301030 	u32 reg;
1031
+	union rga3_color_ctrl top_color_ctrl, bottom_color_ctrl;
1032
+	union rga3_alpha_ctrl top_alpha_ctrl, bottom_alpha_ctrl;
1033
+	struct rga_alpha_config *config;
10311034 
10321035 	bRGA_OVERLAP_TOP_CTRL = (u32 *) (base + RGA3_OVLP_TOP_CTRL_OFFSET);
10331036 	bRGA_OVERLAP_BOT_CTRL = (u32 *) (base + RGA3_OVLP_BOT_CTRL_OFFSET);
....@@ -1039,98 +1042,249 @@
10391042 
10401043 	/* Alpha blend */
10411044 	/*bot -> win0(dst), top -> win1(src). */
1042
-	reg = 0;
1043
-	reg =
1044
-		((reg & (~m_RGA3_OVLP_TOP_CTRL_SW_TOP_COLOR_M0)) |
1045
-		 (s_RGA3_OVLP_TOP_CTRL_SW_TOP_COLOR_M0
1046
-		 (msg->alpha_mode_0 >> 7)));
1047
-	reg =
1048
-		((reg & (~m_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_M0)) |
1049
-		 (s_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_M0
1050
-		 (msg->alpha_mode_0 >> 0)));
1051
-	reg =
1052
-		((reg & (~m_RGA3_OVLP_TOP_CTRL_SW_TOP_BLEND_M0)) |
1053
-		 (s_RGA3_OVLP_TOP_CTRL_SW_TOP_BLEND_M0
1054
-		 (msg->alpha_mode_0 >> 1)));
1055
-	reg =
1056
-		((reg & (~m_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_CAL_M0)) |
1057
-		 (s_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_CAL_M0
1058
-		 (msg->alpha_mode_0 >> 3)));
1059
-	reg =
1060
-		((reg & (~m_RGA3_OVLP_TOP_CTRL_SW_TOP_FACTOR_M0)) |
1061
-		 (s_RGA3_OVLP_TOP_CTRL_SW_TOP_FACTOR_M0
1062
-		 (msg->alpha_mode_0 >> 4)));
1063
-	reg =
1064
-		((reg & (~m_RGA3_OVLP_TOP_CTRL_SW_TOP_GLOBAL_ALPHA)) |
1065
-		 (s_RGA3_OVLP_TOP_CTRL_SW_TOP_GLOBAL_ALPHA
1066
-		 (msg->win1_a_global_val)));
1067
-	*bRGA_OVERLAP_TOP_CTRL = reg;
1045
+	top_color_ctrl.value = 0;
1046
+	bottom_color_ctrl.value = 0;
1047
+	top_alpha_ctrl.value = 0;
1048
+	bottom_alpha_ctrl.value = 0;
1049
+	config = &msg->alpha_config;
10681050 
1069
-	reg = 0;
1070
-	reg =
1071
-		((reg & (~m_RGA3_OVLP_BOT_CTRL_SW_BOT_COLOR_M0)) |
1072
-		 (s_RGA3_OVLP_BOT_CTRL_SW_BOT_COLOR_M0
1073
-		 (msg->alpha_mode_0 >> 15)));
1074
-	reg =
1075
-		((reg & (~m_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_M0)) |
1076
-		 (s_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_M0
1077
-		 (msg->alpha_mode_0 >> 8)));
1078
-	reg =
1079
-		((reg & (~m_RGA3_OVLP_BOT_CTRL_SW_BOT_BLEND_M0)) |
1080
-		 (s_RGA3_OVLP_BOT_CTRL_SW_BOT_BLEND_M0
1081
-		 (msg->alpha_mode_0 >> 9)));
1082
-	reg =
1083
-		((reg & (~m_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_CAL_M0)) |
1084
-		 (s_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_CAL_M0
1085
-		 (msg->alpha_mode_0 >> 11)));
1086
-	reg =
1087
-		((reg & (~m_RGA3_OVLP_BOT_CTRL_SW_BOT_FACTOR_M0)) |
1088
-		 (s_RGA3_OVLP_BOT_CTRL_SW_BOT_FACTOR_M0
1089
-		 (msg->alpha_mode_0 >> 12)));
1090
-	reg =
1091
-		((reg & (~m_RGA3_OVLP_BOT_CTRL_SW_BOT_GLOBAL_ALPHA)) |
1092
-		 (s_RGA3_OVLP_BOT_CTRL_SW_BOT_GLOBAL_ALPHA
1093
-		 (msg->win0_a_global_val)));
1094
-	*bRGA_OVERLAP_BOT_CTRL = reg;
1051
+	if (config->fg_pixel_alpha_en)
1052
+		top_color_ctrl.bits.blend_mode =
1053
+			config->fg_global_alpha_en ? RGA_ALPHA_PER_PIXEL_GLOBAL :
1054
+			RGA_ALPHA_PER_PIXEL;
1055
+	else
1056
+		top_color_ctrl.bits.blend_mode = RGA_ALPHA_GLOBAL;
10951057 
1096
-	reg = 0;
1097
-	reg =
1098
-		((reg & (~m_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_M1)) |
1099
-		 (s_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_M1
1100
-		 (msg->alpha_mode_1 >> 0)));
1101
-	reg =
1102
-		((reg & (~m_RGA3_OVLP_TOP_ALPHA_SW_TOP_BLEND_M1)) |
1103
-		 (s_RGA3_OVLP_TOP_ALPHA_SW_TOP_BLEND_M1
1104
-		 (msg->alpha_mode_1 >> 1)));
1105
-	reg =
1106
-		((reg & (~m_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_CAL_M1)) |
1107
-		 (s_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_CAL_M1
1108
-		 (msg->alpha_mode_1 >> 3)));
1109
-	reg =
1110
-		((reg & (~m_RGA3_OVLP_TOP_ALPHA_SW_TOP_FACTOR_M1)) |
1111
-		 (s_RGA3_OVLP_TOP_ALPHA_SW_TOP_FACTOR_M1
1112
-		 (msg->alpha_mode_1 >> 4)));
1113
-	*bRGA_OVERLAP_TOP_ALPHA = reg;
1058
+	if (config->bg_pixel_alpha_en)
1059
+		bottom_color_ctrl.bits.blend_mode =
1060
+			config->bg_global_alpha_en ? RGA_ALPHA_PER_PIXEL_GLOBAL :
1061
+			RGA_ALPHA_PER_PIXEL;
1062
+	else
1063
+		bottom_color_ctrl.bits.blend_mode = RGA_ALPHA_GLOBAL;
11141064 
1115
-	reg = 0;
1116
-	reg =
1117
-		((reg & (~m_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_M1)) |
1118
-		 (s_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_M1
1119
-		 (msg->alpha_mode_1 >> 8)));
1120
-	reg =
1121
-		((reg & (~m_RGA3_OVLP_BOT_ALPHA_SW_BOT_BLEND_M1)) |
1122
-		 (s_RGA3_OVLP_BOT_ALPHA_SW_BOT_BLEND_M1
1123
-		 (msg->alpha_mode_1 >> 9)));
1124
-	reg =
1125
-		((reg & (~m_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_CAL_M1)) |
1126
-		 (s_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_CAL_M1
1127
-		 (msg->alpha_mode_1 >> 11)));
1128
-	reg =
1129
-		((reg & (~m_RGA3_OVLP_BOT_ALPHA_SW_BOT_FACTOR_M1)) |
1130
-		 (s_RGA3_OVLP_BOT_ALPHA_SW_BOT_FACTOR_M1
1131
-		 (msg->alpha_mode_1 >> 12)));
1065
+	/*
1066
+	 * Since the hardware uses 256 as 1, the original alpha value needs to
1067
+	 * be + (alpha >> 7).
1068
+	 */
1069
+	top_color_ctrl.bits.alpha_cal_mode = RGA_ALPHA_SATURATION;
1070
+	bottom_color_ctrl.bits.alpha_cal_mode = RGA_ALPHA_SATURATION;
11321071 
1133
-	*bRGA_OVERLAP_BOT_ALPHA = reg;
1072
+	top_color_ctrl.bits.global_alpha = config->fg_global_alpha_value;
1073
+	bottom_color_ctrl.bits.global_alpha = config->bg_global_alpha_value;
1074
+
1075
+	/* porter duff alpha enable */
1076
+	switch (config->mode) {
1077
+	case RGA_ALPHA_BLEND_SRC:
1078
+		/*
1079
+		 * SRC mode:
1080
+		 *	Sf = 1, Df = 0；
1081
+		 *	[Rc,Ra] = [Sc,Sa]；
1082
+		 */
1083
+		top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
1084
+		top_color_ctrl.bits.factor_mode = RGA_ALPHA_ONE;
1085
+
1086
+		bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
1087
+		bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO;
1088
+
1089
+		break;
1090
+
1091
+	case RGA_ALPHA_BLEND_DST:
1092
+		/*
1093
+		 * SRC mode:
1094
+		 *	Sf = 0, Df = 1；
1095
+		 *	[Rc,Ra] = [Dc,Da]；
1096
+		 */
1097
+		top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
1098
+		top_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO;
1099
+
1100
+		bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
1101
+		bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_ONE;
1102
+
1103
+		break;
1104
+
1105
+	case RGA_ALPHA_BLEND_SRC_OVER:
1106
+		/*
1107
+		 * SRC-OVER mode:
1108
+		 *	Sf = 1, Df = (1 - Sa)
1109
+		 *	[Rc,Ra] = [ Sc + (1 - Sa) * Dc, Sa + (1 - Sa) * Da ]
1110
+		 */
1111
+		top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
1112
+		top_color_ctrl.bits.factor_mode = RGA_ALPHA_ONE;
1113
+
1114
+		bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
1115
+		bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1116
+
1117
+		break;
1118
+
1119
+	case RGA_ALPHA_BLEND_DST_OVER:
1120
+		/*
1121
+		 * DST-OVER mode:
1122
+		 *	Sf = (1 - Da) , Df = 1
1123
+		 *	[Rc,Ra] = [ Sc * (1 - Da) + Dc, Sa * (1 - Da) + Da ]
1124
+		 */
1125
+		top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
1126
+		top_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1127
+
1128
+		bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
1129
+		bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_ONE;
1130
+
1131
+		break;
1132
+
1133
+	case RGA_ALPHA_BLEND_SRC_IN:
1134
+		/*
1135
+		 * SRC-IN mode:
1136
+		 *	Sf = Da , Df = 0
1137
+		 *	[Rc,Ra] = [ Sc * Da, Sa * Da ]
1138
+		 */
1139
+		top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
1140
+		top_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE;
1141
+
1142
+		bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
1143
+		bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO;
1144
+
1145
+		break;
1146
+
1147
+	case RGA_ALPHA_BLEND_DST_IN:
1148
+		/*
1149
+		 * DST-IN mode:
1150
+		 *	Sf = 0 , Df = Sa
1151
+		 *	[Rc,Ra] = [ Dc * Sa, Da * Sa ]
1152
+		 */
1153
+		top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
1154
+		top_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO;
1155
+
1156
+		bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
1157
+		bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE;
1158
+
1159
+		break;
1160
+
1161
+	case RGA_ALPHA_BLEND_SRC_OUT:
1162
+		/*
1163
+		 * SRC-OUT mode:
1164
+		 *	Sf = (1 - Da) , Df = 0
1165
+		 *	[Rc,Ra] = [ Sc * (1 - Da), Sa * (1 - Da) ]
1166
+		 */
1167
+		top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
1168
+		top_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1169
+
1170
+		bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
1171
+		bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO;
1172
+
1173
+		break;
1174
+
1175
+	case RGA_ALPHA_BLEND_DST_OUT:
1176
+		/*
1177
+		 * DST-OUT mode:
1178
+		 *	Sf = 0 , Df = (1 - Sa)
1179
+		 *	[Rc,Ra] = [ Dc * (1 - Sa), Da * (1 - Sa) ]
1180
+		 */
1181
+		top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
1182
+		top_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO;
1183
+
1184
+		bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
1185
+		bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1186
+
1187
+		break;
1188
+
1189
+	case RGA_ALPHA_BLEND_SRC_ATOP:
1190
+		/*
1191
+		 * SRC-ATOP mode:
1192
+		 *	Sf = Da , Df = (1 - Sa)
1193
+		 *	[Rc,Ra] = [ Sc * Da + Dc * (1 - Sa), Sa * Da + Da * (1 - Sa) ]
1194
+		 */
1195
+		top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
1196
+		top_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE;
1197
+
1198
+		bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
1199
+		bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1200
+
1201
+		break;
1202
+
1203
+	case RGA_ALPHA_BLEND_DST_ATOP:
1204
+		/*
1205
+		 * DST-ATOP mode:
1206
+		 *	Sf = (1 - Da) , Df = Sa
1207
+		 *	[Rc,Ra] = [ Sc * (1 - Da) + Dc * Sa, Sa * (1 - Da) + Da * Sa ]
1208
+		 */
1209
+		top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
1210
+		top_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1211
+
1212
+		bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
1213
+		bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE;
1214
+
1215
+		break;
1216
+
1217
+	case RGA_ALPHA_BLEND_XOR:
1218
+		/*
1219
+		 * DST-XOR mode:
1220
+		 *	Sf = (1 - Da) , Df = (1 - Sa)
1221
+		 *	[Rc,Ra] = [ Sc * (1 - Da) + Dc * (1 - Sa), Sa * (1 - Da) + Da * (1 - Sa) ]
1222
+		 */
1223
+		top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
1224
+		top_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1225
+
1226
+		bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
1227
+		bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1228
+
1229
+		break;
1230
+
1231
+	case RGA_ALPHA_BLEND_CLEAR:
1232
+		/*
1233
+		 * DST-CLEAR mode:
1234
+		 *	Sf = 0 , Df = 0
1235
+		 *	[Rc,Ra] = [ 0, 0 ]
1236
+		 */
1237
+		top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
1238
+		top_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO;
1239
+
1240
+		bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
1241
+		bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO;
1242
+
1243
+		break;
1244
+
1245
+	default:
1246
+		break;
1247
+	}
1248
+
1249
+	if (!config->enable && msg->abb_alpha_pass) {
1250
+		/*
1251
+		 * enabled by default bot_blend_m1 && bot_alpha_cal_m1 for src channel(win0)
1252
+		 * In ABB mode, the number will be fetched according to 16*16, so it needs to
1253
+		 * be enabled top_blend_m1 && top_alpha_cal_m1 for dst channel(wr).
1254
+		 */
1255
+		top_color_ctrl.bits.color_mode = RGA_ALPHA_PRE_MULTIPLIED;
1256
+
1257
+		top_alpha_ctrl.bits.blend_mode = RGA_ALPHA_PER_PIXEL;
1258
+		top_alpha_ctrl.bits.alpha_cal_mode = RGA_ALPHA_NO_SATURATION;
1259
+
1260
+		bottom_color_ctrl.bits.color_mode = RGA_ALPHA_PRE_MULTIPLIED;
1261
+
1262
+		bottom_alpha_ctrl.bits.blend_mode = RGA_ALPHA_PER_PIXEL;
1263
+		bottom_alpha_ctrl.bits.alpha_cal_mode = RGA_ALPHA_NO_SATURATION;
1264
+	} else {
1265
+		top_color_ctrl.bits.color_mode =
1266
+			config->fg_pre_multiplied ?
1267
+				RGA_ALPHA_PRE_MULTIPLIED : RGA_ALPHA_NO_PRE_MULTIPLIED;
1268
+
1269
+		top_alpha_ctrl.bits.blend_mode = top_color_ctrl.bits.blend_mode;
1270
+		top_alpha_ctrl.bits.alpha_cal_mode = top_color_ctrl.bits.alpha_cal_mode;
1271
+		top_alpha_ctrl.bits.alpha_mode = top_color_ctrl.bits.alpha_mode;
1272
+		top_alpha_ctrl.bits.factor_mode = top_color_ctrl.bits.factor_mode;
1273
+
1274
+		bottom_color_ctrl.bits.color_mode =
1275
+			config->bg_pre_multiplied ?
1276
+				RGA_ALPHA_PRE_MULTIPLIED : RGA_ALPHA_NO_PRE_MULTIPLIED;
1277
+
1278
+		bottom_alpha_ctrl.bits.blend_mode = bottom_color_ctrl.bits.blend_mode;
1279
+		bottom_alpha_ctrl.bits.alpha_cal_mode = bottom_color_ctrl.bits.alpha_cal_mode;
1280
+		bottom_alpha_ctrl.bits.alpha_mode = bottom_color_ctrl.bits.alpha_mode;
1281
+		bottom_alpha_ctrl.bits.factor_mode = bottom_color_ctrl.bits.factor_mode;
1282
+	}
1283
+
1284
+	*bRGA_OVERLAP_TOP_CTRL = top_color_ctrl.value;
1285
+	*bRGA_OVERLAP_BOT_CTRL = bottom_color_ctrl.value;
1286
+	*bRGA_OVERLAP_TOP_ALPHA = top_alpha_ctrl.value;
1287
+	*bRGA_OVERLAP_BOT_ALPHA = bottom_alpha_ctrl.value;
11341288 
11351289 	/* set RGA_OVERLAP_CTRL */
11361290 	reg = 0;
....@@ -1166,9 +1320,8 @@
11661320 	 * warning: if m1 & m0 need config split，need to redesign
11671321 	 * this judge, which consider RGBA8888 format
11681322 	 */
1169
-	if (msg->alpha_mode_1 > 0 && msg->alpha_mode_0 > 0)
1170
-		reg = ((reg & (~m_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN)) |
1171
-			 (s_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN(1)));
1323
+	reg = ((reg & (~m_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN)) |
1324
+	       (s_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN(config->enable)));
11721325 
11731326 	*bRGA_OVERLAP_CTRL = reg;
11741327 
....@@ -1261,7 +1414,6 @@
12611414 /* TODO: common part */
12621415 static void rga_cmd_to_rga3_cmd(struct rga_req *req_rga, struct rga3_req *req)
12631416 {
1264
-	u16 alpha_mode_0, alpha_mode_1;
12651417 	struct rga_img_info_t tmp;
12661418 
12671419 	req->render_mode = BITBLT_MODE;
....@@ -1324,8 +1476,8 @@
13241476 	if (!(req_rga->alpha_rop_flag & 1)) {
13251477 		if (!rga_is_alpha_format(req_rga->src.format) &&
13261478 		    rga_is_alpha_format(req_rga->dst.format)) {
1327
-			req->win0_a_global_val = 0xff;
1328
-			req->win1_a_global_val = 0xff;
1479
+			req->alpha_config.fg_global_alpha_value = 0xff;
1480
+			req->alpha_config.bg_global_alpha_value = 0xff;
13291481 		}
13301482 	}
13311483 
....@@ -1345,7 +1497,7 @@
13451497 		 * be enabled top_blend_m1 && top_alpha_cal_m1 for dst channel(wr).
13461498 		 */
13471499 		if (rga_is_alpha_format(req_rga->src.format))
1348
-			req->alpha_mode_1 = 0x0a0a;
1500
+			req->abb_alpha_pass = true;
13491501 
13501502 		set_win_info(&req->win0, &req_rga->src);
13511503 
....@@ -1375,7 +1527,7 @@
13751527 		 * be enabled bot_blend_m1 && bot_alpha_cal_m1 for src1/dst channel(win0).
13761528 		 */
13771529 		if (rga_is_alpha_format(req_rga->src.format))
1378
-			req->alpha_mode_1 = 0x0a0a;
1530
+			req->abb_alpha_pass = true;
13791531 
13801532 		if (req_rga->pat.yrgb_addr != 0) {
13811533 			if (req_rga->src.yrgb_addr == req_rga->dst.yrgb_addr) {
....@@ -1478,103 +1630,43 @@
14781630 	/* Alpha blend mode */
14791631 	if (((req_rga->alpha_rop_flag) & 1)) {
14801632 		if ((req_rga->alpha_rop_flag >> 3) & 1) {
1481
-			/* porter duff alpha enable */
1482
-			switch (req_rga->PD_mode) {
1483
-			/* dst = 0 */
1484
-			case 0:
1485
-				break;
1486
-			/* dst = src */
1487
-			case 1:
1488
-				req->alpha_mode_0 = 0x0212;
1489
-				req->alpha_mode_1 = 0x0212;
1490
-				break;
1491
-			/* dst = dst */
1492
-			case 2:
1493
-				req->alpha_mode_0 = 0x1202;
1494
-				req->alpha_mode_1 = 0x1202;
1495
-				break;
1496
-			/* dst = (256*sc + (256 - sa)*dc) >> 8 */
1497
-			case 3:
1498
-				if ((req_rga->alpha_rop_mode & 3) == 0) {
1499
-					/* both use globalAlpha. */
1500
-					alpha_mode_0 = 0x3010;
1501
-					alpha_mode_1 = 0x3010;
1502
-				} else if ((req_rga->alpha_rop_mode & 3) == 1) {
1503
-					/* Do not use globalAlpha. */
1504
-					alpha_mode_0 = 0x3212;
1505
-					alpha_mode_1 = 0x3212;
1506
-				} else if ((req_rga->alpha_rop_mode & 3) == 2) {
1507
-					/*
1508
-					 * dst use globalAlpha,
1509
-					 * and dst has pixelAlpha.
1510
-					 */
1511
-					alpha_mode_0 = 0x3014;
1512
-					alpha_mode_1 = 0x3014;
1513
-				} else {
1514
-					/*
1515
-					 * dst use globalAlpha,
1516
-					 * and dst does not have pixelAlpha.
1517
-					 */
1518
-					alpha_mode_0 = 0x3012;
1519
-					alpha_mode_1 = 0x3012;
1520
-				}
1521
-				req->alpha_mode_0 = alpha_mode_0;
1522
-				req->alpha_mode_1 = alpha_mode_1;
1523
-				break;
1524
-			/* dst = (sc*(256-da) + 256*dc) >> 8 */
1525
-			case 4:
1526
-				/* Do not use globalAlpha. */
1527
-				req->alpha_mode_0 = 0x1232;
1528
-				req->alpha_mode_1 = 0x1232;
1529
-				break;
1530
-			/* dst = (da*sc) >> 8 */
1531
-			case 5:
1532
-				break;
1533
-			/* dst = (sa*dc) >> 8 */
1534
-			case 6:
1535
-				break;
1536
-			/* dst = ((256-da)*sc) >> 8 */
1537
-			case 7:
1538
-				break;
1539
-			/* dst = ((256-sa)*dc) >> 8 */
1540
-			case 8:
1541
-				break;
1542
-			/* dst = (da*sc + (256-sa)*dc) >> 8 */
1543
-			case 9:
1544
-				req->alpha_mode_0 = 0x3040;
1545
-				req->alpha_mode_1 = 0x3040;
1546
-				break;
1547
-			/* dst = ((256-da)*sc + (sa*dc)) >> 8 */
1548
-			case 10:
1549
-				break;
1550
-			/* dst = ((256-da)*sc + (256-sa)*dc) >> 8 */
1551
-			case 11:
1552
-				break;
1553
-			case 12:
1554
-				req->alpha_mode_0 = 0x0010;
1555
-				req->alpha_mode_1 = 0x0820;
1556
-				break;
1557
-			default:
1558
-				break;
1559
-			}
1560
-			/* Real color mode */
1633
+			req->alpha_config.enable = true;
1634
+
15611635 			if ((req_rga->alpha_rop_flag >> 9) & 1) {
1562
-				if (req->alpha_mode_0 & (0x01 << 1))
1563
-					req->alpha_mode_0 |= (1 << 7);
1564
-				if (req->alpha_mode_0 & (0x01 << 9))
1565
-					req->alpha_mode_0 |= (1 << 15);
1636
+				req->alpha_config.fg_pre_multiplied = false;
1637
+				req->alpha_config.bg_pre_multiplied = false;
1638
+			} else {
1639
+				req->alpha_config.fg_pre_multiplied = true;
1640
+				req->alpha_config.bg_pre_multiplied = true;
15661641 			}
1567
-		} else {
1568
-			if ((req_rga->alpha_rop_mode & 3) == 0) {
1569
-				req->alpha_mode_0 = 0x3040;
1570
-				req->alpha_mode_1 = 0x3040;
1571
-			} else if ((req_rga->alpha_rop_mode & 3) == 1) {
1572
-				req->alpha_mode_0 = 0x3042;
1573
-				req->alpha_mode_1 = 0x3242;
1574
-			} else if ((req_rga->alpha_rop_mode & 3) == 2) {
1575
-				req->alpha_mode_0 = 0x3044;
1576
-				req->alpha_mode_1 = 0x3044;
1642
+
1643
+			req->alpha_config.fg_pixel_alpha_en = rga_is_alpha_format(req->win1.format);
1644
+			req->alpha_config.bg_pixel_alpha_en = rga_is_alpha_format(req->win0.format);
1645
+
1646
+			if (req_rga->feature.global_alpha_en) {
1647
+				if (req_rga->fg_global_alpha < 0xff) {
1648
+					req->alpha_config.fg_global_alpha_en = true;
1649
+					req->alpha_config.fg_global_alpha_value =
1650
+						req_rga->fg_global_alpha;
1651
+				} else if (!req->alpha_config.fg_pixel_alpha_en) {
1652
+					req->alpha_config.fg_global_alpha_en = true;
1653
+					req->alpha_config.fg_global_alpha_value = 0xff;
1654
+				}
1655
+
1656
+				if (req_rga->bg_global_alpha < 0xff) {
1657
+					req->alpha_config.bg_global_alpha_en = true;
1658
+					req->alpha_config.bg_global_alpha_value =
1659
+						req_rga->bg_global_alpha;
1660
+				} else if (!req->alpha_config.bg_pixel_alpha_en) {
1661
+					req->alpha_config.bg_global_alpha_en = true;
1662
+					req->alpha_config.bg_global_alpha_value = 0xff;
1663
+				}
1664
+			} else {
1665
+				req->alpha_config.bg_global_alpha_value = 0xff;
1666
+				req->alpha_config.bg_global_alpha_value = 0xff;
15771667 			}
1668
+
1669
+			req->alpha_config.mode = req_rga->PD_mode;
15781670 		}
15791671 	}
15801672 
....@@ -1651,10 +1743,11 @@
16511743 	}
16521744 
16531745 	if (i == RGA_RESET_TIMEOUT)
1654
-		pr_err("RGA3 soft reset timeout. SYS_CTRL[0x%x], RO_SRST[0x%x]\n",
1655
-		       rga_read(RGA3_SYS_CTRL, scheduler), rga_read(RGA3_RO_SRST, scheduler));
1746
+		pr_err("RGA3 core[%d] soft reset timeout. SYS_CTRL[0x%x], RO_SRST[0x%x]\n",
1747
+		       scheduler->core, rga_read(RGA3_SYS_CTRL, scheduler),
1748
+		       rga_read(RGA3_RO_SRST, scheduler));
16561749 	else
1657
-		pr_info("RGA3 soft reset complete.\n");
1750
+		pr_info("RGA3 core[%d] soft reset complete.\n", scheduler->core);
16581751 }
16591752 
16601753 static int rga3_scale_check(const struct rga3_req *req)
....@@ -1821,11 +1914,14 @@
18211914 	pr_info("mmu: win0 = %.2x win1 = %.2x wr = %.2x\n",
18221915 		req->mmu_info.src0_mmu_flag, req->mmu_info.src1_mmu_flag,
18231916 		req->mmu_info.dst_mmu_flag);
1824
-	pr_info("alpha: flag %x mode0=%x mode1=%x\n", req->alpha_rop_flag,
1825
-		req->alpha_mode_0, req->alpha_mode_1);
1826
-	pr_info("blend mode is %s\n",
1827
-		rga_get_blend_mode_str(req->alpha_rop_flag, req->alpha_mode_0,
1828
-					req->alpha_mode_1));
1917
+	pr_info("alpha: flag %x mode=%s\n",
1918
+		req->alpha_rop_flag, rga_get_blend_mode_str(req->alpha_config.mode));
1919
+	pr_info("alpha: pre_multi=[%d,%d] pixl=[%d,%d] glb=[%d,%d]\n",
1920
+		req->alpha_config.fg_pre_multiplied, req->alpha_config.bg_pre_multiplied,
1921
+		req->alpha_config.fg_pixel_alpha_en, req->alpha_config.bg_pixel_alpha_en,
1922
+		req->alpha_config.fg_global_alpha_en, req->alpha_config.bg_global_alpha_en);
1923
+	pr_info("alpha: fg_global_alpha=%x bg_global_alpha=%x\n",
1924
+		req->alpha_config.fg_global_alpha_value, req->alpha_config.bg_global_alpha_value);
18291925 	pr_info("yuv2rgb mode is %x\n", req->yuv2rgb_mode);
18301926 }
18311927