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2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f 
 kernel/drivers/video/rockchip/rga3/rga2_reg_info.c
....@@ -1277,104 +1277,253 @@
12771277 	u32 *bRGA_ALPHA_CTRL0;
12781278 	u32 *bRGA_ALPHA_CTRL1;
12791279 	u32 *bRGA_FADING_CTRL;
1280
-	u32 reg0 = 0;
1281
-	u32 reg1 = 0;
1280
+	u32 reg = 0;
1281
+	union rga2_color_ctrl color_ctrl;
1282
+	union rga2_alpha_ctrl alpha_ctrl;
1283
+	struct rga_alpha_config *config;
12821284 
12831285 	bRGA_ALPHA_CTRL0 = (u32 *) (base + RGA2_ALPHA_CTRL0_OFFSET);
12841286 	bRGA_ALPHA_CTRL1 = (u32 *) (base + RGA2_ALPHA_CTRL1_OFFSET);
12851287 	bRGA_FADING_CTRL = (u32 *) (base + RGA2_FADING_CTRL_OFFSET);
12861288 
1287
-	reg0 =
1288
-		((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0)) |
1289
+	color_ctrl.value = 0;
1290
+	alpha_ctrl.value = 0;
1291
+	config = &msg->alpha_config;
1292
+
1293
+	color_ctrl.bits.src_color_mode =
1294
+		config->fg_pre_multiplied ? RGA_ALPHA_PRE_MULTIPLIED : RGA_ALPHA_NO_PRE_MULTIPLIED;
1295
+	color_ctrl.bits.dst_color_mode =
1296
+		config->bg_pre_multiplied ? RGA_ALPHA_PRE_MULTIPLIED : RGA_ALPHA_NO_PRE_MULTIPLIED;
1297
+
1298
+	if (config->fg_pixel_alpha_en)
1299
+		color_ctrl.bits.src_blend_mode =
1300
+			config->fg_global_alpha_en ? RGA_ALPHA_PER_PIXEL_GLOBAL :
1301
+			RGA_ALPHA_PER_PIXEL;
1302
+	else
1303
+		color_ctrl.bits.src_blend_mode = RGA_ALPHA_GLOBAL;
1304
+
1305
+	if (config->bg_pixel_alpha_en)
1306
+		color_ctrl.bits.dst_blend_mode =
1307
+			config->bg_global_alpha_en ? RGA_ALPHA_PER_PIXEL_GLOBAL :
1308
+			RGA_ALPHA_PER_PIXEL;
1309
+	else
1310
+		color_ctrl.bits.dst_blend_mode = RGA_ALPHA_GLOBAL;
1311
+
1312
+	/*
1313
+	 * Since the hardware uses 256 as 1, the original alpha value needs to
1314
+	 * be + (alpha >> 7).
1315
+	 */
1316
+	color_ctrl.bits.src_alpha_cal_mode = RGA_ALPHA_SATURATION;
1317
+	color_ctrl.bits.dst_alpha_cal_mode = RGA_ALPHA_SATURATION;
1318
+
1319
+	/* porter duff alpha enable */
1320
+	switch (config->mode) {
1321
+	case RGA_ALPHA_BLEND_SRC:
1322
+		/*
1323
+		 * SRC mode:
1324
+		 *	Sf = 1, Df = 0；
1325
+		 *	[Rc,Ra] = [Sc,Sa]；
1326
+		 */
1327
+		color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1328
+		color_ctrl.bits.src_factor_mode = RGA_ALPHA_ONE;
1329
+
1330
+		color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1331
+		color_ctrl.bits.dst_factor_mode = RGA_ALPHA_ZERO;
1332
+
1333
+		break;
1334
+
1335
+	case RGA_ALPHA_BLEND_DST:
1336
+		/*
1337
+		 * SRC mode:
1338
+		 *	Sf = 0, Df = 1；
1339
+		 *	[Rc,Ra] = [Dc,Da]；
1340
+		 */
1341
+		color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1342
+		color_ctrl.bits.src_factor_mode = RGA_ALPHA_ZERO;
1343
+
1344
+		color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1345
+		color_ctrl.bits.dst_factor_mode = RGA_ALPHA_ONE;
1346
+
1347
+		break;
1348
+
1349
+	case RGA_ALPHA_BLEND_SRC_OVER:
1350
+		/*
1351
+		 * SRC-OVER mode:
1352
+		 *	Sf = 1, Df = (1 - Sa)
1353
+		 *	[Rc,Ra] = [ Sc + (1 - Sa) * Dc, Sa + (1 - Sa) * Da ]
1354
+		 */
1355
+		color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1356
+		color_ctrl.bits.src_factor_mode = RGA_ALPHA_ONE;
1357
+
1358
+		color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1359
+		color_ctrl.bits.dst_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1360
+
1361
+		break;
1362
+
1363
+	case RGA_ALPHA_BLEND_DST_OVER:
1364
+		/*
1365
+		 * DST-OVER mode:
1366
+		 *	Sf = (1 - Da) , Df = 1
1367
+		 *	[Rc,Ra] = [ Sc * (1 - Da) + Dc, Sa * (1 - Da) + Da ]
1368
+		 */
1369
+		color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1370
+		color_ctrl.bits.src_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1371
+
1372
+		color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1373
+		color_ctrl.bits.dst_factor_mode = RGA_ALPHA_ONE;
1374
+
1375
+		break;
1376
+
1377
+	case RGA_ALPHA_BLEND_SRC_IN:
1378
+		/*
1379
+		 * SRC-IN mode:
1380
+		 *	Sf = Da , Df = 0
1381
+		 *	[Rc,Ra] = [ Sc * Da, Sa * Da ]
1382
+		 */
1383
+		color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1384
+		color_ctrl.bits.src_factor_mode = RGA_ALPHA_OPPOSITE;
1385
+
1386
+		color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1387
+		color_ctrl.bits.dst_factor_mode = RGA_ALPHA_ZERO;
1388
+
1389
+		break;
1390
+
1391
+	case RGA_ALPHA_BLEND_DST_IN:
1392
+		/*
1393
+		 * DST-IN mode:
1394
+		 *	Sf = 0 , Df = Sa
1395
+		 *	[Rc,Ra] = [ Dc * Sa, Da * Sa ]
1396
+		 */
1397
+		color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1398
+		color_ctrl.bits.src_factor_mode = RGA_ALPHA_ZERO;
1399
+
1400
+		color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1401
+		color_ctrl.bits.dst_factor_mode = RGA_ALPHA_OPPOSITE;
1402
+
1403
+		break;
1404
+
1405
+	case RGA_ALPHA_BLEND_SRC_OUT:
1406
+		/*
1407
+		 * SRC-OUT mode:
1408
+		 *	Sf = (1 - Da) , Df = 0
1409
+		 *	[Rc,Ra] = [ Sc * (1 - Da), Sa * (1 - Da) ]
1410
+		 */
1411
+		color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1412
+		color_ctrl.bits.src_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1413
+
1414
+		color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1415
+		color_ctrl.bits.dst_factor_mode = RGA_ALPHA_ZERO;
1416
+
1417
+		break;
1418
+
1419
+	case RGA_ALPHA_BLEND_DST_OUT:
1420
+		/*
1421
+		 * DST-OUT mode:
1422
+		 *	Sf = 0 , Df = (1 - Sa)
1423
+		 *	[Rc,Ra] = [ Dc * (1 - Sa), Da * (1 - Sa) ]
1424
+		 */
1425
+		color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1426
+		color_ctrl.bits.src_factor_mode = RGA_ALPHA_ZERO;
1427
+
1428
+		color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1429
+		color_ctrl.bits.dst_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1430
+
1431
+		break;
1432
+
1433
+	case RGA_ALPHA_BLEND_SRC_ATOP:
1434
+		/*
1435
+		 * SRC-ATOP mode:
1436
+		 *	Sf = Da , Df = (1 - Sa)
1437
+		 *	[Rc,Ra] = [ Sc * Da + Dc * (1 - Sa), Sa * Da + Da * (1 - Sa) ]
1438
+		 */
1439
+		color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1440
+		color_ctrl.bits.src_factor_mode = RGA_ALPHA_OPPOSITE;
1441
+
1442
+		color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1443
+		color_ctrl.bits.dst_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1444
+
1445
+		break;
1446
+
1447
+	case RGA_ALPHA_BLEND_DST_ATOP:
1448
+		/*
1449
+		 * DST-ATOP mode:
1450
+		 *	Sf = (1 - Da) , Df = Sa
1451
+		 *	[Rc,Ra] = [ Sc * (1 - Da) + Dc * Sa, Sa * (1 - Da) + Da * Sa ]
1452
+		 */
1453
+		color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1454
+		color_ctrl.bits.src_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1455
+
1456
+		color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1457
+		color_ctrl.bits.dst_factor_mode = RGA_ALPHA_OPPOSITE;
1458
+
1459
+		break;
1460
+
1461
+	case RGA_ALPHA_BLEND_XOR:
1462
+		/*
1463
+		 * DST-XOR mode:
1464
+		 *	Sf = (1 - Da) , Df = (1 - Sa)
1465
+		 *	[Rc,Ra] = [ Sc * (1 - Da) + Dc * (1 - Sa), Sa * (1 - Da) + Da * (1 - Sa) ]
1466
+		 */
1467
+		color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1468
+		color_ctrl.bits.src_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1469
+
1470
+		color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1471
+		color_ctrl.bits.dst_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1472
+
1473
+		break;
1474
+
1475
+	case RGA_ALPHA_BLEND_CLEAR:
1476
+		/*
1477
+		 * DST-CLEAR mode:
1478
+		 *	Sf = 0 , Df = 0
1479
+		 *	[Rc,Ra] = [ 0, 0 ]
1480
+		 */
1481
+		color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1482
+		color_ctrl.bits.src_factor_mode = RGA_ALPHA_ZERO;
1483
+
1484
+		color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1485
+		color_ctrl.bits.dst_factor_mode = RGA_ALPHA_ZERO;
1486
+
1487
+		break;
1488
+
1489
+	default:
1490
+		break;
1491
+	}
1492
+
1493
+	alpha_ctrl.bits.src_blend_mode = color_ctrl.bits.src_blend_mode;
1494
+	alpha_ctrl.bits.dst_blend_mode = color_ctrl.bits.dst_blend_mode;
1495
+
1496
+	alpha_ctrl.bits.src_alpha_cal_mode = color_ctrl.bits.src_alpha_cal_mode;
1497
+	alpha_ctrl.bits.dst_alpha_cal_mode = color_ctrl.bits.dst_alpha_cal_mode;
1498
+
1499
+	alpha_ctrl.bits.src_alpha_mode = color_ctrl.bits.src_alpha_mode;
1500
+	alpha_ctrl.bits.src_factor_mode = color_ctrl.bits.src_factor_mode;
1501
+
1502
+	alpha_ctrl.bits.dst_alpha_mode = color_ctrl.bits.dst_alpha_mode;
1503
+	alpha_ctrl.bits.dst_factor_mode = color_ctrl.bits.dst_factor_mode;
1504
+
1505
+	reg =
1506
+		((reg & (~m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0)) |
12891507 		 (s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0(msg->alpha_rop_flag)));
1290
-	reg0 =
1291
-		((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL)) |
1508
+	reg =
1509
+		((reg & (~m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL)) |
12921510 		 (s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL
12931511 		 (msg->alpha_rop_flag >> 1)));
1294
-	reg0 =
1295
-		((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_ROP_MODE)) |
1512
+	reg =
1513
+		((reg & (~m_RGA2_ALPHA_CTRL0_SW_ROP_MODE)) |
12961514 		 (s_RGA2_ALPHA_CTRL0_SW_ROP_MODE(msg->rop_mode)));
1297
-	reg0 =
1298
-		((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA)) |
1515
+	reg =
1516
+		((reg & (~m_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA)) |
12991517 		 (s_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA
1300
-		 (msg->src_a_global_val)));
1301
-	reg0 =
1302
-		((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA)) |
1518
+		 ((uint8_t)config->fg_global_alpha_value)));
1519
+	reg =
1520
+		((reg & (~m_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA)) |
13031521 		 (s_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA
1304
-		 (msg->dst_a_global_val)));
1522
+		 ((uint8_t)config->bg_global_alpha_value)));
13051523 
1306
-	reg1 =
1307
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_COLOR_M0)) |
1308
-		 (s_RGA2_ALPHA_CTRL1_SW_DST_COLOR_M0
1309
-		 (msg->alpha_mode_0 >> 15)));
1310
-	reg1 =
1311
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_COLOR_M0)) |
1312
-		 (s_RGA2_ALPHA_CTRL1_SW_SRC_COLOR_M0
1313
-		 (msg->alpha_mode_0 >> 7)));
1314
-	reg1 =
1315
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M0)) |
1316
-		 (s_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M0
1317
-		 (msg->alpha_mode_0 >> 12)));
1318
-	reg1 =
1319
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M0)) |
1320
-		 (s_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M0
1321
-		 (msg->alpha_mode_0 >> 4)));
1322
-	reg1 =
1323
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M0)) |
1324
-		 (s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M0
1325
-		 (msg->alpha_mode_0 >> 11)));
1326
-	reg1 =
1327
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M0)) |
1328
-		 (s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M0
1329
-		 (msg->alpha_mode_0 >> 3)));
1330
-	reg1 =
1331
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0)) |
1332
-		 (s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0
1333
-		 (msg->alpha_mode_0 >> 9)));
1334
-	reg1 =
1335
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M0)) |
1336
-		 (s_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M0
1337
-		 (msg->alpha_mode_0 >> 1)));
1338
-	reg1 =
1339
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M0)) |
1340
-		 (s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M0
1341
-		 (msg->alpha_mode_0 >> 8)));
1342
-	reg1 =
1343
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M0)) |
1344
-		 (s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M0
1345
-		 (msg->alpha_mode_0 >> 0)));
1524
+	*bRGA_ALPHA_CTRL0 = reg;
1525
+	*bRGA_ALPHA_CTRL1 = color_ctrl.value | (alpha_ctrl.value << 16);
13461526 
1347
-	reg1 =
1348
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M1)) |
1349
-		 (s_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M1
1350
-		 (msg->alpha_mode_1 >> 12)));
1351
-	reg1 =
1352
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M1)) |
1353
-		 (s_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M1
1354
-		 (msg->alpha_mode_1 >> 4)));
1355
-	reg1 =
1356
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M1)) |
1357
-		 (s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M1
1358
-		 (msg->alpha_mode_1 >> 11)));
1359
-	reg1 =
1360
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M1)) |
1361
-		 (s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M1
1362
-		 (msg->alpha_mode_1 >> 3)));
1363
-	reg1 =
1364
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M1)) |
1365
-		 (s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M1(msg->alpha_mode_1 >> 9)));
1366
-	reg1 =
1367
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M1)) |
1368
-		 (s_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M1(msg->alpha_mode_1 >> 1)));
1369
-	reg1 =
1370
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M1)) |
1371
-		 (s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M1(msg->alpha_mode_1 >> 8)));
1372
-	reg1 =
1373
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M1)) |
1374
-		 (s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M1(msg->alpha_mode_1 >> 0)));
1375
-
1376
-	*bRGA_ALPHA_CTRL0 = reg0;
1377
-	*bRGA_ALPHA_CTRL1 = reg1;
13781527 
13791528 	if ((msg->alpha_rop_flag >> 2) & 1) {
13801529 		*bRGA_FADING_CTRL = (1 << 24) | (msg->fading_b_value << 16) |
....@@ -1776,8 +1925,6 @@
17761925 static void rga_cmd_to_rga2_cmd(struct rga_scheduler_t *scheduler,
17771926 				struct rga_req *req_rga, struct rga2_req *req)
17781927 {
1779
-	u16 alpha_mode_0, alpha_mode_1;
1780
-
17811928 	if (req_rga->render_mode == 6)
17821929 		req->render_mode = UPDATE_PALETTE_TABLE_MODE;
17831930 	else if (req_rga->render_mode == 7)
....@@ -1877,6 +2024,8 @@
18772024 
18782025 	req->palette_mode = req_rga->palette_mode;
18792026 	req->yuv2rgb_mode = req_rga->yuv2rgb_mode;
2027
+	if (req_rga->full_csc.flag & 0x1)
2028
+		req->full_csc_en = 1;
18802029 	req->endian_mode = req_rga->endian_mode;
18812030 	req->rgb2yuv_mode = 0;
18822031 
....@@ -1918,110 +2067,52 @@
19182067 
19192068 	if (((req_rga->alpha_rop_flag) & 1)) {
19202069 		if ((req_rga->alpha_rop_flag >> 3) & 1) {
1921
-			/* porter duff alpha enable */
1922
-			switch (req_rga->PD_mode) {
1923
-			/* dst = 0 */
1924
-			case 0:
1925
-				break;
1926
-			/* dst = src */
1927
-			case 1:
1928
-				req->alpha_mode_0 = 0x0212;
1929
-				req->alpha_mode_1 = 0x0212;
1930
-				break;
1931
-			/* dst = dst */
1932
-			case 2:
1933
-				req->alpha_mode_0 = 0x1202;
1934
-				req->alpha_mode_1 = 0x1202;
1935
-				break;
1936
-			/* dst = (256*sc + (256 - sa)*dc) >> 8 */
1937
-			case 3:
1938
-				if ((req_rga->alpha_rop_mode & 3) == 0) {
1939
-					/* both use globalAlpha. */
1940
-					alpha_mode_0 = 0x3010;
1941
-					alpha_mode_1 = 0x3010;
1942
-				} else if ((req_rga->alpha_rop_mode & 3) == 1) {
1943
-					/* Do not use globalAlpha. */
1944
-					alpha_mode_0 = 0x3212;
1945
-					alpha_mode_1 = 0x3212;
1946
-				} else if ((req_rga->alpha_rop_mode & 3) == 2) {
1947
-					/*
1948
-					 * dst use globalAlpha,
1949
-					 * and dst has pixelAlpha.
1950
-					 */
1951
-					alpha_mode_0 = 0x3014;
1952
-					alpha_mode_1 = 0x3014;
1953
-				} else {
1954
-					/*
1955
-					 * dst use globalAlpha, and
1956
-					 * dst does not have pixelAlpha.
1957
-					 */
1958
-					alpha_mode_0 = 0x3012;
1959
-					alpha_mode_1 = 0x3012;
1960
-				}
1961
-				req->alpha_mode_0 = alpha_mode_0;
1962
-				req->alpha_mode_1 = alpha_mode_1;
1963
-				break;
1964
-			/* dst = (sc*(256-da) + 256*dc) >> 8 */
1965
-			case 4:
1966
-				/* Do not use globalAlpha. */
1967
-				req->alpha_mode_0 = 0x1232;
1968
-				req->alpha_mode_1 = 0x1232;
1969
-				break;
1970
-			/* dst = (da*sc) >> 8 */
1971
-			case 5:
1972
-				break;
1973
-			/* dst = (sa*dc) >> 8 */
1974
-			case 6:
1975
-				break;
1976
-			/* dst = ((256-da)*sc) >> 8 */
1977
-			case 7:
1978
-				break;
1979
-			/* dst = ((256-sa)*dc) >> 8 */
1980
-			case 8:
1981
-				break;
1982
-			/* dst = (da*sc + (256-sa)*dc) >> 8 */
1983
-			case 9:
1984
-				req->alpha_mode_0 = 0x3040;
1985
-				req->alpha_mode_1 = 0x3040;
1986
-				break;
1987
-			/* dst = ((256-da)*sc + (sa*dc)) >> 8 */
1988
-			case 10:
1989
-				break;
1990
-			/* dst = ((256-da)*sc + (256-sa)*dc) >> 8 */
1991
-			case 11:
1992
-				break;
1993
-			case 12:
1994
-				req->alpha_mode_0 = 0x0010;
1995
-				req->alpha_mode_1 = 0x0820;
1996
-				break;
1997
-			default:
1998
-				break;
1999
-			}
2070
+			req->alpha_config.enable = true;
20002071 
2001
-			if (req->osd_info.enable) {
2002
-				/* set dst(osd_block) real color mode */
2003
-				if (req->alpha_mode_0 & (0x01 << 9))
2004
-					req->alpha_mode_0 |= (1 << 15);
2005
-			}
2006
-
2007
-			/* Real color mode */
20082072 			if ((req_rga->alpha_rop_flag >> 9) & 1) {
2009
-				if (req->alpha_mode_0 & (0x01 << 1))
2010
-					req->alpha_mode_0 |= (1 << 7);
2011
-				if (req->alpha_mode_0 & (0x01 << 9))
2012
-					req->alpha_mode_0 |= (1 << 15);
2073
+				req->alpha_config.fg_pre_multiplied = false;
2074
+				req->alpha_config.bg_pre_multiplied = false;
2075
+			} else if (req->osd_info.enable) {
2076
+				req->alpha_config.fg_pre_multiplied = true;
2077
+				/* set dst(osd_block) real color mode */
2078
+				req->alpha_config.bg_pre_multiplied = false;
2079
+			} else {
2080
+				req->alpha_config.fg_pre_multiplied = true;
2081
+				req->alpha_config.bg_pre_multiplied = true;
20132082 			}
2014
-		} else {
2015
-			if ((req_rga->alpha_rop_mode & 3) == 0) {
2016
-				req->alpha_mode_0 = 0x3040;
2017
-				req->alpha_mode_1 = 0x3040;
2018
-			} else if ((req_rga->alpha_rop_mode & 3) == 1) {
2019
-				req->alpha_mode_0 = 0x3042;
2020
-				req->alpha_mode_1 = 0x3242;
2021
-			} else if ((req_rga->alpha_rop_mode & 3) == 2) {
2022
-				req->alpha_mode_0 = 0x3044;
2023
-				req->alpha_mode_1 = 0x3044;
2083
+
2084
+			req->alpha_config.fg_pixel_alpha_en = rga_is_alpha_format(req->src.format);
2085
+			if (req->bitblt_mode)
2086
+				req->alpha_config.bg_pixel_alpha_en =
2087
+					rga_is_alpha_format(req->src1.format);
2088
+			else
2089
+				req->alpha_config.bg_pixel_alpha_en =
2090
+					rga_is_alpha_format(req->dst.format);
2091
+
2092
+			if (req_rga->feature.global_alpha_en) {
2093
+				if (req_rga->fg_global_alpha < 0xff) {
2094
+					req->alpha_config.fg_global_alpha_en = true;
2095
+					req->alpha_config.fg_global_alpha_value =
2096
+						req_rga->fg_global_alpha;
2097
+				} else if (!req->alpha_config.fg_pixel_alpha_en) {
2098
+					req->alpha_config.fg_global_alpha_en = true;
2099
+					req->alpha_config.fg_global_alpha_value = 0xff;
2100
+				}
2101
+
2102
+				if (req_rga->bg_global_alpha < 0xff) {
2103
+					req->alpha_config.bg_global_alpha_en = true;
2104
+					req->alpha_config.bg_global_alpha_value =
2105
+						req_rga->bg_global_alpha;
2106
+				} else if (!req->alpha_config.bg_pixel_alpha_en) {
2107
+					req->alpha_config.bg_global_alpha_en = true;
2108
+					req->alpha_config.bg_global_alpha_value = 0xff;
2109
+				}
2110
+			} else {
2111
+				req->alpha_config.bg_global_alpha_value = 0xff;
2112
+				req->alpha_config.bg_global_alpha_value = 0xff;
20242113 			}
2114
+
2115
+			req->alpha_config.mode = req_rga->PD_mode;
20252116 		}
20262117 	}
20272118 
....@@ -2094,9 +2185,9 @@
20942185 	}
20952186 
20962187 	if (i == RGA_RESET_TIMEOUT)
2097
-		pr_err("RAG2 soft reset timeout.\n");
2188
+		pr_err("RAG2 core[%d] soft reset timeout.\n", scheduler->core);
20982189 	else
2099
-		pr_info("RGA2 soft reset complete.\n");
2190
+		pr_info("RGA2 core[%d] soft reset complete.\n", scheduler->core);
21002191 
21012192 }
21022193 
....@@ -2216,11 +2307,14 @@
22162307 	pr_info("mmu: src=%.2x src1=%.2x dst=%.2x els=%.2x\n",
22172308 		req->mmu_info.src0_mmu_flag, req->mmu_info.src1_mmu_flag,
22182309 		req->mmu_info.dst_mmu_flag, req->mmu_info.els_mmu_flag);
2219
-	pr_info("alpha: flag %x mode0=%x mode1=%x\n", req->alpha_rop_flag,
2220
-		req->alpha_mode_0, req->alpha_mode_1);
2221
-	pr_info("blend mode is %s\n",
2222
-		rga_get_blend_mode_str(req->alpha_rop_flag, req->alpha_mode_0,
2223
-					req->alpha_mode_1));
2310
+	pr_info("alpha: flag %x mode=%s\n",
2311
+		req->alpha_rop_flag, rga_get_blend_mode_str(req->alpha_config.mode));
2312
+	pr_info("alpha: pre_multi=[%d,%d] pixl=[%d,%d] glb=[%d,%d]\n",
2313
+		req->alpha_config.fg_pre_multiplied, req->alpha_config.bg_pre_multiplied,
2314
+		req->alpha_config.fg_pixel_alpha_en, req->alpha_config.bg_pixel_alpha_en,
2315
+		req->alpha_config.fg_global_alpha_en, req->alpha_config.bg_global_alpha_en);
2316
+	pr_info("alpha: fg_global_alpha=%x bg_global_alpha=%x\n",
2317
+		req->alpha_config.fg_global_alpha_value, req->alpha_config.bg_global_alpha_value);
22242318 	pr_info("yuv2rgb mode is %x\n", req->yuv2rgb_mode);
22252319 }
22262320 
....@@ -2239,7 +2333,24 @@
22392333 	memset(&req, 0x0, sizeof(req));
22402334 
22412335 	rga_cmd_to_rga2_cmd(scheduler, &job->rga_command_base, &req);
2242
-	memcpy(&job->full_csc, &job->rga_command_base.full_csc, sizeof(job->full_csc));
2336
+	if (req.full_csc_en) {
2337
+		memcpy(&job->full_csc, &job->rga_command_base.full_csc, sizeof(job->full_csc));
2338
+		if (job->rga_command_base.feature.full_csc_clip_en) {
2339
+			memcpy(&job->full_csc_clip, &job->rga_command_base.full_csc_clip,
2340
+			       sizeof(job->full_csc_clip));
2341
+		} else {
2342
+			job->full_csc_clip.y.max = 0xff;
2343
+			job->full_csc_clip.y.min = 0x0;
2344
+			job->full_csc_clip.uv.max = 0xff;
2345
+			job->full_csc_clip.uv.min = 0x0;
2346
+		}
2347
+
2348
+	} else {
2349
+		job->full_csc_clip.y.max = 0xff;
2350
+		job->full_csc_clip.y.min = 0x0;
2351
+		job->full_csc_clip.uv.max = 0xff;
2352
+		job->full_csc_clip.uv.min = 0x0;
2353
+	}
22432354 	memcpy(&job->pre_intr_info, &job->rga_command_base.pre_intr_info,
22442355 	       sizeof(job->pre_intr_info));
22452356 
....@@ -2390,19 +2501,13 @@
23902501 
23912502 static void rga2_set_reg_full_csc(struct rga_job *job, struct rga_scheduler_t *scheduler)
23922503 {
2393
-	uint8_t clip_y_max, clip_y_min;
2394
-	uint8_t clip_uv_max, clip_uv_min;
2395
-
2396
-	clip_y_max = 0xff;
2397
-	clip_y_min = 0x0;
2398
-	clip_uv_max = 0xff;
2399
-	clip_uv_min = 0;
2400
-
24012504 	/* full csc coefficient */
24022505 	/* Y coefficient */
2403
-	rga_write(job->full_csc.coe_y.r_v | (clip_y_max << 16) | (clip_y_min << 24),
2506
+	rga_write(job->full_csc.coe_y.r_v |
2507
+		  (job->full_csc_clip.y.max << 16) | (job->full_csc_clip.y.min << 24),
24042508 		  RGA2_DST_CSC_00, scheduler);
2405
-	rga_write(job->full_csc.coe_y.g_y | (clip_uv_max << 16) | (clip_uv_min << 24),
2509
+	rga_write(job->full_csc.coe_y.g_y |
2510
+		  (job->full_csc_clip.uv.max << 16) | (job->full_csc_clip.uv.min << 24),
24062511 		  RGA2_DST_CSC_01, scheduler);
24072512 	rga_write(job->full_csc.coe_y.b_u, RGA2_DST_CSC_02, scheduler);
24082513 	rga_write(job->full_csc.coe_y.off, RGA2_DST_CSC_OFF0, scheduler);