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hc
2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f 
 kernel/drivers/usb/dwc3/core.h
....@@ -1,8 +1,8 @@
1
-// SPDX-License-Identifier: GPL-2.0
1
+/* SPDX-License-Identifier: GPL-2.0 */
22 /*
33  * core.h - DesignWare USB3 DRD Core Header
44  *
5
- * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5
+ * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
66  *
77  * Authors: Felipe Balbi <balbi@ti.com>,
88  *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
....@@ -13,6 +13,7 @@
1313 
1414 #include <linux/device.h>
1515 #include <linux/spinlock.h>
16
+#include <linux/mutex.h>
1617 #include <linux/ioport.h>
1718 #include <linux/list.h>
1819 #include <linux/bitops.h>
....@@ -21,18 +22,21 @@
2122 #include <linux/debugfs.h>
2223 #include <linux/wait.h>
2324 #include <linux/workqueue.h>
25
+#include <linux/android_kabi.h>
2426 
2527 #include <linux/usb/ch9.h>
2628 #include <linux/usb/gadget.h>
2729 #include <linux/usb/otg.h>
30
+#include <linux/usb/role.h>
2831 #include <linux/ulpi/interface.h>
2932 
3033 #include <linux/phy/phy.h>
3134 
35
+#include <linux/power_supply.h>
36
+
3237 #define DWC3_MSG_MAX	500
3338 
3439 /* Global constants */
35
-#define DWC3_DISCON_TIMEOUT	1000	/* ms */
3640 #define DWC3_PULL_UP_TIMEOUT	500	/* ms */
3741 #define DWC3_BOUNCE_SIZE	1024	/* size of a superspeed bulk */
3842 #define DWC3_EP0_SETUP_SIZE	512
....@@ -54,7 +58,7 @@
5458 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE	3
5559 #define DWC3_DEVICE_EVENT_WAKEUP		4
5660 #define DWC3_DEVICE_EVENT_HIBER_REQ		5
57
-#define DWC3_DEVICE_EVENT_EOPF			6
61
+#define DWC3_DEVICE_EVENT_SUSPEND		6
5862 #define DWC3_DEVICE_EVENT_SOF			7
5963 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR		9
6064 #define DWC3_DEVICE_EVENT_CMD_CMPL		10
....@@ -69,6 +73,7 @@
6973 #define DWC3_GEVNTCOUNT_EHB	BIT(31)
7074 #define DWC3_GSNPSID_MASK	0xffff0000
7175 #define DWC3_GSNPSREV_MASK	0xffff
76
+#define DWC3_GSNPS_ID(p)	(((p) & DWC3_GSNPSID_MASK) >> 16)
7277 
7378 /* DWC3 registers memory space boundries */
7479 #define DWC3_XHCI_REGS_START		0x0
....@@ -137,7 +142,9 @@
137142 #define DWC3_GEVNTCOUNT(n)	(0xc40c + ((n) * 0x10))
138143 
139144 #define DWC3_GHWPARAMS8		0xc600
145
+#define DWC3_GUCTL3		0xc60c
140146 #define DWC3_GFLADJ		0xc630
147
+#define DWC3_GHWPARAMS9		0xc6e0
141148 
142149 /* Device Registers */
143150 #define DWC3_DCFG		0xc700
....@@ -250,10 +257,12 @@
250257 #define DWC3_GUCTL_HSTINAUTORETRY	BIT(14)
251258 
252259 /* Global User Control 1 Register */
260
+#define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT	BIT(31)
253261 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)
254262 #define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK	BIT(26)
255
-#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW	BIT(24)
256
-#define DWC3_GUCTL1_PARKMODE_DISABLE_SS	BIT(17)
263
+#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW		BIT(24)
264
+#define DWC3_GUCTL1_PARKMODE_DISABLE_SS		BIT(17)
265
+#define DWC3_GUCTL1_PARKMODE_DISABLE_HS		BIT(16)
257266 
258267 /* Global Status Register */
259268 #define DWC3_GSTS_OTG_IP	BIT(10)
....@@ -309,13 +318,14 @@
309318 
310319 /* Global TX Fifo Size Register */
311320 #define DWC31_GTXFIFOSIZ_TXFRAMNUM	BIT(15)		/* DWC_usb31 only */
312
-#define DWC31_GTXFIFOSIZ_TXFDEF(n)	((n) & 0x7fff)	/* DWC_usb31 only */
313
-#define DWC3_GTXFIFOSIZ_TXFDEF(n)	((n) & 0xffff)
321
+#define DWC31_GTXFIFOSIZ_TXFDEP(n)	((n) & 0x7fff)	/* DWC_usb31 only */
322
+#define DWC3_GTXFIFOSIZ_TXFDEP(n)	((n) & 0xffff)
314323 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n)	((n) & 0xffff0000)
315324 
316325 /* Global RX Fifo Size Register */
317326 #define DWC31_GRXFIFOSIZ_RXFDEP(n)	((n) & 0x7fff)	/* DWC_usb31 only */
318327 #define DWC3_GRXFIFOSIZ_RXFDEP(n)	((n) & 0xffff)
328
+#define DWC3_GRXFIFOSIZ_RXFSTADDR(n)	((n) & 0xffff0000)
319329 
320330 /* Global Event Size Registers */
321331 #define DWC3_GEVNTSIZ_INTMASK		BIT(31)
....@@ -366,10 +376,17 @@
366376 #define DWC3_GHWPARAMS6_HNPSUPPORT		BIT(11)
367377 #define DWC3_GHWPARAMS6_SRPSUPPORT		BIT(10)
368378 #define DWC3_GHWPARAMS6_EN_FPGA			BIT(7)
379
+#define DWC3_GHWPARAMS6_RAM0_DEPTH(n)		(((n) >> 16) & 0xffff)
380
+
381
+/* DWC_usb32 only */
382
+#define DWC3_GHWPARAMS6_MDWIDTH(n)		((n) & (0x3 << 8))
369383 
370384 /* Global HWPARAMS7 Register */
371385 #define DWC3_GHWPARAMS7_RAM1_DEPTH(n)	((n) & 0xffff)
372386 #define DWC3_GHWPARAMS7_RAM2_DEPTH(n)	(((n) >> 16) & 0xffff)
387
+
388
+/* Global HWPARAMS9 Register */
389
+#define DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS	BIT(0)
373390 
374391 /* Global Frame Length Adjustment Register */
375392 #define DWC3_GFLADJ_30MHZ_SDBND_SEL		BIT(7)
....@@ -378,7 +395,12 @@
378395 /* Global User Control Register 2 */
379396 #define DWC3_GUCTL2_RST_ACTBITLATER		BIT(14)
380397 
398
+/* Global User Control Register 3 */
399
+#define DWC3_GUCTL3_SPLITDISABLE		BIT(14)
400
+
381401 /* Device Configuration Register */
402
+#define DWC3_DCFG_NUMLANES(n)	(((n) & 0x3) << 30) /* DWC_usb32 only */
403
+
382404 #define DWC3_DCFG_DEVADDR(addr)	((addr) << 3)
383405 #define DWC3_DCFG_DEVADDR_MASK	DWC3_DCFG_DEVADDR(0x7f)
384406 
....@@ -393,6 +415,7 @@
393415 #define DWC3_DCFG_NUMP(n)	(((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
394416 #define DWC3_DCFG_NUMP_MASK	(0x1f << DWC3_DCFG_NUMP_SHIFT)
395417 #define DWC3_DCFG_LPM_CAP	BIT(22)
418
+#define DWC3_DCFG_IGNSTRMPP	BIT(23)
396419 
397420 /* Device Control Register */
398421 #define DWC3_DCTL_RUN_STOP	BIT(31)
....@@ -444,13 +467,15 @@
444467 #define DWC3_DEVTEN_CMDCMPLTEN		BIT(10)
445468 #define DWC3_DEVTEN_ERRTICERREN		BIT(9)
446469 #define DWC3_DEVTEN_SOFEN		BIT(7)
447
-#define DWC3_DEVTEN_EOPFEN		BIT(6)
470
+#define DWC3_DEVTEN_U3L2L1SUSPEN	BIT(6)
448471 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN	BIT(5)
449472 #define DWC3_DEVTEN_WKUPEVTEN		BIT(4)
450473 #define DWC3_DEVTEN_ULSTCNGEN		BIT(3)
451474 #define DWC3_DEVTEN_CONNECTDONEEN	BIT(2)
452475 #define DWC3_DEVTEN_USBRSTEN		BIT(1)
453476 #define DWC3_DEVTEN_DISCONNEVTEN	BIT(0)
477
+
478
+#define DWC3_DSTS_CONNLANES(n)		(((n) >> 30) & 0x3) /* DWC_usb32 only */
454479 
455480 /* Device Status Register */
456481 #define DWC3_DSTS_DCNRD			BIT(29)
....@@ -493,6 +518,7 @@
493518 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH	0x09
494519 #define DWC3_DGCMD_ALL_FIFO_FLUSH	0x0a
495520 #define DWC3_DGCMD_SET_ENDPOINT_NRDY	0x0c
521
+#define DWC3_DGCMD_SET_ENDPOINT_PRIME	0x0d
496522 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK	0x10
497523 
498524 #define DWC3_DGCMD_STATUS(n)		(((n) >> 12) & 0x0F)
....@@ -631,7 +657,7 @@
631657 struct dwc3_event_buffer {
632658 	void			*buf;
633659 	void			*cache;
634
-	unsigned		length;
660
+	unsigned int		length;
635661 	unsigned int		lpos;
636662 	unsigned int		count;
637663 	unsigned int		flags;
....@@ -641,6 +667,8 @@
641667 	dma_addr_t		dma;
642668 
643669 	struct dwc3		*dwc;
670
+
671
+	ANDROID_KABI_RESERVE(1);
644672 };
645673 
646674 #define DWC3_EP_FLAG_STALLED	BIT(0)
....@@ -657,7 +685,6 @@
657685  * @cancelled_list: list of cancelled requests for this endpoint
658686  * @pending_list: list of pending requests for this endpoint
659687  * @started_list: list of started requests on this endpoint
660
- * @lock: spinlock for endpoint request queue traversal
661688  * @regs: pointer to first endpoint register
662689  * @trb_pool: array of transaction buffers
663690  * @trb_pool_dma: dma address of @trb_pool
....@@ -685,7 +712,6 @@
685712 	struct list_head	pending_list;
686713 	struct list_head	started_list;
687714 
688
-	spinlock_t		lock;
689715 	void __iomem		*regs;
690716 
691717 	struct dwc3_trb		*trb_pool;
....@@ -693,7 +719,7 @@
693719 	struct dwc3		*dwc;
694720 
695721 	u32			saved_state;
696
-	unsigned		flags;
722
+	unsigned int		flags;
697723 #define DWC3_EP_ENABLED		BIT(0)
698724 #define DWC3_EP_STALL		BIT(1)
699725 #define DWC3_EP_WEDGE		BIT(2)
....@@ -701,6 +727,13 @@
701727 #define DWC3_EP_END_TRANSFER_PENDING BIT(4)
702728 #define DWC3_EP_PENDING_REQUEST	BIT(5)
703729 #define DWC3_EP_DELAY_START	BIT(6)
730
+#define DWC3_EP_WAIT_TRANSFER_COMPLETE	BIT(7)
731
+#define DWC3_EP_IGNORE_NEXT_NOSTREAM	BIT(8)
732
+#define DWC3_EP_FORCE_RESTART_STREAM	BIT(9)
733
+#define DWC3_EP_FIRST_STREAM_PRIMED	BIT(10)
734
+#define DWC3_EP_PENDING_CLEAR_STALL	BIT(11)
735
+#define DWC3_EP_TXFIFO_RESIZED		BIT(12)
736
+#define DWC3_EP_DELAY_STOP             BIT(13)
704737 
705738 	/* This last one is specific to EP0 */
706739 #define DWC3_EP0_DIR_IN		BIT(31)
....@@ -731,6 +764,9 @@
731764 	/* For isochronous START TRANSFER workaround only */
732765 	u8			combo_num;
733766 	int			start_cmd_status;
767
+
768
+	ANDROID_KABI_RESERVE(1);
769
+	ANDROID_KABI_RESERVE(2);
734770 };
735771 
736772 enum dwc3_phy {
....@@ -829,6 +865,7 @@
829865  * @hwparams6: GHWPARAMS6
830866  * @hwparams7: GHWPARAMS7
831867  * @hwparams8: GHWPARAMS8
868
+ * @hwparams9: GHWPARAMS9
832869  */
833870 struct dwc3_hwparams {
834871 	u32	hwparams0;
....@@ -840,15 +877,18 @@
840877 	u32	hwparams6;
841878 	u32	hwparams7;
842879 	u32	hwparams8;
880
+	u32	hwparams9;
881
+
882
+	ANDROID_KABI_RESERVE(1);
883
+	ANDROID_KABI_RESERVE(2);
843884 };
844885 
845886 /* HWPARAMS0 */
846887 #define DWC3_MODE(n)		((n) & 0x7)
847888 
848
-#define DWC3_MDWIDTH(n)		(((n) & 0xff00) >> 8)
849
-
850889 /* HWPARAMS1 */
851890 #define DWC3_NUM_INT(n)		(((n) & (0x3f << 15)) >> 15)
891
+#define DWC3_NUM_RAMS(n)	(((n) & (0x3 << 21)) >> 21)
852892 
853893 /* HWPARAMS3 */
854894 #define DWC3_NUM_IN_EPS_MASK	(0x1f << 18)
....@@ -888,26 +928,31 @@
888928 	struct scatterlist	*sg;
889929 	struct scatterlist	*start_sg;
890930 
891
-	unsigned		num_pending_sgs;
931
+	unsigned int		num_pending_sgs;
892932 	unsigned int		num_queued_sgs;
893
-	unsigned		remaining;
933
+	unsigned int		remaining;
894934 
895935 	unsigned int		status;
896
-#define DWC3_REQUEST_STATUS_QUEUED	0
897
-#define DWC3_REQUEST_STATUS_STARTED	1
898
-#define DWC3_REQUEST_STATUS_CANCELLED	2
899
-#define DWC3_REQUEST_STATUS_COMPLETED	3
900
-#define DWC3_REQUEST_STATUS_UNKNOWN	-1
936
+#define DWC3_REQUEST_STATUS_QUEUED		0
937
+#define DWC3_REQUEST_STATUS_STARTED		1
938
+#define DWC3_REQUEST_STATUS_DISCONNECTED	2
939
+#define DWC3_REQUEST_STATUS_DEQUEUED		3
940
+#define DWC3_REQUEST_STATUS_STALLED		4
941
+#define DWC3_REQUEST_STATUS_COMPLETED		5
942
+#define DWC3_REQUEST_STATUS_UNKNOWN		-1
901943 
902944 	u8			epnum;
903945 	struct dwc3_trb		*trb;
904946 	dma_addr_t		trb_dma;
905947 
906
-	unsigned		num_trbs;
948
+	unsigned int		num_trbs;
907949 
908
-	unsigned		needs_extra_trb:1;
909
-	unsigned		direction:1;
910
-	unsigned		mapped:1;
950
+	unsigned int		needs_extra_trb:1;
951
+	unsigned int		direction:1;
952
+	unsigned int		mapped:1;
953
+
954
+	ANDROID_KABI_RESERVE(1);
955
+	ANDROID_KABI_RESERVE(2);
911956 };
912957 
913958 /*
....@@ -930,8 +975,8 @@
930975  * @ep0_usb_req: dummy req used while handling STD USB requests
931976  * @scratch_addr: dma address of scratchbuf
932977  * @ep0_in_setup: one control transfer is completed and enter setup phase
933
- * @discon_done: disconnect event is completed
934978  * @lock: for synchronizing
979
+ * @mutex: for mode switching
935980  * @dev: pointer to our struct device
936981  * @sysdev: pointer to the DMA-capable device
937982  * @xhci: pointer to our xHCI child
....@@ -954,7 +999,12 @@
954999  * @nr_scratch: number of scratch buffers
9551000  * @u1u2: only used on revisions <1.83a for workaround
9561001  * @maximum_speed: maximum speed requested (mainly for testing purposes)
957
- * @revision: revision register contents
1002
+ * @max_ssp_rate: SuperSpeed Plus maximum signaling rate and lane count
1003
+ * @gadget_max_speed: maximum gadget speed requested
1004
+ * @gadget_ssp_rate: Gadget driver's maximum supported SuperSpeed Plus signaling
1005
+ *			rate and lane count.
1006
+ * @ip: controller's ID
1007
+ * @revision: controller's version of an IP
9581008  * @version_type: VERSIONTYPE register contents, a sub release of a revision
9591009  * @dr_mode: requested mode of operation
9601010  * @current_dr_role: current role of operation when in dual-role mode
....@@ -964,6 +1014,12 @@
9641014  * @hsphy_mode: UTMI phy mode, one of following:
9651015  *		- USBPHY_INTERFACE_MODE_UTMI
9661016  *		- USBPHY_INTERFACE_MODE_UTMIW
1017
+ * @role_sw: usb_role_switch handle
1018
+ * @role_switch_default_mode: default operation mode of controller while
1019
+ *			usb role is USB_ROLE_NONE.
1020
+ * @current_role_sw_mode: current usb role switch mode.
1021
+ * @desired_role_sw_mode: desired usb role switch mode.
1022
+ * @usb_psy: pointer to power supply interface.
9671023  * @usb2_phy: pointer to USB2 PHY
9681024  * @usb3_phy: pointer to USB3 PHY
9691025  * @usb2_generic_phy: pointer to USB2 PHY
....@@ -992,6 +1048,7 @@
9921048  * @rx_max_burst_prd: max periodic ESS receive burst size
9931049  * @tx_thr_num_pkt_prd: periodic ESS transmit packet count
9941050  * @tx_max_burst_prd: max periodic ESS transmit burst size
1051
+ * @tx_fifo_resize_max_num: max number of fifos allocated during txfifo resize
9951052  * @hsphy_interface: "utmi" or "ulpi"
9961053  * @connected: true when we're connected to a host, false otherwise
9971054  * @delayed_status: true when gadget driver asks for delayed status
....@@ -1002,17 +1059,19 @@
10021059  * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
10031060  *			there's now way for software to detect this in runtime.
10041061  * @is_utmi_l1_suspend: the core asserts output signal
1005
- * 	0	- utmi_sleep_n
1006
- * 	1	- utmi_l1_suspend_n
1062
+ *	0	- utmi_sleep_n
1063
+ *	1	- utmi_l1_suspend_n
10071064  * @is_fpga: true when we are using the FPGA board
10081065  * @pending_events: true when we have pending IRQs to be handled
1066
+ * @do_fifo_resize: true when txfifo resizing is enabled for dwc3 endpoints
10091067  * @pullups_connected: true when Run/Stop bit is set
10101068  * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
10111069  * @three_stage_setup: set if we perform a three phase setup
10121070  * @dis_start_transfer_quirk: set if start_transfer failure SW workaround is
10131071  *			not needed for DWC_usb31 version 1.70a-ea06 and below
10141072  * @usb3_lpm_capable: set if hadrware supports Link Power Management
1015
- * @usb2_lpm_disable: set to disable usb2 lpm
1073
+ * @usb2_lpm_disable: set to disable usb2 lpm for host
1074
+ * @usb2_gadget_lpm_disable: set to disable usb2 lpm for gadget
10161075  * @disable_scramble_quirk: set if we enable the disable scramble quirk
10171076  * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
10181077  * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
....@@ -1023,9 +1082,10 @@
10231082  * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
10241083  * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
10251084  * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
1026
- * @dis_u1u2_quirk: set if we reject transition to U1 or U2 state
10271085  * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
10281086  *                      disabling the suspend signal to the PHY.
1087
+ * @dis_u1_entry_quirk: set if link entering into U1 state needs to be disabled.
1088
+ * @dis_u2_entry_quirk: set if link entering into U2 state needs to be disabled.
10291089  * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3
10301090  * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
10311091  *			in GUSB2PHYCFG, specify that USB2 PHY doesn't
....@@ -1036,31 +1096,23 @@
10361096  *			check during HS transmit.
10371097  * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed
10381098  *			instances in park mode.
1039
- * @xhci_slow_suspend_quirk: set if need an extraordinary delay to wait
1040
- *			for xHC enter the Halted state after the Run/Stop
1041
- *			(R/S) bit is cleared to '0'.
1042
- * @xhci_trb_ent_quirk: set if need to enable the Evaluate Next TRB(ENT)
1043
-			flag in the TRB data structure to force xHC to
1044
-			pre-fetch the next TRB of a TD.
1045
- * @xhci_warm_reset_on_suspend_quirk: set if need to do a warm port reset
1046
- *			for xHC USB3 port upon suspend.
1047
- * @dis_u3_autosuspend_quirk: set if the we want to disable usb3 autosuspend
1099
+ * @parkmode_disable_hs_quirk: set if we need to disable all HishSpeed
1100
+ *			instances in park mode.
10481101  * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
10491102  * @tx_de_emphasis: Tx de-emphasis value
1050
- * 	0	- -6dB de-emphasis
1051
- * 	1	- -3.5dB de-emphasis
1052
- * 	2	- No de-emphasis
1053
- * 	3	- Reserved
1103
+ *	0	- -6dB de-emphasis
1104
+ *	1	- -3.5dB de-emphasis
1105
+ *	2	- No de-emphasis
1106
+ *	3	- Reserved
10541107  * @dis_metastability_quirk: set to disable metastability quirk.
1055
- * @needs_fifo_resize: set if we want to resize TXFIFO.
1056
- * @fifo_resize_status: true if the TXFIFOs have been resized.
1057
- * @drd_connected: true when usb connected to a host or a device(drd mode),
1058
- *			false otherwise.
1059
- * @en_runtime: true when need runtime PM management. For example, RK3399 need
1060
- *			reset dwc3 and usb3phy to support typec interface.
1061
- * @uwk_en: true when enable usb wakeup from host resume signal.
1108
+ * @dis_split_quirk: set to disable split boundary.
10621109  * @imod_interval: set the interrupt moderation interval in 250ns
1063
- *                 increments or 0 to disable.
1110
+ *			increments or 0 to disable.
1111
+ * @max_cfg_eps: current max number of IN eps used across all USB configs.
1112
+ * @last_fifo_depth: last fifo depth used to determine next fifo ram start
1113
+ *		     address.
1114
+ * @num_ep_resized: carries the current number endpoints which have had its tx
1115
+ *		    fifo resized.
10641116  */
10651117 struct dwc3 {
10661118 	struct work_struct	drd_work;
....@@ -1073,10 +1125,12 @@
10731125 	dma_addr_t		scratch_addr;
10741126 	struct dwc3_request	ep0_usb_req;
10751127 	struct completion	ep0_in_setup;
1076
-	struct completion	discon_done;
10771128 
10781129 	/* device lock */
10791130 	spinlock_t		lock;
1131
+
1132
+	/* mode switching lock */
1133
+	struct mutex		mutex;
10801134 
10811135 	struct device		*dev;
10821136 	struct device		*sysdev;
....@@ -1087,7 +1141,7 @@
10871141 	struct dwc3_event_buffer *ev_buf;
10881142 	struct dwc3_ep		*eps[DWC3_ENDPOINTS_NUM];
10891143 
1090
-	struct usb_gadget	gadget;
1144
+	struct usb_gadget	*gadget;
10911145 	struct usb_gadget_driver *gadget_driver;
10921146 
10931147 	struct clk_bulk_data	*clks;
....@@ -1115,6 +1169,14 @@
11151169 	struct extcon_dev	*edev;
11161170 	struct notifier_block	edev_nb;
11171171 	enum usb_phy_interface	hsphy_mode;
1172
+	struct usb_role_switch	*role_sw;
1173
+	enum usb_dr_mode	role_switch_default_mode;
1174
+#if defined(CONFIG_ARCH_ROCKCHIP) && defined(CONFIG_NO_GKI)
1175
+	u32			current_role_sw_mode;
1176
+	u32			desired_role_sw_mode;
1177
+#endif
1178
+
1179
+	struct power_supply	*usb_psy;
11181180 
11191181 	u32			fladj;
11201182 	u32			irq_gadget;
....@@ -1125,16 +1187,19 @@
11251187 	u32			nr_scratch;
11261188 	u32			u1u2;
11271189 	u32			maximum_speed;
1190
+	u32			gadget_max_speed;
1191
+	enum usb_ssp_rate	max_ssp_rate;
1192
+	enum usb_ssp_rate	gadget_ssp_rate;
11281193 
1129
-	/*
1130
-	 * All 3.1 IP version constants are greater than the 3.0 IP
1131
-	 * version constants. This works for most version checks in
1132
-	 * dwc3. However, in the future, this may not apply as
1133
-	 * features may be developed on newer versions of the 3.0 IP
1134
-	 * that are not in the 3.1 IP.
1135
-	 */
1194
+	u32			ip;
1195
+
1196
+#define DWC3_IP			0x5533
1197
+#define DWC31_IP		0x3331
1198
+#define DWC32_IP		0x3332
1199
+
11361200 	u32			revision;
11371201 
1202
+#define DWC3_REVISION_ANY	0x0
11381203 #define DWC3_REVISION_173A	0x5533173a
11391204 #define DWC3_REVISION_175A	0x5533175a
11401205 #define DWC3_REVISION_180A	0x5533180a
....@@ -1159,18 +1224,20 @@
11591224 #define DWC3_REVISION_310A	0x5533310a
11601225 #define DWC3_REVISION_330A	0x5533330a
11611226 
1162
-/*
1163
- * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really
1164
- * just so dwc31 revisions are always larger than dwc3.
1165
- */
1166
-#define DWC3_REVISION_IS_DWC31		0x80000000
1167
-#define DWC3_USB31_REVISION_110A	(0x3131302a | DWC3_REVISION_IS_DWC31)
1168
-#define DWC3_USB31_REVISION_120A	(0x3132302a | DWC3_REVISION_IS_DWC31)
1169
-#define DWC3_USB31_REVISION_160A	(0x3136302a | DWC3_REVISION_IS_DWC31)
1170
-#define DWC3_USB31_REVISION_170A	(0x3137302a | DWC3_REVISION_IS_DWC31)
1227
+#define DWC31_REVISION_ANY	0x0
1228
+#define DWC31_REVISION_110A	0x3131302a
1229
+#define DWC31_REVISION_120A	0x3132302a
1230
+#define DWC31_REVISION_160A	0x3136302a
1231
+#define DWC31_REVISION_170A	0x3137302a
1232
+#define DWC31_REVISION_180A	0x3138302a
1233
+#define DWC31_REVISION_190A	0x3139302a
1234
+
1235
+#define DWC32_REVISION_ANY	0x0
1236
+#define DWC32_REVISION_100A	0x3130302a
11711237 
11721238 	u32			version_type;
11731239 
1240
+#define DWC31_VERSIONTYPE_ANY		0x0
11741241 #define DWC31_VERSIONTYPE_EA01		0x65613031
11751242 #define DWC31_VERSIONTYPE_EA02		0x65613032
11761243 #define DWC31_VERSIONTYPE_EA03		0x65613033
....@@ -1205,6 +1272,7 @@
12051272 	u8			rx_max_burst_prd;
12061273 	u8			tx_thr_num_pkt_prd;
12071274 	u8			tx_max_burst_prd;
1275
+	u8			tx_fifo_resize_max_num;
12081276 
12091277 	const char		*hsphy_interface;
12101278 
....@@ -1218,12 +1286,14 @@
12181286 	unsigned		is_utmi_l1_suspend:1;
12191287 	unsigned		is_fpga:1;
12201288 	unsigned		pending_events:1;
1289
+	unsigned		do_fifo_resize:1;
12211290 	unsigned		pullups_connected:1;
12221291 	unsigned		setup_packet_pending:1;
12231292 	unsigned		three_stage_setup:1;
12241293 	unsigned		dis_start_transfer_quirk:1;
12251294 	unsigned		usb3_lpm_capable:1;
12261295 	unsigned		usb2_lpm_disable:1;
1296
+	unsigned		usb2_gadget_lpm_disable:1;
12271297 
12281298 	unsigned		disable_scramble_quirk:1;
12291299 	unsigned		u2exit_lfps_quirk:1;
....@@ -1235,29 +1305,48 @@
12351305 	unsigned		rx_detect_poll_quirk:1;
12361306 	unsigned		dis_u3_susphy_quirk:1;
12371307 	unsigned		dis_u2_susphy_quirk:1;
1238
-	unsigned		dis_u1u2_quirk:1;
12391308 	unsigned		dis_enblslpm_quirk:1;
1309
+	unsigned		dis_u1_entry_quirk:1;
1310
+	unsigned		dis_u2_entry_quirk:1;
12401311 	unsigned		dis_rxdet_inp3_quirk:1;
12411312 	unsigned		dis_u2_freeclk_exists_quirk:1;
12421313 	unsigned		dis_del_phy_power_chg_quirk:1;
12431314 	unsigned		dis_tx_ipgap_linecheck_quirk:1;
12441315 	unsigned		parkmode_disable_ss_quirk:1;
1245
-	unsigned		xhci_slow_suspend_quirk:1;
1246
-	unsigned		xhci_trb_ent_quirk:1;
1247
-	unsigned		xhci_warm_reset_on_suspend_quirk:1;
1248
-	unsigned		dis_u3_autosuspend_quirk:1;
1316
+#ifdef CONFIG_NO_GKI
1317
+	unsigned		parkmode_disable_hs_quirk:1;
1318
+#endif
12491319 
12501320 	unsigned		tx_de_emphasis_quirk:1;
12511321 	unsigned		tx_de_emphasis:2;
12521322 
12531323 	unsigned		dis_metastability_quirk:1;
1254
-	unsigned		needs_fifo_resize:1;
1255
-	unsigned		fifo_resize_status:1;
1256
-	unsigned		drd_connected:1;
1257
-	unsigned		en_runtime:1;
1258
-	unsigned		uwk_en:1;
1324
+
1325
+	unsigned		dis_split_quirk:1;
1326
+	unsigned		async_callbacks:1;
12591327 
12601328 	u16			imod_interval;
1329
+
1330
+	int			max_cfg_eps;
1331
+	int			last_fifo_depth;
1332
+	int			num_ep_resized;
1333
+
1334
+	ANDROID_KABI_RESERVE(1);
1335
+	ANDROID_KABI_RESERVE(2);
1336
+	ANDROID_KABI_RESERVE(3);
1337
+	ANDROID_KABI_RESERVE(4);
1338
+};
1339
+
1340
+/**
1341
+ * struct dwc3_vendor - contains parameters without modifying the format of DWC3 core
1342
+ * @dwc: contains dwc3 core reference
1343
+ * @clear_stall_protocol: endpoint number that requires a delayed status phase
1344
+ * @softconnect: true when gadget connect is called, false when disconnect runs
1345
+ */
1346
+struct dwc3_vendor {
1347
+	struct dwc3	dwc;
1348
+	u8		clear_stall_protocol;
1349
+	unsigned	softconnect:1;
12611350 };
12621351 
12631352 #define INCRX_BURST_MODE 0
....@@ -1281,7 +1370,7 @@
12811370 #define DWC3_DEPEVT_EPCMDCMPLT		0x07
12821371 
12831372 /**
1284
- * struct dwc3_event_depvt - Device Endpoint Events
1373
+ * struct dwc3_event_depevt - Device Endpoint Events
12851374  * @one_bit: indicates this is an endpoint event (not used)
12861375  * @endpoint_number: number of the endpoint
12871376  * @endpoint_event: The event we have:
....@@ -1320,6 +1409,10 @@
13201409 #define DEPEVT_STREAMEVT_FOUND		1
13211410 #define DEPEVT_STREAMEVT_NOTFOUND	2
13221411 
1412
+/* Stream event parameter */
1413
+#define DEPEVT_STREAM_PRIME		0xfffe
1414
+#define DEPEVT_STREAM_NOSTREAM		0x0
1415
+
13231416 /* Control-only Status */
13241417 #define DEPEVT_STATUS_CONTROL_DATA	1
13251418 #define DEPEVT_STATUS_CONTROL_STATUS	2
....@@ -1346,7 +1439,7 @@
13461439  *	3	- ULStChng
13471440  *	4	- WkUpEvt
13481441  *	5	- Reserved
1349
- *	6	- EOPF
1442
+ *	6	- Suspend (EOPF on revisions 2.10a and prior)
13501443  *	7	- SOF
13511444  *	8	- Reserved
13521445  *	9	- ErrticErr
....@@ -1422,22 +1515,50 @@
14221515 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
14231516 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
14241517 
1425
-/* check whether we are on the DWC_usb3 core */
1426
-static inline bool dwc3_is_usb3(struct dwc3 *dwc)
1427
-{
1428
-	return !(dwc->revision & DWC3_REVISION_IS_DWC31);
1429
-}
1518
+#define DWC3_IP_IS(_ip)							\
1519
+	(dwc->ip == _ip##_IP)
14301520 
1431
-/* check whether we are on the DWC_usb31 core */
1432
-static inline bool dwc3_is_usb31(struct dwc3 *dwc)
1521
+#define DWC3_VER_IS(_ip, _ver)						\
1522
+	(DWC3_IP_IS(_ip) && dwc->revision == _ip##_REVISION_##_ver)
1523
+
1524
+#define DWC3_VER_IS_PRIOR(_ip, _ver)					\
1525
+	(DWC3_IP_IS(_ip) && dwc->revision < _ip##_REVISION_##_ver)
1526
+
1527
+#define DWC3_VER_IS_WITHIN(_ip, _from, _to)				\
1528
+	(DWC3_IP_IS(_ip) &&						\
1529
+	 dwc->revision >= _ip##_REVISION_##_from &&			\
1530
+	 (!(_ip##_REVISION_##_to) ||					\
1531
+	  dwc->revision <= _ip##_REVISION_##_to))
1532
+
1533
+#define DWC3_VER_TYPE_IS_WITHIN(_ip, _ver, _from, _to)			\
1534
+	(DWC3_VER_IS(_ip, _ver) &&					\
1535
+	 dwc->version_type >= _ip##_VERSIONTYPE_##_from &&		\
1536
+	 (!(_ip##_VERSIONTYPE_##_to) ||					\
1537
+	  dwc->version_type <= _ip##_VERSIONTYPE_##_to))
1538
+
1539
+/**
1540
+ * dwc3_mdwidth - get MDWIDTH value in bits
1541
+ * @dwc: pointer to our context structure
1542
+ *
1543
+ * Return MDWIDTH configuration value in bits.
1544
+ */
1545
+static inline u32 dwc3_mdwidth(struct dwc3 *dwc)
14331546 {
1434
-	return !!(dwc->revision & DWC3_REVISION_IS_DWC31);
1547
+	u32 mdwidth;
1548
+
1549
+	mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1550
+	if (DWC3_IP_IS(DWC32))
1551
+		mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6);
1552
+
1553
+	return mdwidth;
14351554 }
14361555 
14371556 bool dwc3_has_imod(struct dwc3 *dwc);
14381557 
14391558 int dwc3_event_buffers_setup(struct dwc3 *dwc);
14401559 void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
1560
+
1561
+int dwc3_core_soft_reset(struct dwc3 *dwc);
14411562 
14421563 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
14431564 int dwc3_host_init(struct dwc3 *dwc);
....@@ -1455,11 +1576,13 @@
14551576 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
14561577 int dwc3_gadget_get_link_state(struct dwc3 *dwc);
14571578 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1458
-int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1579
+int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
14591580 		struct dwc3_gadget_ep_cmd_params *params);
1460
-int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1461
-void dwc3_gadget_disable_irq(struct dwc3 *dwc);
1462
-void dwc3_gadget_enable_irq(struct dwc3 *dwc);
1581
+int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
1582
+		u32 param);
1583
+void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, bool interrupt);
1584
+void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc);
1585
+void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep, int status);
14631586 #else
14641587 static inline int dwc3_gadget_init(struct dwc3 *dwc)
14651588 { return 0; }
....@@ -1473,15 +1596,16 @@
14731596 		enum dwc3_link_state state)
14741597 { return 0; }
14751598 
1476
-static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1599
+static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
14771600 		struct dwc3_gadget_ep_cmd_params *params)
14781601 { return 0; }
14791602 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
14801603 		int cmd, u32 param)
14811604 { return 0; }
1482
-static inline void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1605
+static inline void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
1606
+					     bool interrupt)
14831607 { }
1484
-static inline void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1608
+static inline void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
14851609 { }
14861610 #endif
14871611