.. | .. |
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4 | 4 | tristate "DesignWare USB3 DRD Core Support" |
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5 | 5 | depends on (USB || USB_GADGET) && HAS_DMA |
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6 | 6 | select USB_XHCI_PLATFORM if USB_XHCI_HCD |
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| 7 | + select USB_ROLE_SWITCH if USB_DWC3_DUAL_ROLE |
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7 | 8 | help |
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8 | 9 | Say Y or M here if your system has a Dual Role SuperSpeed |
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9 | 10 | USB controller based on the DesignWare USB3 IP Core. |
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.. | .. |
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89 | 90 | platform, please say 'Y' or 'M' here. |
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90 | 91 | |
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91 | 92 | config USB_DWC3_KEYSTONE |
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92 | | - tristate "Texas Instruments Keystone2 Platforms" |
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93 | | - depends on ARCH_KEYSTONE || COMPILE_TEST |
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| 93 | + tristate "Texas Instruments Keystone2/AM654 Platforms" |
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| 94 | + depends on ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST |
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94 | 95 | default USB_DWC3 |
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95 | 96 | help |
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96 | | - Support of USB2/3 functionality in TI Keystone2 platforms. |
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| 97 | + Support of USB2/3 functionality in TI Keystone2 and AM654 platforms. |
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97 | 98 | Say 'Y' or 'M' here if you have one such device |
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98 | 99 | |
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| 100 | +config USB_DWC3_MESON_G12A |
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| 101 | + tristate "Amlogic Meson G12A Platforms" |
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| 102 | + depends on OF && COMMON_CLK |
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| 103 | + depends on ARCH_MESON || COMPILE_TEST |
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| 104 | + default USB_DWC3 |
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| 105 | + select USB_ROLE_SWITCH |
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| 106 | + select REGMAP_MMIO |
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| 107 | + help |
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| 108 | + Support USB2/3 functionality in Amlogic G12A platforms. |
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| 109 | + Say 'Y' or 'M' if you have one such device. |
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| 110 | + |
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99 | 111 | config USB_DWC3_OF_SIMPLE |
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100 | | - tristate "Generic OF Simple Glue Layer" |
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101 | | - depends on OF && COMMON_CLK |
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102 | | - default USB_DWC3 |
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103 | | - help |
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104 | | - Support USB2/3 functionality in simple SoC integrations. |
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105 | | - Currently supports Xilinx and Qualcomm DWC USB3 IP. |
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106 | | - Say 'Y' or 'M' if you have one such device. |
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| 112 | + tristate "Generic OF Simple Glue Layer" |
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| 113 | + depends on OF && COMMON_CLK |
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| 114 | + default USB_DWC3 |
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| 115 | + help |
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| 116 | + Support USB2/3 functionality in simple SoC integrations. |
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| 117 | + Currently supports Xilinx and Qualcomm DWC USB3 IP. |
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| 118 | + Say 'Y' or 'M' if you have one such device. |
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107 | 119 | |
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108 | 120 | config USB_DWC3_ROCKCHIP_INNO |
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109 | | - tristate "Rockchip Platforms with INNO PHY" |
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| 121 | + bool "Rockchip Platforms with INNO PHY" |
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110 | 122 | depends on OF && COMMON_CLK && (ARCH_ROCKCHIP || COMPILE_TEST) |
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111 | | - depends on USB=y || USB=USB_DWC3 |
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112 | | - default USB_DWC3 |
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| 123 | + default USB_DWC3 && PHY_ROCKCHIP_INNO_USB3 && NO_GKI |
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113 | 124 | help |
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114 | 125 | Support of USB2/3 functionality in Rockchip platforms |
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115 | 126 | with INNO USB 3.0 PHY IP inside. |
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.. | .. |
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128 | 139 | tristate "Qualcomm Platform" |
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129 | 140 | depends on ARCH_QCOM || COMPILE_TEST |
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130 | 141 | depends on EXTCON || !EXTCON |
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131 | | - depends on OF |
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| 142 | + depends on (OF || ACPI) |
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132 | 143 | default USB_DWC3 |
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133 | 144 | help |
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134 | 145 | Some Qualcomm SoCs use DesignWare Core IP for USB2/3 |
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.. | .. |
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137 | 148 | for peripheral mode support. |
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138 | 149 | Say 'Y' or 'M' if you have one such device. |
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139 | 150 | |
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| 151 | +config USB_DWC3_IMX8MP |
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| 152 | + tristate "NXP iMX8MP Platform" |
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| 153 | + depends on OF && COMMON_CLK |
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| 154 | + depends on (ARCH_MXC && ARM64) || COMPILE_TEST |
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| 155 | + default USB_DWC3 |
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| 156 | + help |
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| 157 | + NXP iMX8M Plus SoC use DesignWare Core IP for USB2/3 |
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| 158 | + functionality. |
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| 159 | + Say 'Y' or 'M' if you have one such device. |
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| 160 | + |
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140 | 161 | endif |
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