.. | .. |
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112 | 112 | /* HYF2GQ4UHCCAE */ |
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113 | 113 | { 0xC9, 0x5A, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, |
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114 | 114 | /* HYF4GQ4UAACBE */ |
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115 | | - { 0xC9, 0xD4, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0xE, 1, { 0x20, 0x40, 0x24, 0x44 }, &sfc_nand_get_ecc_status0 }, |
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116 | | - /* HYF2GQ4IAACAE */ |
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117 | | - { 0xC9, 0x82, 0x00, 4, 0x40, 1, 2048, 0x4C, 20, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, |
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118 | | - /* HYF1GQ4IDACAE */ |
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119 | | - { 0xC9, 0x81, 0x00, 4, 0x40, 1, 1024, 0x4C, 20, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, |
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| 115 | + { 0xC9, 0xD4, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x4, 1, { 0x20, 0x40, 0x24, 0x44 }, &sfc_nand_get_ecc_status0 }, |
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120 | 116 | |
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121 | 117 | /* FS35ND01G-S1 */ |
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122 | 118 | { 0xCD, 0xB1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, |
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.. | .. |
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153 | 149 | { 0xE5, 0xF4, 0x00, 4, 0x40, 2, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, |
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154 | 150 | /* DS35M1GB-IB */ |
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155 | 151 | { 0xE5, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, |
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156 | | - /* DS35Q12B-IB */ |
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157 | | - { 0xE5, 0xF5, 0x00, 4, 0x40, 1, 512, 0x0C, 17, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, |
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158 | | - /* DS35M12B-IB */ |
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159 | | - { 0xE5, 0xA5, 0x00, 4, 0x40, 1, 512, 0x0C, 17, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, |
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160 | 152 | |
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161 | 153 | /* EM73C044VCC-H */ |
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162 | 154 | { 0xD5, 0x22, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, |
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.. | .. |
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214 | 206 | { 0xEA, 0xC1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, |
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215 | 207 | /* TX25G01 */ |
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216 | 208 | { 0xA1, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status8 }, |
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217 | | - /* ANV1GCP0CLG, HYF1GQ4UTXCAE */ |
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218 | | - { 0x01, 0x15, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status9 }, |
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219 | | - /* S35ML02G3, ANV1GCP0CLG */ |
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220 | | - { 0x01, 0x25, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x4, 0, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status9 }, |
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| 209 | + /* S35ML02G3 */ |
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| 210 | + { 0x01, 0x25, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x4, 1, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status9 }, |
---|
221 | 211 | /* S35ML04G3 */ |
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222 | | - { 0x01, 0x35, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 0, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status9 }, |
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223 | | - /* GSS01GSAK1 */ |
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224 | | - { 0x52, 0xBA, 0x13, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, |
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225 | | - /* GSS02GSAK1 */ |
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226 | | - { 0x52, 0xBA, 0x23, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, |
---|
| 212 | + { 0x01, 0x35, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status9 }, |
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227 | 213 | }; |
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228 | 214 | |
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229 | 215 | static struct nand_info *p_nand_info; |
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.. | .. |
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325 | 311 | return ret; |
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326 | 312 | } |
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327 | 313 | |
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328 | | -static int sfc_nand_wait_busy(u8 *data, int timeout) |
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| 314 | +static int sfc_nand_wait_busy_sleep(u8 *data, int timeout, int sleep_us) |
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329 | 315 | { |
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330 | 316 | int ret; |
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331 | 317 | int i; |
---|
.. | .. |
---|
333 | 319 | |
---|
334 | 320 | *data = 0; |
---|
335 | 321 | |
---|
336 | | - for (i = 0; i < timeout; i++) { |
---|
| 322 | + for (i = 0; i < timeout; i += sleep_us) { |
---|
| 323 | + usleep_range(sleep_us, sleep_us + 50); |
---|
| 324 | + |
---|
337 | 325 | ret = sfc_nand_read_feature(0xC0, &status); |
---|
338 | 326 | |
---|
339 | 327 | if (ret != SFC_OK) |
---|
.. | .. |
---|
343 | 331 | |
---|
344 | 332 | if (!(status & (1 << 0))) |
---|
345 | 333 | return SFC_OK; |
---|
346 | | - |
---|
347 | | - sfc_delay(1); |
---|
348 | 334 | } |
---|
349 | 335 | |
---|
350 | 336 | return SFC_NAND_WAIT_TIME_OUT; |
---|
.. | .. |
---|
808 | 794 | if (ret != SFC_OK) |
---|
809 | 795 | return ret; |
---|
810 | 796 | |
---|
811 | | - ret = sfc_nand_wait_busy(&status, 1000 * 1000); |
---|
| 797 | + ret = sfc_nand_wait_busy_sleep(&status, 1000 * 1000, 1000); |
---|
812 | 798 | |
---|
813 | 799 | if (status & (1 << 2)) |
---|
814 | 800 | return SFC_NAND_PROG_ERASE_ERROR; |
---|
.. | .. |
---|
865 | 851 | op.sfctrl.d32 = 0; |
---|
866 | 852 | op.sfctrl.b.datalines = sfc_nand_dev.prog_lines; |
---|
867 | 853 | op.sfctrl.b.addrbits = 16; |
---|
| 854 | + op.sfctrl.b.enbledma = 0; |
---|
868 | 855 | plane = p_nand_info->plane_per_die == 2 ? ((addr >> 6) & 0x1) << 12 : 0; |
---|
869 | 856 | sfc_request(&op, plane, p_page_buf, page_size); |
---|
870 | 857 | |
---|
.. | .. |
---|
877 | 864 | if (p_nand_info->id0 == MID_GIGADEV) { |
---|
878 | 865 | sfc_nand_read_cache(addr, (u32 *)sfc_nand_dev.recheck_buffer, 0, data_area_size); |
---|
879 | 866 | if (memcmp(sfc_nand_dev.recheck_buffer, p_page_buf, data_area_size)) { |
---|
880 | | - rkflash_print_error("%s %x cache bitflip\n", __func__, addr); |
---|
| 867 | + rkflash_print_error("%s cache bitflip1\n", __func__); |
---|
881 | 868 | msleep(1000); |
---|
882 | 869 | sfc_request(&op, plane, p_page_buf, page_size); |
---|
883 | 870 | } |
---|
.. | .. |
---|
894 | 881 | if (ret != SFC_OK) |
---|
895 | 882 | return ret; |
---|
896 | 883 | |
---|
897 | | - ret = sfc_nand_wait_busy(&status, 1000 * 1000); |
---|
| 884 | + ret = sfc_nand_wait_busy_sleep(&status, 1000 * 1000, 200); |
---|
| 885 | + |
---|
898 | 886 | if (status & (1 << 3)) |
---|
899 | 887 | return SFC_NAND_PROG_ERASE_ERROR; |
---|
900 | 888 | |
---|
.. | .. |
---|
945 | 933 | sfc_get_version() < SFC_VER_3) |
---|
946 | 934 | sfc_nand_rw_preset(); |
---|
947 | 935 | |
---|
948 | | - sfc_nand_wait_busy(&status, 1000 * 1000); |
---|
| 936 | + sfc_nand_wait_busy_sleep(&status, 1000 * 1000, 50); |
---|
949 | 937 | if (sfc_nand_dev.manufacturer == 0x01 && status) |
---|
950 | | - sfc_nand_wait_busy(&status, 1000 * 1000); |
---|
| 938 | + sfc_nand_wait_busy_sleep(&status, 1000 * 1000, 50); |
---|
951 | 939 | |
---|
952 | 940 | ecc_result = p_nand_info->ecc_status(); |
---|
953 | 941 | |
---|
.. | .. |
---|
959 | 947 | op.sfctrl.d32 = 0; |
---|
960 | 948 | op.sfctrl.b.datalines = sfc_nand_dev.read_lines; |
---|
961 | 949 | op.sfctrl.b.addrbits = 16; |
---|
| 950 | + op.sfctrl.b.enbledma = 0; |
---|
962 | 951 | |
---|
963 | 952 | plane = p_nand_info->plane_per_die == 2 ? ((row >> 6) & 0x1) << 12 : 0; |
---|
964 | 953 | ret = sfc_request(&op, plane | column, p_page_buf, len); |
---|
.. | .. |
---|
983 | 972 | u32 sec_per_page = p_nand_info->sec_per_page; |
---|
984 | 973 | u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE; |
---|
985 | 974 | struct nand_mega_area *meta = &p_nand_info->meta; |
---|
| 975 | + int retries = 0; |
---|
986 | 976 | |
---|
| 977 | +retry: |
---|
987 | 978 | ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); |
---|
988 | 979 | memcpy(p_data, gp_page_buf, data_size); |
---|
989 | 980 | p_spare[0] = gp_page_buf[(data_size + meta->off0) / 4]; |
---|
.. | .. |
---|
1005 | 996 | |
---|
1006 | 997 | if (p_spare) |
---|
1007 | 998 | rkflash_print_hex("spare:", p_spare, 4, 2); |
---|
| 999 | + if (ret == SFC_NAND_ECC_ERROR && retries < 1) { |
---|
| 1000 | + retries++; |
---|
| 1001 | + goto retry; |
---|
| 1002 | + } |
---|
1008 | 1003 | } |
---|
1009 | 1004 | |
---|
1010 | 1005 | return ret; |
---|