kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/drivers/pwm/pwm-rockchip.c
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@@ -169,7 +169,7 @@
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 			       const struct pwm_state *state)
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 {
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 	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
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-	unsigned long period, duty;
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+	unsigned long period, duty, delay_ns;
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 	unsigned long flags;
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 	u64 div;
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 	u32 ctrl;
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@@ -191,11 +191,13 @@
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 	div = (u64)pc->clk_rate * state->duty_cycle;
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 	duty = DIV_ROUND_CLOSEST_ULL(div, dclk_div * pc->data->prescaler * NSEC_PER_SEC);
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+	if (pc->data->supports_lock) {
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+		div = (u64)10 * NSEC_PER_SEC * dclk_div * pc->data->prescaler;
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+		delay_ns = DIV_ROUND_UP_ULL(div, pc->clk_rate);
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+	}
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+
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 	local_irq_save(flags);
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-	/*
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-	 * Lock the period and duty of previous configuration, then
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-	 * change the duty and period, that would not be effective.
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-	 */
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+
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 	ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
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 	if (pc->data->vop_pwm) {
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 		if (pc->vop_pwm_en)
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@@ -253,6 +255,10 @@
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 	}
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 #endif
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+	/*
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+	 * Lock the period and duty of previous configuration, then
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+	 * change the duty and period, that would not be effective.
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+	 */
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 	if (pc->data->supports_lock) {
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 		ctrl |= PWM_LOCK_EN;
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 		writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);
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@@ -270,12 +276,14 @@
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 	}
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 	/*
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-	 * Unlock and set polarity at the same time,
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-	 * the configuration of duty, period and polarity
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-	 * would be effective together at next period.
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+	 * Unlock and set polarity at the same time, the configuration of duty,
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+	 * period and polarity would be effective together at next period. It
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+	 * takes 10 dclk cycles to make sure lock works before unlocking.
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 	 */
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-	if (pc->data->supports_lock)
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+	if (pc->data->supports_lock) {
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 		ctrl &= ~PWM_LOCK_EN;
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+		ndelay(delay_ns);
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+	}
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 	writel(ctrl, pc->base + pc->data->regs.ctrl);
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 	local_irq_restore(flags);