hc
2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f
kernel/drivers/pci/pci.h
....@@ -2,8 +2,11 @@
22 #ifndef DRIVERS_PCI_H
33 #define DRIVERS_PCI_H
44
5
-#include <linux/android_kabi.h>
65 #include <linux/pci.h>
6
+#include <linux/android_kabi.h>
7
+
8
+/* Number of possible devfns: 0.0 to 1f.7 inclusive */
9
+#define MAX_NR_DEVFNS 256
710
811 #define PCI_FIND_CAP_TTL 48
912
....@@ -13,6 +16,7 @@
1316 extern bool pci_early_dump;
1417
1518 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
19
+bool pcie_cap_has_rtctl(const struct pci_dev *dev);
1620
1721 /* Functions internal to the PCI core code */
1822
....@@ -40,8 +44,14 @@
4044 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
4145 int pci_bus_error_reset(struct pci_dev *dev);
4246
47
+#define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
48
+#define PCI_PM_D3HOT_WAIT 10 /* msec */
49
+#define PCI_PM_D3COLD_WAIT 100 /* msec */
50
+
4351 /**
4452 * struct pci_platform_pm_ops - Firmware PM callbacks
53
+ *
54
+ * @bridge_d3: Does the bridge allow entering into D3
4555 *
4656 * @is_manageable: returns 'true' if given device is power manageable by the
4757 * platform firmware
....@@ -49,6 +59,8 @@
4959 * @set_state: invokes the platform firmware to set the device's power state
5060 *
5161 * @get_state: queries the platform firmware for a device's current power state
62
+ *
63
+ * @refresh_state: asks the platform to refresh the device's power state data
5264 *
5365 * @choose_state: returns PCI power state of given device preferred by the
5466 * platform; to be used during system-wide transitions from a
....@@ -64,9 +76,11 @@
6476 * these callbacks are mandatory.
6577 */
6678 struct pci_platform_pm_ops {
79
+ bool (*bridge_d3)(struct pci_dev *dev);
6780 bool (*is_manageable)(struct pci_dev *dev);
6881 int (*set_state)(struct pci_dev *dev, pci_power_t state);
6982 pci_power_t (*get_state)(struct pci_dev *dev);
83
+ void (*refresh_state)(struct pci_dev *dev);
7084 pci_power_t (*choose_state)(struct pci_dev *dev);
7185 int (*set_wakeup)(struct pci_dev *dev, bool enable);
7286 bool (*need_resume)(struct pci_dev *dev);
....@@ -74,13 +88,18 @@
7488
7589 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
7690 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
77
-void pci_power_up(struct pci_dev *dev);
91
+void pci_refresh_power_state(struct pci_dev *dev);
92
+int pci_power_up(struct pci_dev *dev);
7893 void pci_disable_enabled_device(struct pci_dev *dev);
7994 int pci_finish_runtime_suspend(struct pci_dev *dev);
95
+void pcie_clear_device_status(struct pci_dev *dev);
8096 void pcie_clear_root_pme_status(struct pci_dev *dev);
97
+bool pci_check_pme_status(struct pci_dev *dev);
98
+void pci_pme_wakeup_bus(struct pci_bus *bus);
8199 int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
82100 void pci_pme_restore(struct pci_dev *dev);
83
-bool pci_dev_keep_suspended(struct pci_dev *dev);
101
+bool pci_dev_need_resume(struct pci_dev *dev);
102
+void pci_dev_adjust_pme(struct pci_dev *dev);
84103 void pci_dev_complete_resume(struct pci_dev *pci_dev);
85104 void pci_config_pm_runtime_get(struct pci_dev *dev);
86105 void pci_config_pm_runtime_put(struct pci_dev *dev);
....@@ -90,6 +109,7 @@
90109 void pci_free_cap_save_buffers(struct pci_dev *dev);
91110 bool pci_bridge_d3_possible(struct pci_dev *dev);
92111 void pci_bridge_d3_update(struct pci_dev *dev);
112
+void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev);
93113
94114 static inline void pci_wakeup_event(struct pci_dev *dev)
95115 {
....@@ -111,10 +131,24 @@
111131 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
112132 }
113133
134
+static inline bool pcie_downstream_port(const struct pci_dev *dev)
135
+{
136
+ int type = pci_pcie_type(dev);
137
+
138
+ return type == PCI_EXP_TYPE_ROOT_PORT ||
139
+ type == PCI_EXP_TYPE_DOWNSTREAM ||
140
+ type == PCI_EXP_TYPE_PCIE_BRIDGE;
141
+}
142
+
114143 int pci_vpd_init(struct pci_dev *dev);
115144 void pci_vpd_release(struct pci_dev *dev);
116145 void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev);
117146 void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev);
147
+
148
+/* PCI Virtual Channel */
149
+int pci_save_vc_state(struct pci_dev *dev);
150
+void pci_restore_vc_state(struct pci_dev *dev);
151
+void pci_allocate_vc_save_buffers(struct pci_dev *dev);
118152
119153 /* PCI /proc functions */
120154 #ifdef CONFIG_PROC_FS
....@@ -144,7 +178,7 @@
144178
145179 extern raw_spinlock_t pci_lock;
146180
147
-extern unsigned int pci_pm_d3_delay;
181
+extern unsigned int pci_pm_d3hot_delay;
148182
149183 #ifdef CONFIG_PCI_MSI
150184 void pci_no_msi(void);
....@@ -189,6 +223,10 @@
189223 extern const struct device_type pci_dev_type;
190224 extern const struct attribute_group *pci_bus_groups[];
191225
226
+extern unsigned long pci_hotplug_io_size;
227
+extern unsigned long pci_hotplug_mmio_size;
228
+extern unsigned long pci_hotplug_mmio_pref_size;
229
+extern unsigned long pci_hotplug_bus_size;
192230
193231 /**
194232 * pci_match_one_device - Tell if a PCI device structure has a matching
....@@ -229,6 +267,9 @@
229267 pci_bar_mem64, /* A 64-bit memory BAR */
230268 };
231269
270
+struct device *pci_get_host_bridge_device(struct pci_dev *dev);
271
+void pci_put_host_bridge_device(struct device *dev);
272
+
232273 int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
233274 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
234275 int crs_timeout);
....@@ -249,28 +290,35 @@
249290
250291 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
251292 void pci_disable_bridge_window(struct pci_dev *dev);
293
+struct pci_bus *pci_bus_get(struct pci_bus *bus);
294
+void pci_bus_put(struct pci_bus *bus);
252295
253
-/* PCIe link information */
254
-#define PCIE_SPEED2STR(speed) \
255
- ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \
256
- (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \
257
- (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \
258
- (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \
259
- "Unknown speed")
296
+/* PCIe link information from Link Capabilities 2 */
297
+#define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
298
+ ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
299
+ (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
300
+ (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
301
+ (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
302
+ (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
303
+ PCI_SPEED_UNKNOWN)
260304
261305 /* PCIe speed to Mb/s reduced by encoding overhead */
262306 #define PCIE_SPEED2MBS_ENC(speed) \
263
- ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
307
+ ((speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
308
+ (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
264309 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
265310 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
266311 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
267312 0)
268313
314
+const char *pci_speed_string(enum pci_bus_speed speed);
269315 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
270316 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
271317 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
272318 enum pcie_link_width *width);
273319 void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
320
+void pcie_report_downtraining(struct pci_dev *dev);
321
+void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
274322
275323 /* Single Root I/O Virtualization */
276324 struct pci_sriov {
....@@ -303,20 +351,72 @@
303351 ANDROID_KABI_RESERVE(4);
304352 };
305353
306
-/* pci_dev priv_flags */
307
-#define PCI_DEV_DISCONNECTED 0
308
-#define PCI_DEV_ADDED 1
354
+/**
355
+ * pci_dev_set_io_state - Set the new error state if possible.
356
+ *
357
+ * @dev - pci device to set new error_state
358
+ * @new - the state we want dev to be in
359
+ *
360
+ * Must be called with device_lock held.
361
+ *
362
+ * Returns true if state has been changed to the requested state.
363
+ */
364
+static inline bool pci_dev_set_io_state(struct pci_dev *dev,
365
+ pci_channel_state_t new)
366
+{
367
+ bool changed = false;
368
+
369
+ device_lock_assert(&dev->dev);
370
+ switch (new) {
371
+ case pci_channel_io_perm_failure:
372
+ switch (dev->error_state) {
373
+ case pci_channel_io_frozen:
374
+ case pci_channel_io_normal:
375
+ case pci_channel_io_perm_failure:
376
+ changed = true;
377
+ break;
378
+ }
379
+ break;
380
+ case pci_channel_io_frozen:
381
+ switch (dev->error_state) {
382
+ case pci_channel_io_frozen:
383
+ case pci_channel_io_normal:
384
+ changed = true;
385
+ break;
386
+ }
387
+ break;
388
+ case pci_channel_io_normal:
389
+ switch (dev->error_state) {
390
+ case pci_channel_io_frozen:
391
+ case pci_channel_io_normal:
392
+ changed = true;
393
+ break;
394
+ }
395
+ break;
396
+ }
397
+ if (changed)
398
+ dev->error_state = new;
399
+ return changed;
400
+}
309401
310402 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
311403 {
312
- set_bit(PCI_DEV_DISCONNECTED, &dev->priv_flags);
404
+ device_lock(&dev->dev);
405
+ pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
406
+ device_unlock(&dev->dev);
407
+
313408 return 0;
314409 }
315410
316411 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
317412 {
318
- return test_bit(PCI_DEV_DISCONNECTED, &dev->priv_flags);
413
+ return dev->error_state == pci_channel_io_perm_failure;
319414 }
415
+
416
+/* pci_dev priv_flags */
417
+#define PCI_DEV_ADDED 0
418
+#define PCI_DPC_RECOVERED 1
419
+#define PCI_DPC_RECOVERING 2
320420
321421 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
322422 {
....@@ -356,13 +456,44 @@
356456 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
357457 #endif /* CONFIG_PCIEAER */
358458
459
+#ifdef CONFIG_PCIE_DPC
460
+void pci_save_dpc_state(struct pci_dev *dev);
461
+void pci_restore_dpc_state(struct pci_dev *dev);
462
+void pci_dpc_init(struct pci_dev *pdev);
463
+void dpc_process_error(struct pci_dev *pdev);
464
+pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
465
+bool pci_dpc_recovered(struct pci_dev *pdev);
466
+#else
467
+static inline void pci_save_dpc_state(struct pci_dev *dev) {}
468
+static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
469
+static inline void pci_dpc_init(struct pci_dev *pdev) {}
470
+static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
471
+#endif
472
+
359473 #ifdef CONFIG_PCI_ATS
474
+/* Address Translation Service */
475
+void pci_ats_init(struct pci_dev *dev);
360476 void pci_restore_ats_state(struct pci_dev *dev);
361477 #else
362
-static inline void pci_restore_ats_state(struct pci_dev *dev)
363
-{
364
-}
478
+static inline void pci_ats_init(struct pci_dev *d) { }
479
+static inline void pci_restore_ats_state(struct pci_dev *dev) { }
365480 #endif /* CONFIG_PCI_ATS */
481
+
482
+#ifdef CONFIG_PCI_PRI
483
+void pci_pri_init(struct pci_dev *dev);
484
+void pci_restore_pri_state(struct pci_dev *pdev);
485
+#else
486
+static inline void pci_pri_init(struct pci_dev *dev) { }
487
+static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
488
+#endif
489
+
490
+#ifdef CONFIG_PCI_PASID
491
+void pci_pasid_init(struct pci_dev *dev);
492
+void pci_restore_pasid_state(struct pci_dev *pdev);
493
+#else
494
+static inline void pci_pasid_init(struct pci_dev *dev) { }
495
+static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
496
+#endif
366497
367498 #ifdef CONFIG_PCI_IOV
368499 int pci_iov_init(struct pci_dev *dev);
....@@ -372,7 +503,7 @@
372503 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
373504 void pci_restore_iov_state(struct pci_dev *dev);
374505 int pci_iov_bus_range(struct pci_bus *bus);
375
-
506
+extern const struct attribute_group sriov_dev_attr_group;
376507 #else
377508 static inline int pci_iov_init(struct pci_dev *dev)
378509 {
....@@ -411,7 +542,7 @@
411542 return resource_alignment(res);
412543 }
413544
414
-void pci_enable_acs(struct pci_dev *dev);
545
+void pci_acs_init(struct pci_dev *dev);
415546 #ifdef CONFIG_PCI_QUIRKS
416547 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
417548 int pci_dev_specific_enable_acs(struct pci_dev *dev);
....@@ -433,8 +564,9 @@
433564 #endif
434565
435566 /* PCI error reporting and recovery */
436
-void pcie_do_fatal_recovery(struct pci_dev *dev, u32 service);
437
-void pcie_do_nonfatal_recovery(struct pci_dev *dev);
567
+pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
568
+ pci_channel_state_t state,
569
+ pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
438570
439571 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
440572 #ifdef CONFIG_PCIEASPM
....@@ -449,12 +581,12 @@
449581 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
450582 #endif
451583
452
-#ifdef CONFIG_PCIEASPM_DEBUG
453
-void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev);
454
-void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev);
584
+#ifdef CONFIG_PCIE_ECRC
585
+void pcie_set_ecrc_checking(struct pci_dev *dev);
586
+void pcie_ecrc_get_policy(char *str);
455587 #else
456
-static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) { }
457
-static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) { }
588
+static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
589
+static inline void pcie_ecrc_get_policy(char *str) { }
458590 #endif
459591
460592 #ifdef CONFIG_PCIE_PTM
....@@ -503,6 +635,12 @@
503635 int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
504636 int of_get_pci_domain_nr(struct device_node *node);
505637 int of_pci_get_max_link_speed(struct device_node *node);
638
+void pci_set_of_node(struct pci_dev *dev);
639
+void pci_release_of_node(struct pci_dev *dev);
640
+void pci_set_bus_of_node(struct pci_bus *bus);
641
+void pci_release_bus_of_node(struct pci_bus *bus);
642
+
643
+int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
506644
507645 #else
508646 static inline int
....@@ -522,20 +660,18 @@
522660 {
523661 return -EINVAL;
524662 }
525
-#endif /* CONFIG_OF */
526663
527
-#if defined(CONFIG_OF_ADDRESS)
528
-int devm_of_pci_get_host_bridge_resources(struct device *dev,
529
- unsigned char busno, unsigned char bus_max,
530
- struct list_head *resources, resource_size_t *io_base);
531
-#else
532
-static inline int devm_of_pci_get_host_bridge_resources(struct device *dev,
533
- unsigned char busno, unsigned char bus_max,
534
- struct list_head *resources, resource_size_t *io_base)
664
+static inline void pci_set_of_node(struct pci_dev *dev) { }
665
+static inline void pci_release_of_node(struct pci_dev *dev) { }
666
+static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
667
+static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
668
+
669
+static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
535670 {
536
- return -EINVAL;
671
+ return 0;
537672 }
538
-#endif
673
+
674
+#endif /* CONFIG_OF */
539675
540676 #ifdef CONFIG_PCIEAER
541677 void pci_no_aer(void);
....@@ -543,13 +679,28 @@
543679 void pci_aer_exit(struct pci_dev *dev);
544680 extern const struct attribute_group aer_stats_attr_group;
545681 void pci_aer_clear_fatal_status(struct pci_dev *dev);
546
-void pci_aer_clear_device_status(struct pci_dev *dev);
682
+int pci_aer_clear_status(struct pci_dev *dev);
683
+int pci_aer_raw_clear_status(struct pci_dev *dev);
547684 #else
548685 static inline void pci_no_aer(void) { }
549686 static inline void pci_aer_init(struct pci_dev *d) { }
550687 static inline void pci_aer_exit(struct pci_dev *d) { }
551688 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
552
-static inline void pci_aer_clear_device_status(struct pci_dev *dev) { }
689
+static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
690
+static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
691
+#endif
692
+
693
+#ifdef CONFIG_ACPI
694
+int pci_acpi_program_hp_params(struct pci_dev *dev);
695
+#else
696
+static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
697
+{
698
+ return -ENODEV;
699
+}
700
+#endif
701
+
702
+#ifdef CONFIG_PCIEASPM
703
+extern const struct attribute_group aspm_ctrl_attr_group;
553704 #endif
554705
555706 #endif /* DRIVERS_PCI_H */