forked from ~ljy/RK356X_SDK_RELEASE

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hc
2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f 
 kernel/drivers/pci/controller/dwc/pcie-dw-rockchip.c
....@@ -115,6 +115,10 @@
115115 #define PME_TURN_OFF			(BIT(4) | BIT(20))
116116 #define PCIE_CLIENT_GENERAL_DEBUG	0x104
117117 #define PCIE_CLIENT_HOT_RESET_CTRL	0x180
118
+#define PCIE_LTSSM_APP_DLY1_EN		BIT(0)
119
+#define PCIE_LTSSM_APP_DLY2_EN		BIT(1)
120
+#define PCIE_LTSSM_APP_DLY1_DONE	BIT(2)
121
+#define PCIE_LTSSM_APP_DLY2_DONE	BIT(3)
118122 #define PCIE_LTSSM_ENABLE_ENHANCE	BIT(4)
119123 #define PCIE_CLIENT_LTSSM_STATUS	0x300
120124 #define SMLH_LINKUP			BIT(16)
....@@ -137,6 +141,7 @@
137141 
138142 #define PCIE_PL_ORDER_RULE_CTRL_OFF	0x8B4
139143 #define RK_PCIE_L2_TMOUT_US		5000
144
+#define RK_PCIE_HOTRESET_TMOUT_US	10000
140145 
141146 enum rk_pcie_ltssm_code {
142147 	S_L0 = 0x11,
....@@ -185,6 +190,10 @@
185190 	u32				l1ss_ctl1;
186191 	struct dentry			*debugfs;
187192 	u32				msi_vector_num;
193
+	struct workqueue_struct		*hot_rst_wq;
194
+	struct work_struct		hot_rst_work;
195
+	u32				comp_prst[2];
196
+	u32				intx;
188197 };
189198 
190199 struct rk_pcie_of_data {
....@@ -1119,6 +1128,10 @@
11191128 
11201129 	dw_pcie_setup_rc(pp);
11211130 
1131
+	/* Disable BAR0 BAR1 */
1132
+	dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + BAR_0 * 4, 0);
1133
+	dw_pcie_writel_dbi(pci, PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + BAR_1 * 4, 0);
1134
+
11221135 	ret = rk_pcie_establish_link(pci);
11231136 
11241137 	if (pp->msi_irq > 0)
....@@ -1434,13 +1447,37 @@
14341447 	table->start.chnl = table->chn;
14351448 }
14361449 
1450
+static void rk_pcie_hot_rst_work(struct work_struct *work)
1451
+{
1452
+	struct rk_pcie *rk_pcie = container_of(work, struct rk_pcie, hot_rst_work);
1453
+	u32 val, status;
1454
+	int ret;
1455
+
1456
+	/* Setup command register */
1457
+	val = dw_pcie_readl_dbi(rk_pcie->pci, PCI_COMMAND);
1458
+	val &= 0xffff0000;
1459
+	val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
1460
+		PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
1461
+	dw_pcie_writel_dbi(rk_pcie->pci, PCI_COMMAND, val);
1462
+
1463
+	if (rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_HOT_RESET_CTRL) & PCIE_LTSSM_APP_DLY2_EN) {
1464
+		ret = readl_poll_timeout(rk_pcie->apb_base + PCIE_CLIENT_LTSSM_STATUS,
1465
+			 status, ((status & 0x3F) == 0), 100, RK_PCIE_HOTRESET_TMOUT_US);
1466
+		if (ret)
1467
+			dev_err(rk_pcie->pci->dev, "wait for detect quiet failed!\n");
1468
+
1469
+		rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_HOT_RESET_CTRL,
1470
+			(PCIE_LTSSM_APP_DLY2_DONE) | ((PCIE_LTSSM_APP_DLY2_DONE) << 16));
1471
+	}
1472
+}
1473
+
14371474 static irqreturn_t rk_pcie_sys_irq_handler(int irq, void *arg)
14381475 {
14391476 	struct rk_pcie *rk_pcie = arg;
14401477 	u32 chn;
14411478 	union int_status status;
14421479 	union int_clear clears;
1443
-	u32 reg, val;
1480
+	u32 reg;
14441481 
14451482 	status.asdword = dw_pcie_readl_dbi(rk_pcie->pci, PCIE_DMA_OFFSET +
14461483 					   PCIE_DMA_WR_INT_STATUS);
....@@ -1481,14 +1518,8 @@
14811518 	}
14821519 
14831520 	reg = rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_INTR_STATUS_MISC);
1484
-	if (reg & BIT(2)) {
1485
-		/* Setup command register */
1486
-		val = dw_pcie_readl_dbi(rk_pcie->pci, PCI_COMMAND);
1487
-		val &= 0xffff0000;
1488
-		val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
1489
-		       PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
1490
-		dw_pcie_writel_dbi(rk_pcie->pci, PCI_COMMAND, val);
1491
-	}
1521
+	if (reg & BIT(2))
1522
+		queue_work(rk_pcie->hot_rst_wq, &rk_pcie->hot_rst_work);
14921523 
14931524 	rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_INTR_STATUS_MISC, reg);
14941525 
....@@ -1612,7 +1643,8 @@
16121643 
16131644 	/* LTSSM EN ctrl mode */
16141645 	val = rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_HOT_RESET_CTRL);
1615
-	val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16);
1646
+	val |= (PCIE_LTSSM_ENABLE_ENHANCE | PCIE_LTSSM_APP_DLY2_EN)
1647
+		| ((PCIE_LTSSM_APP_DLY2_EN | PCIE_LTSSM_ENABLE_ENHANCE) << 16);
16161648 	rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_HOT_RESET_CTRL, val);
16171649 }
16181650 
....@@ -1650,7 +1682,7 @@
16501682 static int rk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
16511683 			    irq_hw_number_t hwirq)
16521684 {
1653
-	irq_set_chip_and_handler(irq, &rk_pcie_legacy_irq_chip, handle_simple_irq);
1685
+	irq_set_chip_and_handler(irq, &rk_pcie_legacy_irq_chip, handle_level_irq);
16541686 	irq_set_chip_data(irq, domain->host_data);
16551687 
16561688 	return 0;
....@@ -2051,17 +2083,39 @@
20512083 		rk_pcie->is_signal_test = true;
20522084 	}
20532085 
2054
-	/* Force into compliance mode */
2055
-	if (device_property_read_bool(dev, "rockchip,compliance-mode")) {
2056
-		val = dw_pcie_readl_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS);
2057
-		val |= BIT(4);
2058
-		dw_pcie_writel_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS, val);
2086
+	/*
2087
+	 * Force into compliance mode
2088
+	 * comp_prst is a two dimensional array of which the first element
2089
+	 * stands for speed mode, and the second one is preset value encoding:
2090
+	 * [0] 0->SMA tool control the signal switch, 1/2/3 is for manual Gen setting
2091
+	 * [1] transmitter setting for manual Gen setting, valid only if [0] isn't zero.
2092
+	 */
2093
+	if (!device_property_read_u32_array(dev, "rockchip,compliance-mode",
2094
+					    rk_pcie->comp_prst, 2)) {
2095
+		BUG_ON(rk_pcie->comp_prst[0] > 3 || rk_pcie->comp_prst[1] > 10);
2096
+		if (!rk_pcie->comp_prst[0]) {
2097
+			dev_info(dev, "Auto compliance mode for SMA tool.\n");
2098
+		} else {
2099
+			dev_info(dev, "compliance mode for soldered board Gen%d, P%d.\n",
2100
+				 rk_pcie->comp_prst[0], rk_pcie->comp_prst[1]);
2101
+			val = dw_pcie_readl_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS);
2102
+			val |= BIT(4) | rk_pcie->comp_prst[0] | (rk_pcie->comp_prst[1] << 12);
2103
+			dw_pcie_writel_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS, val);
2104
+		}
20592105 		rk_pcie->is_signal_test = true;
20602106 	}
20612107 
20622108 	/* Skip waiting for training to pass in system PM routine */
20632109 	if (device_property_read_bool(dev, "rockchip,skip-scan-in-resume"))
20642110 		rk_pcie->skip_scan_in_resume = true;
2111
+
2112
+	rk_pcie->hot_rst_wq = create_singlethread_workqueue("rk_pcie_hot_rst_wq");
2113
+	if (!rk_pcie->hot_rst_wq) {
2114
+		dev_err(dev, "failed to create hot_rst workqueue\n");
2115
+		ret = -ENOMEM;
2116
+		goto remove_irq_domain;
2117
+	}
2118
+	INIT_WORK(&rk_pcie->hot_rst_work, rk_pcie_hot_rst_work);
20652119 
20662120 	switch (rk_pcie->mode) {
20672121 	case RK_PCIE_RC_TYPE:
....@@ -2076,12 +2130,12 @@
20762130 		return 0;
20772131 
20782132 	if (ret)
2079
-		goto remove_irq_domain;
2133
+		goto remove_rst_wq;
20802134 
20812135 	ret = rk_pcie_init_dma_trx(rk_pcie);
20822136 	if (ret) {
20832137 		dev_err(dev, "failed to add dma extension\n");
2084
-		goto remove_irq_domain;
2138
+		goto remove_rst_wq;
20852139 	}
20862140 
20872141 	if (rk_pcie->dma_obj) {
....@@ -2093,7 +2147,7 @@
20932147 		/* hold link reset grant after link-up */
20942148 		ret = rk_pcie_reset_grant_ctrl(rk_pcie, false);
20952149 		if (ret)
2096
-			goto remove_irq_domain;
2150
+			goto remove_rst_wq;
20972151 	}
20982152 
20992153 	dw_pcie_dbi_ro_wr_dis(pci);
....@@ -2121,6 +2175,8 @@
21212175 
21222176 	return 0;
21232177 
2178
+remove_rst_wq:
2179
+	destroy_workqueue(rk_pcie->hot_rst_wq);
21242180 remove_irq_domain:
21252181 	if (rk_pcie->irq_domain)
21262182 		irq_domain_remove(rk_pcie->irq_domain);
....@@ -2304,6 +2360,8 @@
23042360 	phy_power_off(rk_pcie->phy);
23052361 	phy_exit(rk_pcie->phy);
23062362 
2363
+	rk_pcie->intx = rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_INTR_MASK_LEGACY);
2364
+
23072365 	clk_bulk_disable_unprepare(rk_pcie->clk_cnt, rk_pcie->clks);
23082366 
23092367 	rk_pcie->in_suspend = true;
....@@ -2368,6 +2426,9 @@
23682426 	if (std_rc)
23692427 		dw_pcie_setup_rc(&rk_pcie->pci->pp);
23702428 
2429
+	rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_INTR_MASK_LEGACY,
2430
+			   rk_pcie->intx | 0xffff0000);
2431
+
23712432 	ret = rk_pcie_establish_link(rk_pcie->pci);
23722433 	if (ret) {
23732434 		dev_err(dev, "failed to establish pcie link\n");