forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f 
 kernel/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c
....@@ -1,27 +1,5 @@
1
-/******************************************************************************
2
- *
3
- * Copyright(c) 2009-2010  Realtek Corporation.
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms of version 2 of the GNU General Public License as
7
- * published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope that it will be useful, but WITHOUT
10
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12
- * more details.
13
- *
14
- * The full GNU General Public License is included in this distribution in the
15
- * file called LICENSE.
16
- *
17
- * Contact Information:
18
- * wlanfae <wlanfae@realtek.com>
19
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20
- * Hsinchu 300, Taiwan.
21
- *
22
- * Larry Finger <Larry.Finger@lwfinger.net>
23
- *
24
- *****************************************************************************/
1
+// SPDX-License-Identifier: GPL-2.0
2
+/* Copyright(c) 2009-2010  Realtek Corporation.*/
253 
264 #include "../wifi.h"
275 #include "../efuse.h"
....@@ -55,11 +33,10 @@
5533 		struct rtl_tx_desc *entry = &ring->desc[ring->idx];
5634 		struct sk_buff *skb = __skb_dequeue(&ring->queue);
5735 
58
-		pci_unmap_single(rtlpci->pdev,
59
-				 rtlpriv->cfg->ops->get_desc(
60
-				 hw,
61
-				 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
62
-				 skb->len, PCI_DMA_TODEVICE);
36
+		dma_unmap_single(&rtlpci->pdev->dev,
37
+				 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
38
+						true, HW_DESC_TXBUFF_ADDR),
39
+				 skb->len, DMA_TO_DEVICE);
6340 		kfree_skb(skb);
6441 		ring->idx = (ring->idx + 1) % ring->entries;
6542 	}
....@@ -165,9 +142,9 @@
165142 			if (content & IMR_CPWM) {
166143 				rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
167144 				rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8821AE;
168
-				RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
169
-					 "Receive CPWM INT!!! Set rtlhal->FwPSState = %X\n",
170
-					 rtlhal->fw_ps_state);
145
+				rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
146
+					"Receive CPWM INT!!! Set rtlhal->FwPSState = %X\n",
147
+					rtlhal->fw_ps_state);
171148 			}
172149 		}
173150 
....@@ -352,8 +329,8 @@
352329 	} while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
353330 
354331 	if (!(bcnvalid_reg & BIT(0)))
355
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
356
-			 "Download RSVD page failed!\n");
332
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
333
+			"Download RSVD page failed!\n");
357334 	if (bcnvalid_reg & BIT(0) && rtlhal->enter_pnp_sleep) {
358335 		rtl_write_byte(rtlpriv, REG_TDECTRL + 2, bcnvalid_reg | BIT(0));
359336 		_rtl8821ae_return_beacon_queue_skb(hw);
....@@ -387,8 +364,8 @@
387364 			} while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
388365 
389366 			if (!(bcnvalid_reg & BIT(0)))
390
-				RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
391
-					 "2 Download RSVD page failed!\n");
367
+				rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
368
+					"2 Download RSVD page failed!\n");
392369 		}
393370 	}
394371 
....@@ -480,8 +457,8 @@
480457 			*((bool *)(val)) = false;
481458 		break;
482459 	default:
483
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
484
-			 "switch case %#x not processed\n", variable);
460
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
461
+			"switch case %#x not processed\n", variable);
485462 		break;
486463 	}
487464 }
....@@ -533,8 +510,8 @@
533510 	case HW_VAR_SLOT_TIME:{
534511 		u8 e_aci;
535512 
536
-		RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
537
-			 "HW_VAR_SLOT_TIME %x\n", val[0]);
513
+		rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
514
+			"HW_VAR_SLOT_TIME %x\n", val[0]);
538515 
539516 		rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
540517 
....@@ -580,9 +557,9 @@
580557 
581558 			*val = min_spacing_to_set;
582559 
583
-			RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
584
-				 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
585
-				  mac->min_space_cfg);
560
+			rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
561
+				"Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
562
+				mac->min_space_cfg);
586563 
587564 			rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
588565 				       mac->min_space_cfg);
....@@ -594,9 +571,9 @@
594571 		density_to_set = *((u8 *)val);
595572 		mac->min_space_cfg |= (density_to_set << 3);
596573 
597
-		RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
598
-			 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
599
-			  mac->min_space_cfg);
574
+		rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
575
+			"Set HW_VAR_SHORTGI_DENSITY: %#x\n",
576
+			mac->min_space_cfg);
600577 
601578 		rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
602579 			       mac->min_space_cfg);
....@@ -654,9 +631,9 @@
654631 				acm_ctrl |= ACMHW_VOQEN;
655632 				break;
656633 			default:
657
-				RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
658
-					 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
659
-					 acm);
634
+				rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
635
+					"HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
636
+					acm);
660637 				break;
661638 			}
662639 		} else {
....@@ -671,16 +648,16 @@
671648 				acm_ctrl &= (~ACMHW_VOQEN);
672649 				break;
673650 			default:
674
-				RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
675
-					 "switch case %#x not processed\n",
676
-					 e_aci);
651
+				rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
652
+					"switch case %#x not processed\n",
653
+					e_aci);
677654 				break;
678655 			}
679656 		}
680657 
681
-		RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
682
-			 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
683
-			 acm_ctrl);
658
+		rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE,
659
+			"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
660
+			acm_ctrl);
684661 		rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
685662 		break; }
686663 	case HW_VAR_RCR:
....@@ -783,9 +760,9 @@
783760 		u32	us_nav_upper = *(u32 *)val;
784761 
785762 		if (us_nav_upper > HAL_92C_NAV_UPPER_UNIT * 0xFF) {
786
-			RT_TRACE(rtlpriv, COMP_INIT , DBG_WARNING,
787
-				 "The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n",
788
-				 us_nav_upper, HAL_92C_NAV_UPPER_UNIT);
763
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING,
764
+				"The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n",
765
+				us_nav_upper, HAL_92C_NAV_UPPER_UNIT);
789766 			break;
790767 		}
791768 		rtl_write_byte(rtlpriv, REG_NAV_UPPER,
....@@ -801,8 +778,8 @@
801778 				       array);
802779 		break; }
803780 	default:
804
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
805
-			 "switch case %#x not processed\n", variable);
781
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
782
+			"switch case %#x not processed\n", variable);
806783 		break;
807784 	}
808785 }
....@@ -932,16 +909,16 @@
932909 		if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
933910 					      PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
934911 					      RTL8812_NIC_ENABLE_FLOW)) {
935
-				RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
936
-					 "init 8812 MAC Fail as power on failure\n");
937
-				return false;
912
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
913
+				"init 8812 MAC Fail as power on failure\n");
914
+			return false;
938915 		}
939916 	} else {
940917 		/* HW Power on sequence */
941918 		if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_A_MSK,
942919 					      PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
943920 					      RTL8821A_NIC_ENABLE_FLOW)){
944
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
921
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
945922 				"init 8821 MAC Fail as power on failure\n");
946923 			return false;
947924 		}
....@@ -1183,14 +1160,14 @@
11831160 	u8 sec_reg_value;
11841161 	u8 tmp;
11851162 
1186
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1187
-		 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1188
-		  rtlpriv->sec.pairwise_enc_algorithm,
1189
-		  rtlpriv->sec.group_enc_algorithm);
1163
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1164
+		"PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1165
+		rtlpriv->sec.pairwise_enc_algorithm,
1166
+		rtlpriv->sec.group_enc_algorithm);
11901167 
11911168 	if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1192
-		RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1193
-			 "not open hw encryption\n");
1169
+		rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
1170
+			"not open hw encryption\n");
11941171 		return;
11951172 	}
11961173 
....@@ -1206,8 +1183,8 @@
12061183 	tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
12071184 	rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
12081185 
1209
-	RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1210
-		 "The SECR-value %x\n", sec_reg_value);
1186
+	rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
1187
+		"The SECR-value %x\n", sec_reg_value);
12111188 
12121189 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
12131190 }
....@@ -1229,10 +1206,10 @@
12291206 	rtlpriv->cfg->ops->set_hw_reg(hw,
12301207 		HW_VAR_H2C_FW_MEDIASTATUSRPT, media_rpt);
12311208 
1232
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1233
-		 "Initialize MacId media status: from %d to %d\n",
1234
-		 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1235
-		 MAC_ID_STATIC_FOR_BT_CLIENT_END);
1209
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1210
+		"Initialize MacId media status: from %d to %d\n",
1211
+		MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1212
+		MAC_ID_STATIC_FOR_BT_CLIENT_END);
12361213 }
12371214 
12381215 static bool _rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw *hw)
....@@ -1251,8 +1228,8 @@
12511228 	/* read reg 0x350 Bit[24] if 1 : TX hang */
12521229 	tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
12531230 	if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1254
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1255
-			 "CheckPcieDMAHang8821AE(): true! Reset PCIE DMA!\n");
1231
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1232
+			"CheckPcieDMAHang8821AE(): true! Reset PCIE DMA!\n");
12561233 		return true;
12571234 	} else {
12581235 		return false;
....@@ -1269,7 +1246,7 @@
12691246 	bool release_mac_rx_pause;
12701247 	u8 backup_pcie_dma_pause;
12711248 
1272
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1249
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
12731250 
12741251 	/* 1. Disable register write lock. 0x1c[1] = 0 */
12751252 	tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
....@@ -1368,8 +1345,8 @@
13681345 
13691346 	fw_reason = rtl_read_byte(rtlpriv, REG_MCUTST_WOWLAN);
13701347 
1371
-	RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "WOL Read 0x1c7 = %02X\n",
1372
-		 fw_reason);
1348
+	rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "WOL Read 0x1c7 = %02X\n",
1349
+		fw_reason);
13731350 
13741351 	ppsc->wakeup_reason = 0;
13751352 
....@@ -1378,63 +1355,63 @@
13781355 	switch (fw_reason) {
13791356 	case FW_WOW_V2_PTK_UPDATE_EVENT:
13801357 		ppsc->wakeup_reason = WOL_REASON_PTK_UPDATE;
1381
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1382
-			 "It's a WOL PTK Key update event!\n");
1358
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1359
+			"It's a WOL PTK Key update event!\n");
13831360 		break;
13841361 	case FW_WOW_V2_GTK_UPDATE_EVENT:
13851362 		ppsc->wakeup_reason = WOL_REASON_GTK_UPDATE;
1386
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1387
-			 "It's a WOL GTK Key update event!\n");
1363
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1364
+			"It's a WOL GTK Key update event!\n");
13881365 		break;
13891366 	case FW_WOW_V2_DISASSOC_EVENT:
13901367 		ppsc->wakeup_reason = WOL_REASON_DISASSOC;
1391
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1392
-			 "It's a disassociation event!\n");
1368
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1369
+			"It's a disassociation event!\n");
13931370 		break;
13941371 	case FW_WOW_V2_DEAUTH_EVENT:
13951372 		ppsc->wakeup_reason = WOL_REASON_DEAUTH;
1396
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1397
-			 "It's a deauth event!\n");
1373
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1374
+			"It's a deauth event!\n");
13981375 		break;
13991376 	case FW_WOW_V2_FW_DISCONNECT_EVENT:
14001377 		ppsc->wakeup_reason = WOL_REASON_AP_LOST;
1401
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1402
-			 "It's a Fw disconnect decision (AP lost) event!\n");
1378
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1379
+			"It's a Fw disconnect decision (AP lost) event!\n");
14031380 	break;
14041381 	case FW_WOW_V2_MAGIC_PKT_EVENT:
14051382 		ppsc->wakeup_reason = WOL_REASON_MAGIC_PKT;
1406
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1407
-			 "It's a magic packet event!\n");
1383
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1384
+			"It's a magic packet event!\n");
14081385 		break;
14091386 	case FW_WOW_V2_UNICAST_PKT_EVENT:
14101387 		ppsc->wakeup_reason = WOL_REASON_UNICAST_PKT;
1411
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1412
-			 "It's an unicast packet event!\n");
1388
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1389
+			"It's an unicast packet event!\n");
14131390 		break;
14141391 	case FW_WOW_V2_PATTERN_PKT_EVENT:
14151392 		ppsc->wakeup_reason = WOL_REASON_PATTERN_PKT;
1416
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1417
-			 "It's a pattern match event!\n");
1393
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1394
+			"It's a pattern match event!\n");
14181395 		break;
14191396 	case FW_WOW_V2_RTD3_SSID_MATCH_EVENT:
14201397 		ppsc->wakeup_reason = WOL_REASON_RTD3_SSID_MATCH;
1421
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1422
-			 "It's an RTD3 Ssid match event!\n");
1398
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1399
+			"It's an RTD3 Ssid match event!\n");
14231400 		break;
14241401 	case FW_WOW_V2_REALWOW_V2_WAKEUPPKT:
14251402 		ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_WAKEUPPKT;
1426
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1427
-			 "It's an RealWoW wake packet event!\n");
1403
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1404
+			"It's an RealWoW wake packet event!\n");
14281405 		break;
14291406 	case FW_WOW_V2_REALWOW_V2_ACKLOST:
14301407 		ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_ACKLOST;
1431
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1432
-			 "It's an RealWoW ack lost event!\n");
1408
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1409
+			"It's an RealWoW ack lost event!\n");
14331410 		break;
14341411 	default:
1435
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1436
-			 "WOL Read 0x1c7 = %02X, Unknown reason!\n",
1437
-			  fw_reason);
1412
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
1413
+			"WOL Read 0x1c7 = %02X, Unknown reason!\n",
1414
+			fw_reason);
14381415 		break;
14391416 	}
14401417 }
....@@ -1506,9 +1483,9 @@
15061483 	rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
15071484 				      (u8 *)(&support_remote_wakeup));
15081485 
1509
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1510
-		 "boundary=%#X, NPQ_RQPNValue=%#X, RQPNValue=%#X\n",
1511
-		  boundary, npq_rqpn_value, rqpn_val);
1486
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1487
+		"boundary=%#X, NPQ_RQPNValue=%#X, RQPNValue=%#X\n",
1488
+		boundary, npq_rqpn_value, rqpn_val);
15121489 
15131490 	/* stop PCIe DMA
15141491 	 * 1. 0x301[7:0] = 0xFE */
....@@ -1522,12 +1499,12 @@
15221499 		tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
15231500 		count++;
15241501 		if ((count % 200) == 0) {
1525
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1526
-				 "Tx queue is not empty for 20ms!\n");
1502
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1503
+				"Tx queue is not empty for 20ms!\n");
15271504 		}
15281505 		if (count >= 1000) {
1529
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1530
-				 "Wait for Tx FIFO empty timeout!\n");
1506
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1507
+				"Wait for Tx FIFO empty timeout!\n");
15311508 			break;
15321509 		}
15331510 	}
....@@ -1543,8 +1520,8 @@
15431520 		udelay(100);
15441521 		count++;
15451522 		if (count >= 500) {
1546
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1547
-				 "Wait for TX State Machine ready timeout !!\n");
1523
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1524
+				"Wait for TX State Machine ready timeout !!\n");
15481525 			break;
15491526 		}
15501527 	}
....@@ -1562,9 +1539,9 @@
15621539 		count++;
15631540 	} while (!(tmp & BIT(1)) && count < 100);
15641541 
1565
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1566
-		 "Wait until Rx DMA Idle. count=%d REG[0x286]=0x%x\n",
1567
-		  count, tmp);
1542
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1543
+		"Wait until Rx DMA Idle. count=%d REG[0x286]=0x%x\n",
1544
+		count, tmp);
15681545 
15691546 	/* reset BB
15701547 	 * 7.	0x02 [0] = 0 */
....@@ -1621,8 +1598,8 @@
16211598 	/* init LLT
16221599 	 * 17. init LLT */
16231600 	if (!_rtl8821ae_init_llt_table(hw, boundary)) {
1624
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
1625
-			 "Failed to init LLT table!\n");
1601
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING,
1602
+			"Failed to init LLT table!\n");
16261603 		return false;
16271604 	}
16281605 
....@@ -1642,7 +1619,7 @@
16421619 	tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
16431620 	rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp&~BIT(2)));
16441621 
1645
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "End.\n");
1622
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "End.\n");
16461623 	return ret;
16471624 }
16481625 
....@@ -1677,12 +1654,12 @@
16771654 	u8 tmp  = 0;
16781655 	struct rtl_priv *rtlpriv = rtl_priv(hw);
16791656 
1680
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1657
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
16811658 
16821659 	tmp = _rtl8821ae_dbi_read(rtlpriv, 0x160);
16831660 	if (!(tmp & (BIT(2) | BIT(3)))) {
1684
-		RT_TRACE(rtlpriv, COMP_POWER | COMP_INIT, DBG_LOUD,
1685
-			 "0x160(%#x)return!!\n", tmp);
1661
+		rtl_dbg(rtlpriv, COMP_POWER | COMP_INIT, DBG_LOUD,
1662
+			"0x160(%#x)return!!\n", tmp);
16861663 		return;
16871664 	}
16881665 
....@@ -1692,7 +1669,7 @@
16921669 	tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718);
16931670 	_rtl8821ae_dbi_write(rtlpriv, 0x718, tmp | BIT(5));
16941671 
1695
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1672
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
16961673 }
16971674 
16981675 static void _rtl8821ae_enable_ltr(struct ieee80211_hw *hw)
....@@ -1700,13 +1677,13 @@
17001677 	u8 tmp  = 0;
17011678 	struct rtl_priv *rtlpriv = rtl_priv(hw);
17021679 
1703
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1680
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
17041681 
17051682 	/* Check 0x98[10] */
17061683 	tmp = _rtl8821ae_dbi_read(rtlpriv, 0x99);
17071684 	if (!(tmp & BIT(2))) {
1708
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1709
-			 "<---0x99(%#x) return!!\n", tmp);
1685
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1686
+			"<---0x99(%#x) return!!\n", tmp);
17101687 		return;
17111688 	}
17121689 
....@@ -1723,7 +1700,7 @@
17231700 	rtl_write_byte(rtlpriv, 0x7a4, (tmp & (~BIT(0))));
17241701 	rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(0)));
17251702 
1726
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1703
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
17271704 }
17281705 
17291706 static bool _rtl8821ae_wowlan_initialize_adapter(struct ieee80211_hw *hw)
....@@ -1746,14 +1723,14 @@
17461723 
17471724 	/* Release Pcie Interface Rx DMA to allow wake packet DMA. */
17481725 	rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1749
-	RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Enable PCIE Rx DMA.\n");
1726
+	rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Enable PCIE Rx DMA.\n");
17501727 
17511728 	/* Check wake up event.
17521729 	 * We should check wake packet bit before disable wowlan by H2C or
17531730 	 * Fw will clear the bit. */
17541731 	tmp = rtl_read_byte(rtlpriv, REG_FTISR + 3);
1755
-	RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1756
-		 "Read REG_FTISR 0x13f = %#X\n", tmp);
1732
+	rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
1733
+		"Read REG_FTISR 0x13f = %#X\n", tmp);
17571734 
17581735 	/* Set the WoWLAN related function control disable. */
17591736 	rtl8821ae_set_fw_wowlan_mode(hw, false);
....@@ -1818,7 +1795,7 @@
18181795 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
18191796 		/* Combo (PCIe + USB) Card and PCIe-MF Card */
18201797 		/* 1. Run LPS WL RFOFF flow */
1821
-		/* RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1798
+		/* rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
18221799 		"=====>CardDisableRTL8812E,RTL8821A_NIC_LPS_ENTER_FLOW\n");
18231800 		*/
18241801 		rtl_hal_pwrseqcmdparsing(rtlpriv,
....@@ -1884,8 +1861,8 @@
18841861 	tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
18851862 	if (tmp_u1b != 0 && tmp_u1b != 0xEA) {
18861863 		rtlhal->mac_func_enable = true;
1887
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1888
-			 "MAC has already power on.\n");
1864
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1865
+			"MAC has already power on.\n");
18891866 	} else {
18901867 		rtlhal->mac_func_enable = false;
18911868 		rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
....@@ -1917,7 +1894,7 @@
19171894 	}
19181895 
19191896 	rtstatus = _rtl8821ae_init_mac(hw);
1920
-	if (rtstatus != true) {
1897
+	if (!rtstatus) {
19211898 		pr_err("Init MAC failed\n");
19221899 		err = 1;
19231900 		return err;
....@@ -1929,8 +1906,8 @@
19291906 
19301907 	err = rtl8821ae_download_fw(hw, false);
19311908 	if (err) {
1932
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1933
-			 "Failed to download FW. Init HW without FW now\n");
1909
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1910
+			"Failed to download FW. Init HW without FW now\n");
19341911 		err = 1;
19351912 		rtlhal->fw_ready = false;
19361913 		return err;
....@@ -2009,7 +1986,7 @@
20091986 	rtl8821ae_dm_init(hw);
20101987 	rtl8821ae_macid_initialize_mediastatus(hw);
20111988 
2012
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_hw_init() <====\n");
1989
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "%s() <====\n", __func__);
20131990 	return err;
20141991 }
20151992 
....@@ -2022,16 +1999,16 @@
20221999 	u32 value32;
20232000 
20242001 	value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
2025
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2026
-		 "ReadChipVersion8812A 0xF0 = 0x%x\n", value32);
2002
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2003
+		"ReadChipVersion8812A 0xF0 = 0x%x\n", value32);
20272004 
20282005 	if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
20292006 		rtlphy->rf_type = RF_2T2R;
20302007 	else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
20312008 		rtlphy->rf_type = RF_1T1R;
20322009 
2033
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2034
-		 "RF_Type is %x!!\n", rtlphy->rf_type);
2010
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2011
+		"RF_Type is %x!!\n", rtlphy->rf_type);
20352012 
20362013 	if (value32 & TRP_VAUX_EN) {
20372014 		if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
....@@ -2071,44 +2048,44 @@
20712048 
20722049 	switch (version) {
20732050 	case VERSION_TEST_CHIP_1T1R_8812:
2074
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2075
-			 "Chip Version ID: VERSION_TEST_CHIP_1T1R_8812\n");
2051
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2052
+			"Chip Version ID: VERSION_TEST_CHIP_1T1R_8812\n");
20762053 		break;
20772054 	case VERSION_TEST_CHIP_2T2R_8812:
2078
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2079
-			 "Chip Version ID: VERSION_TEST_CHIP_2T2R_8812\n");
2055
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2056
+			"Chip Version ID: VERSION_TEST_CHIP_2T2R_8812\n");
20802057 		break;
20812058 	case VERSION_NORMAL_TSMC_CHIP_1T1R_8812:
2082
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2083
-			 "Chip Version ID:VERSION_NORMAL_TSMC_CHIP_1T1R_8812\n");
2059
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2060
+			"Chip Version ID:VERSION_NORMAL_TSMC_CHIP_1T1R_8812\n");
20842061 		break;
20852062 	case VERSION_NORMAL_TSMC_CHIP_2T2R_8812:
2086
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2087
-			 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812\n");
2063
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2064
+			"Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812\n");
20882065 		break;
20892066 	case VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT:
2090
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2091
-			 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT\n");
2067
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2068
+			"Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT\n");
20922069 		break;
20932070 	case VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT:
2094
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2095
-			 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT\n");
2071
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2072
+			"Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT\n");
20962073 		break;
20972074 	case VERSION_TEST_CHIP_8821:
2098
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2099
-			 "Chip Version ID: VERSION_TEST_CHIP_8821\n");
2075
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2076
+			"Chip Version ID: VERSION_TEST_CHIP_8821\n");
21002077 		break;
21012078 	case VERSION_NORMAL_TSMC_CHIP_8821:
2102
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2103
-			 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT\n");
2079
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2080
+			"Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT\n");
21042081 		break;
21052082 	case VERSION_NORMAL_TSMC_CHIP_8821_B_CUT:
2106
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2107
-			 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT\n");
2083
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2084
+			"Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT\n");
21082085 		break;
21092086 	default:
2110
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2111
-			 "Chip Version ID: Unknown (0x%X)\n", version);
2087
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2088
+			"Chip Version ID: Unknown (0x%X)\n", version);
21122089 		break;
21132090 	}
21142091 
....@@ -2124,7 +2101,7 @@
21242101 	bt_msr &= 0xfc;
21252102 
21262103 	rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
2127
-	RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD,
2104
+	rtl_dbg(rtlpriv, COMP_BEACON, DBG_LOUD,
21282105 		"clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
21292106 
21302107 	if (type == NL80211_IFTYPE_UNSPECIFIED ||
....@@ -2136,33 +2113,33 @@
21362113 		_rtl8821ae_resume_tx_beacon(hw);
21372114 		_rtl8821ae_disable_bcn_sub_func(hw);
21382115 	} else {
2139
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2140
-			 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
2141
-			 type);
2116
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
2117
+			"Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
2118
+			type);
21422119 	}
21432120 
21442121 	switch (type) {
21452122 	case NL80211_IFTYPE_UNSPECIFIED:
21462123 		bt_msr |= MSR_NOLINK;
21472124 		ledaction = LED_CTL_LINK;
2148
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2149
-			 "Set Network type to NO LINK!\n");
2125
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2126
+			"Set Network type to NO LINK!\n");
21502127 		break;
21512128 	case NL80211_IFTYPE_ADHOC:
21522129 		bt_msr |= MSR_ADHOC;
2153
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2154
-			 "Set Network type to Ad Hoc!\n");
2130
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2131
+			"Set Network type to Ad Hoc!\n");
21552132 		break;
21562133 	case NL80211_IFTYPE_STATION:
21572134 		bt_msr |= MSR_INFRA;
21582135 		ledaction = LED_CTL_LINK;
2159
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2160
-			 "Set Network type to STA!\n");
2136
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2137
+			"Set Network type to STA!\n");
21612138 		break;
21622139 	case NL80211_IFTYPE_AP:
21632140 		bt_msr |= MSR_AP;
2164
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2165
-			 "Set Network type to AP!\n");
2141
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
2142
+			"Set Network type to AP!\n");
21662143 		break;
21672144 	default:
21682145 		pr_err("Network type %d not support!\n", type);
....@@ -2205,7 +2182,7 @@
22052182 {
22062183 	struct rtl_priv *rtlpriv = rtl_priv(hw);
22072184 
2208
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_set_network_type!\n");
2185
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "%s!\n", __func__);
22092186 
22102187 	if (_rtl8821ae_set_media_status(hw, type))
22112188 		return -EOPNOTSUPP;
....@@ -2305,16 +2282,16 @@
23052282 	 * offset 0x34 from the Function Header */
23062283 
23072284 	pci_read_config_byte(rtlpci->pdev, 0x34, &cap_pointer);
2308
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2309
-		 "PCI configuration 0x34 = 0x%2x\n", cap_pointer);
2285
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2286
+		"PCI configuration 0x34 = 0x%2x\n", cap_pointer);
23102287 
23112288 	do {
23122289 		pci_read_config_word(rtlpci->pdev, cap_pointer, &cap_hdr);
23132290 		cap_id = cap_hdr & 0xFF;
23142291 
2315
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2316
-			 "in pci configuration, cap_pointer%x = %x\n",
2317
-			  cap_pointer, cap_id);
2292
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2293
+			"in pci configuration, cap_pointer%x = %x\n",
2294
+			cap_pointer, cap_id);
23182295 
23192296 		if (cap_id == 0x01) {
23202297 			break;
....@@ -2344,17 +2321,17 @@
23442321 			/* Read it back to check */
23452322 			pci_read_config_byte(rtlpci->pdev, cap_pointer + 5,
23462323 					     &pmcs_reg);
2347
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2348
-				 "Clear PME status 0x%2x to 0x%2x\n",
2349
-				  cap_pointer + 5, pmcs_reg);
2324
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2325
+				"Clear PME status 0x%2x to 0x%2x\n",
2326
+				cap_pointer + 5, pmcs_reg);
23502327 		} else {
2351
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2352
-				 "PME status(0x%2x) = 0x%2x\n",
2353
-				  cap_pointer + 5, pmcs_reg);
2328
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2329
+				"PME status(0x%2x) = 0x%2x\n",
2330
+				cap_pointer + 5, pmcs_reg);
23542331 		}
23552332 	} else {
2356
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
2357
-			 "Cannot find PME Capability\n");
2333
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_WARNING,
2334
+			"Cannot find PME Capability\n");
23582335 	}
23592336 }
23602337 
....@@ -2376,13 +2353,13 @@
23762353 
23772354 	if (!(support_remote_wakeup && mac->opmode == NL80211_IFTYPE_STATION)
23782355 	    || !rtlhal->enter_pnp_sleep) {
2379
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Normal Power off\n");
2356
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Normal Power off\n");
23802357 		mac->link_state = MAC80211_NOLINK;
23812358 		opmode = NL80211_IFTYPE_UNSPECIFIED;
23822359 		_rtl8821ae_set_media_status(hw, opmode);
23832360 		_rtl8821ae_poweroff_adapter(hw);
23842361 	} else {
2385
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Wowlan Supported.\n");
2362
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Wowlan Supported.\n");
23862363 		/* 3 <1> Prepare for configuring wowlan related infomations */
23872364 		/* Clear Fw WoWLAN event. */
23882365 		rtl_write_byte(rtlpriv, REG_MCUTST_WOWLAN, 0x0);
....@@ -2432,9 +2409,9 @@
24322409 			udelay(10);
24332410 			tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
24342411 		}
2435
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2436
-			 "Wait Rx DMA Finished before host sleep. count=%d\n",
2437
-			  count);
2412
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2413
+			"Wait Rx DMA Finished before host sleep. count=%d\n",
2414
+			count);
24382415 
24392416 		/* reset trx ring */
24402417 		rtlpriv->intf_ops->reset_trx_ring(hw);
....@@ -2460,7 +2437,7 @@
24602437 
24612438 		/* Stop Pcie Interface Tx DMA. */
24622439 		rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
2463
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Stop PCIE Tx DMA.\n");
2440
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Stop PCIE Tx DMA.\n");
24642441 
24652442 		/* Wait for TxDMA idle. */
24662443 		count = 0;
....@@ -2469,9 +2446,9 @@
24692446 			udelay(10);
24702447 			count++;
24712448 		} while ((tmp != 0) && (count < 100));
2472
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2473
-			 "Wait Tx DMA Finished before host sleep. count=%d\n",
2474
-			  count);
2449
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2450
+			"Wait Tx DMA Finished before host sleep. count=%d\n",
2451
+			count);
24752452 
24762453 		if (rtlhal->hw_rof_enable) {
24772454 			printk("hw_rof_enable\n");
....@@ -2523,8 +2500,8 @@
25232500 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
25242501 	u16 bcn_interval = mac->beacon_interval;
25252502 
2526
-	RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
2527
-		 "beacon_interval:%d\n", bcn_interval);
2503
+	rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG,
2504
+		"beacon_interval:%d\n", bcn_interval);
25282505 	rtl8821ae_disable_interrupt(hw);
25292506 	rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
25302507 	rtl8821ae_enable_interrupt(hw);
....@@ -2536,8 +2513,8 @@
25362513 	struct rtl_priv *rtlpriv = rtl_priv(hw);
25372514 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
25382515 
2539
-	RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
2540
-		 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
2516
+	rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD,
2517
+		"add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
25412518 
25422519 	if (add_msr)
25432520 		rtlpci->irq_mask[0] |= add_msr;
....@@ -2606,50 +2583,50 @@
26062583 	u8 *hwinfo)
26072584 {
26082585 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2609
-	u32 rfPath, eeAddr = EEPROM_TX_PWR_INX, group, TxCount = 0;
2586
+	u32 rfpath, eeaddr = EEPROM_TX_PWR_INX, group, txcount = 0;
26102587 
2611
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2612
-		 "hal_ReadPowerValueFromPROM8821ae(): hwinfo[0x%x]=0x%x\n",
2613
-		 (eeAddr+1), hwinfo[eeAddr+1]);
2614
-	if (0xFF == hwinfo[eeAddr+1])  /*YJ,add,120316*/
2588
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2589
+		"hal_ReadPowerValueFromPROM8821ae(): hwinfo[0x%x]=0x%x\n",
2590
+		(eeaddr + 1), hwinfo[eeaddr + 1]);
2591
+	if (hwinfo[eeaddr + 1] == 0xFF)  /*YJ,add,120316*/
26152592 		autoload_fail = true;
26162593 
26172594 	if (autoload_fail) {
2618
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2619
-			 "auto load fail : Use Default value!\n");
2620
-		for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2595
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2596
+			"auto load fail : Use Default value!\n");
2597
+		for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
26212598 			/*2.4G default value*/
26222599 			for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2623
-				pwrinfo24g->index_cck_base[rfPath][group] =	0x2D;
2624
-				pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2600
+				pwrinfo24g->index_cck_base[rfpath][group] = 0x2D;
2601
+				pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D;
26252602 			}
2626
-			for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2627
-				if (TxCount == 0) {
2628
-					pwrinfo24g->bw20_diff[rfPath][0] = 0x02;
2629
-					pwrinfo24g->ofdm_diff[rfPath][0] = 0x04;
2603
+			for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2604
+				if (txcount == 0) {
2605
+					pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
2606
+					pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
26302607 				} else {
2631
-					pwrinfo24g->bw20_diff[rfPath][TxCount] = 0xFE;
2632
-					pwrinfo24g->bw40_diff[rfPath][TxCount] = 0xFE;
2633
-					pwrinfo24g->cck_diff[rfPath][TxCount] =	0xFE;
2634
-					pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0xFE;
2608
+					pwrinfo24g->bw20_diff[rfpath][txcount] = 0xFE;
2609
+					pwrinfo24g->bw40_diff[rfpath][txcount] = 0xFE;
2610
+					pwrinfo24g->cck_diff[rfpath][txcount] =	0xFE;
2611
+					pwrinfo24g->ofdm_diff[rfpath][txcount] = 0xFE;
26352612 				}
26362613 			}
26372614 			/*5G default value*/
26382615 			for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
2639
-				pwrinfo5g->index_bw40_base[rfPath][group] = 0x2A;
2616
+				pwrinfo5g->index_bw40_base[rfpath][group] = 0x2A;
26402617 
2641
-			for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2642
-				if (TxCount == 0) {
2643
-					pwrinfo5g->ofdm_diff[rfPath][0] = 0x04;
2644
-					pwrinfo5g->bw20_diff[rfPath][0] = 0x00;
2645
-					pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2646
-					pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2618
+			for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2619
+				if (txcount == 0) {
2620
+					pwrinfo5g->ofdm_diff[rfpath][0] = 0x04;
2621
+					pwrinfo5g->bw20_diff[rfpath][0] = 0x00;
2622
+					pwrinfo5g->bw80_diff[rfpath][0] = 0xFE;
2623
+					pwrinfo5g->bw160_diff[rfpath][0] = 0xFE;
26472624 				} else {
2648
-					pwrinfo5g->ofdm_diff[rfPath][0] = 0xFE;
2649
-					pwrinfo5g->bw20_diff[rfPath][0] = 0xFE;
2650
-					pwrinfo5g->bw40_diff[rfPath][0] = 0xFE;
2651
-					pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2652
-					pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2625
+					pwrinfo5g->ofdm_diff[rfpath][0] = 0xFE;
2626
+					pwrinfo5g->bw20_diff[rfpath][0] = 0xFE;
2627
+					pwrinfo5g->bw40_diff[rfpath][0] = 0xFE;
2628
+					pwrinfo5g->bw80_diff[rfpath][0] = 0xFE;
2629
+					pwrinfo5g->bw160_diff[rfpath][0] = 0xFE;
26532630 				}
26542631 			}
26552632 		}
....@@ -2658,112 +2635,112 @@
26582635 
26592636 	rtl_priv(hw)->efuse.txpwr_fromeprom = true;
26602637 
2661
-	for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2638
+	for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
26622639 		/*2.4G default value*/
26632640 		for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2664
-			pwrinfo24g->index_cck_base[rfPath][group] = hwinfo[eeAddr++];
2665
-			if (pwrinfo24g->index_cck_base[rfPath][group] == 0xFF)
2666
-				pwrinfo24g->index_cck_base[rfPath][group] = 0x2D;
2641
+			pwrinfo24g->index_cck_base[rfpath][group] = hwinfo[eeaddr++];
2642
+			if (pwrinfo24g->index_cck_base[rfpath][group] == 0xFF)
2643
+				pwrinfo24g->index_cck_base[rfpath][group] = 0x2D;
26672644 		}
26682645 		for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
2669
-			pwrinfo24g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2670
-			if (pwrinfo24g->index_bw40_base[rfPath][group] == 0xFF)
2671
-				pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2646
+			pwrinfo24g->index_bw40_base[rfpath][group] = hwinfo[eeaddr++];
2647
+			if (pwrinfo24g->index_bw40_base[rfpath][group] == 0xFF)
2648
+				pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D;
26722649 		}
2673
-		for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2674
-			if (TxCount == 0) {
2675
-				pwrinfo24g->bw40_diff[rfPath][TxCount] = 0;
2650
+		for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2651
+			if (txcount == 0) {
2652
+				pwrinfo24g->bw40_diff[rfpath][txcount] = 0;
26762653 				/*bit sign number to 8 bit sign number*/
2677
-				pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2678
-				if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2679
-					pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2654
+				pwrinfo24g->bw20_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4;
2655
+				if (pwrinfo24g->bw20_diff[rfpath][txcount] & BIT(3))
2656
+					pwrinfo24g->bw20_diff[rfpath][txcount] |= 0xF0;
26802657 				/*bit sign number to 8 bit sign number*/
2681
-				pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2682
-				if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2683
-					pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2658
+				pwrinfo24g->ofdm_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f);
2659
+				if (pwrinfo24g->ofdm_diff[rfpath][txcount] & BIT(3))
2660
+					pwrinfo24g->ofdm_diff[rfpath][txcount] |= 0xF0;
26842661 
2685
-				pwrinfo24g->cck_diff[rfPath][TxCount] = 0;
2686
-				eeAddr++;
2662
+				pwrinfo24g->cck_diff[rfpath][txcount] = 0;
2663
+				eeaddr++;
26872664 			} else {
2688
-				pwrinfo24g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr]&0xf0) >> 4;
2689
-				if (pwrinfo24g->bw40_diff[rfPath][TxCount] & BIT(3))
2690
-					pwrinfo24g->bw40_diff[rfPath][TxCount] |= 0xF0;
2665
+				pwrinfo24g->bw40_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4;
2666
+				if (pwrinfo24g->bw40_diff[rfpath][txcount] & BIT(3))
2667
+					pwrinfo24g->bw40_diff[rfpath][txcount] |= 0xF0;
26912668 
2692
-				pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2693
-				if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2694
-					pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2669
+				pwrinfo24g->bw20_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f);
2670
+				if (pwrinfo24g->bw20_diff[rfpath][txcount] & BIT(3))
2671
+					pwrinfo24g->bw20_diff[rfpath][txcount] |= 0xF0;
26952672 
2696
-				eeAddr++;
2673
+				eeaddr++;
26972674 
2698
-				pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2699
-				if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2700
-					pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2675
+				pwrinfo24g->ofdm_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4;
2676
+				if (pwrinfo24g->ofdm_diff[rfpath][txcount] & BIT(3))
2677
+					pwrinfo24g->ofdm_diff[rfpath][txcount] |= 0xF0;
27012678 
2702
-				pwrinfo24g->cck_diff[rfPath][TxCount] =	(hwinfo[eeAddr] & 0x0f);
2703
-				if (pwrinfo24g->cck_diff[rfPath][TxCount] & BIT(3))
2704
-					pwrinfo24g->cck_diff[rfPath][TxCount] |= 0xF0;
2679
+				pwrinfo24g->cck_diff[rfpath][txcount] =	(hwinfo[eeaddr] & 0x0f);
2680
+				if (pwrinfo24g->cck_diff[rfpath][txcount] & BIT(3))
2681
+					pwrinfo24g->cck_diff[rfpath][txcount] |= 0xF0;
27052682 
2706
-				eeAddr++;
2683
+				eeaddr++;
27072684 			}
27082685 		}
27092686 
27102687 		/*5G default value*/
27112688 		for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
2712
-			pwrinfo5g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2713
-			if (pwrinfo5g->index_bw40_base[rfPath][group] == 0xFF)
2714
-				pwrinfo5g->index_bw40_base[rfPath][group] = 0xFE;
2689
+			pwrinfo5g->index_bw40_base[rfpath][group] = hwinfo[eeaddr++];
2690
+			if (pwrinfo5g->index_bw40_base[rfpath][group] == 0xFF)
2691
+				pwrinfo5g->index_bw40_base[rfpath][group] = 0xFE;
27152692 		}
27162693 
2717
-		for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2718
-			if (TxCount == 0) {
2719
-				pwrinfo5g->bw40_diff[rfPath][TxCount] = 0;
2694
+		for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2695
+			if (txcount == 0) {
2696
+				pwrinfo5g->bw40_diff[rfpath][txcount] = 0;
27202697 
2721
-				pwrinfo5g->bw20_diff[rfPath][0] = (hwinfo[eeAddr] & 0xf0) >> 4;
2722
-				if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2723
-					pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2698
+				pwrinfo5g->bw20_diff[rfpath][0] = (hwinfo[eeaddr] & 0xf0) >> 4;
2699
+				if (pwrinfo5g->bw20_diff[rfpath][txcount] & BIT(3))
2700
+					pwrinfo5g->bw20_diff[rfpath][txcount] |= 0xF0;
27242701 
2725
-				pwrinfo5g->ofdm_diff[rfPath][0] = (hwinfo[eeAddr] & 0x0f);
2726
-				if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2727
-					pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2702
+				pwrinfo5g->ofdm_diff[rfpath][0] = (hwinfo[eeaddr] & 0x0f);
2703
+				if (pwrinfo5g->ofdm_diff[rfpath][txcount] & BIT(3))
2704
+					pwrinfo5g->ofdm_diff[rfpath][txcount] |= 0xF0;
27282705 
2729
-				eeAddr++;
2706
+				eeaddr++;
27302707 			} else {
2731
-				pwrinfo5g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2732
-				if (pwrinfo5g->bw40_diff[rfPath][TxCount] & BIT(3))
2733
-					pwrinfo5g->bw40_diff[rfPath][TxCount] |= 0xF0;
2708
+				pwrinfo5g->bw40_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0xf0) >> 4;
2709
+				if (pwrinfo5g->bw40_diff[rfpath][txcount] & BIT(3))
2710
+					pwrinfo5g->bw40_diff[rfpath][txcount] |= 0xF0;
27342711 
2735
-				pwrinfo5g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2736
-				if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2737
-					pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2712
+				pwrinfo5g->bw20_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f);
2713
+				if (pwrinfo5g->bw20_diff[rfpath][txcount] & BIT(3))
2714
+					pwrinfo5g->bw20_diff[rfpath][txcount] |= 0xF0;
27382715 
2739
-				eeAddr++;
2716
+				eeaddr++;
27402717 			}
27412718 		}
27422719 
2743
-		pwrinfo5g->ofdm_diff[rfPath][1] =	(hwinfo[eeAddr] & 0xf0) >> 4;
2744
-		pwrinfo5g->ofdm_diff[rfPath][2] =	(hwinfo[eeAddr] & 0x0f);
2720
+		pwrinfo5g->ofdm_diff[rfpath][1] =	(hwinfo[eeaddr] & 0xf0) >> 4;
2721
+		pwrinfo5g->ofdm_diff[rfpath][2] =	(hwinfo[eeaddr] & 0x0f);
27452722 
2746
-		eeAddr++;
2723
+		eeaddr++;
27472724 
2748
-		pwrinfo5g->ofdm_diff[rfPath][3] = (hwinfo[eeAddr] & 0x0f);
2725
+		pwrinfo5g->ofdm_diff[rfpath][3] = (hwinfo[eeaddr] & 0x0f);
27492726 
2750
-		eeAddr++;
2727
+		eeaddr++;
27512728 
2752
-		for (TxCount = 1; TxCount < MAX_TX_COUNT; TxCount++) {
2753
-			if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2754
-				pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2729
+		for (txcount = 1; txcount < MAX_TX_COUNT; txcount++) {
2730
+			if (pwrinfo5g->ofdm_diff[rfpath][txcount] & BIT(3))
2731
+				pwrinfo5g->ofdm_diff[rfpath][txcount] |= 0xF0;
27552732 		}
2756
-		for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2757
-			pwrinfo5g->bw80_diff[rfPath][TxCount] =	(hwinfo[eeAddr] & 0xf0) >> 4;
2733
+		for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
2734
+			pwrinfo5g->bw80_diff[rfpath][txcount] =	(hwinfo[eeaddr] & 0xf0) >> 4;
27582735 			/* 4bit sign number to 8 bit sign number */
2759
-			if (pwrinfo5g->bw80_diff[rfPath][TxCount] & BIT(3))
2760
-				pwrinfo5g->bw80_diff[rfPath][TxCount] |= 0xF0;
2736
+			if (pwrinfo5g->bw80_diff[rfpath][txcount] & BIT(3))
2737
+				pwrinfo5g->bw80_diff[rfpath][txcount] |= 0xF0;
27612738 			/* 4bit sign number to 8 bit sign number */
2762
-			pwrinfo5g->bw160_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2763
-			if (pwrinfo5g->bw160_diff[rfPath][TxCount] & BIT(3))
2764
-				pwrinfo5g->bw160_diff[rfPath][TxCount] |= 0xF0;
2739
+			pwrinfo5g->bw160_diff[rfpath][txcount] = (hwinfo[eeaddr] & 0x0f);
2740
+			if (pwrinfo5g->bw160_diff[rfpath][txcount] & BIT(3))
2741
+				pwrinfo5g->bw160_diff[rfpath][txcount] |= 0xF0;
27652742 
2766
-			eeAddr++;
2743
+			eeaddr++;
27672744 		}
27682745 	}
27692746 }
....@@ -2930,8 +2907,8 @@
29302907 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
29312908 
29322909 	if (!autoload_fail) {
2933
-		rtlhal->pa_type_2g = hwinfo[0xBC];
2934
-		rtlhal->lna_type_2g = hwinfo[0xBD];
2910
+		rtlhal->pa_type_2g = hwinfo[0XBC];
2911
+		rtlhal->lna_type_2g = hwinfo[0XBD];
29352912 		if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
29362913 			rtlhal->pa_type_2g = 0;
29372914 			rtlhal->lna_type_2g = 0;
....@@ -2943,8 +2920,8 @@
29432920 					   (rtlhal->lna_type_2g & BIT(3))) ?
29442921 					  1 : 0;
29452922 
2946
-		rtlhal->pa_type_5g = hwinfo[0xBC];
2947
-		rtlhal->lna_type_5g = hwinfo[0xBF];
2923
+		rtlhal->pa_type_5g = hwinfo[0XBC];
2924
+		rtlhal->lna_type_5g = hwinfo[0XBF];
29482925 		if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
29492926 			rtlhal->pa_type_5g = 0;
29502927 			rtlhal->lna_type_5g = 0;
....@@ -2969,18 +2946,18 @@
29692946 	struct rtl_priv *rtlpriv = rtl_priv(hw);
29702947 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
29712948 
2972
-	u8 ext_type_pa_2g_a  = (hwinfo[0xBD] & BIT(2))      >> 2; /* 0xBD[2] */
2973
-	u8 ext_type_pa_2g_b  = (hwinfo[0xBD] & BIT(6))      >> 6; /* 0xBD[6] */
2974
-	u8 ext_type_pa_5g_a  = (hwinfo[0xBF] & BIT(2))      >> 2; /* 0xBF[2] */
2975
-	u8 ext_type_pa_5g_b  = (hwinfo[0xBF] & BIT(6))      >> 6; /* 0xBF[6] */
2976
-	/* 0xBD[1:0] */
2977
-	u8 ext_type_lna_2g_a = (hwinfo[0xBD] & (BIT(1) | BIT(0))) >> 0;
2978
-	/* 0xBD[5:4] */
2979
-	u8 ext_type_lna_2g_b = (hwinfo[0xBD] & (BIT(5) | BIT(4))) >> 4;
2980
-	/* 0xBF[1:0] */
2981
-	u8 ext_type_lna_5g_a = (hwinfo[0xBF] & (BIT(1) | BIT(0))) >> 0;
2982
-	/* 0xBF[5:4] */
2983
-	u8 ext_type_lna_5g_b = (hwinfo[0xBF] & (BIT(5) | BIT(4))) >> 4;
2949
+	u8 ext_type_pa_2g_a  = (hwinfo[0XBD] & BIT(2))      >> 2; /* 0XBD[2] */
2950
+	u8 ext_type_pa_2g_b  = (hwinfo[0XBD] & BIT(6))      >> 6; /* 0XBD[6] */
2951
+	u8 ext_type_pa_5g_a  = (hwinfo[0XBF] & BIT(2))      >> 2; /* 0XBF[2] */
2952
+	u8 ext_type_pa_5g_b  = (hwinfo[0XBF] & BIT(6))      >> 6; /* 0XBF[6] */
2953
+	/* 0XBD[1:0] */
2954
+	u8 ext_type_lna_2g_a = (hwinfo[0XBD] & (BIT(1) | BIT(0))) >> 0;
2955
+	/* 0XBD[5:4] */
2956
+	u8 ext_type_lna_2g_b = (hwinfo[0XBD] & (BIT(5) | BIT(4))) >> 4;
2957
+	/* 0XBF[1:0] */
2958
+	u8 ext_type_lna_5g_a = (hwinfo[0XBF] & (BIT(1) | BIT(0))) >> 0;
2959
+	/* 0XBF[5:4] */
2960
+	u8 ext_type_lna_5g_b = (hwinfo[0XBF] & (BIT(5) | BIT(4))) >> 4;
29842961 
29852962 	_rtl8812ae_read_pa_type(hw, hwinfo, autoload_fail);
29862963 
....@@ -3008,8 +2985,8 @@
30082985 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
30092986 
30102987 	if (!autoload_fail) {
3011
-		rtlhal->pa_type_2g = hwinfo[0xBC];
3012
-		rtlhal->lna_type_2g = hwinfo[0xBD];
2988
+		rtlhal->pa_type_2g = hwinfo[0XBC];
2989
+		rtlhal->lna_type_2g = hwinfo[0XBD];
30132990 		if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
30142991 			rtlhal->pa_type_2g = 0;
30152992 			rtlhal->lna_type_2g = 0;
....@@ -3017,8 +2994,8 @@
30172994 		rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(5)) ? 1 : 0;
30182995 		rtlhal->external_lna_2g = (rtlhal->lna_type_2g & BIT(7)) ? 1 : 0;
30192996 
3020
-		rtlhal->pa_type_5g = hwinfo[0xBC];
3021
-		rtlhal->lna_type_5g = hwinfo[0xBF];
2997
+		rtlhal->pa_type_5g = hwinfo[0XBC];
2998
+		rtlhal->lna_type_5g = hwinfo[0XBF];
30222999 		if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
30233000 			rtlhal->pa_type_5g = 0;
30243001 			rtlhal->lna_type_5g = 0;
....@@ -3070,8 +3047,8 @@
30703047 		rtlhal->rfe_type = 0x04;
30713048 	}
30723049 
3073
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3074
-		 "RFE Type: 0x%2x\n", rtlhal->rfe_type);
3050
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3051
+		"RFE Type: 0x%2x\n", rtlhal->rfe_type);
30753052 }
30763053 
30773054 static void _rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
....@@ -3175,8 +3152,8 @@
31753152 		rtlefuse->board_type |= ODM_BOARD_BT;
31763153 
31773154 	rtlhal->board_type = rtlefuse->board_type;
3178
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3179
-		 "board_type = 0x%x\n", rtlefuse->board_type);
3155
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3156
+		"board_type = 0x%x\n", rtlefuse->board_type);
31803157 
31813158 	rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
31823159 	if (rtlefuse->eeprom_channelplan == 0xff)
....@@ -3198,8 +3175,8 @@
31983175 	}
31993176 
32003177 	rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
3201
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3202
-		 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
3178
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3179
+		"thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
32033180 
32043181 	if (!rtlefuse->autoload_failflag) {
32053182 		rtlefuse->antenna_div_cfg =
....@@ -3219,7 +3196,7 @@
32193196 		rtlefuse->antenna_div_type = 0;
32203197 	}
32213198 
3222
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3199
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
32233200 		"SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n",
32243201 		rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type);
32253202 
....@@ -3268,8 +3245,8 @@
32683245 	default:
32693246 		break;
32703247 	}
3271
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3272
-		 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
3248
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
3249
+		"RT Customized ID: 0x%02X\n", rtlhal->oem_id);
32733250 }*/
32743251 
32753252 void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw)
....@@ -3286,20 +3263,20 @@
32863263 	else
32873264 		rtlpriv->dm.rfpath_rxenable[0] =
32883265 		    rtlpriv->dm.rfpath_rxenable[1] = true;
3289
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
3290
-						rtlhal->version);
3266
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
3267
+		rtlhal->version);
32913268 
32923269 	tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
32933270 	if (tmp_u1b & BIT(4)) {
3294
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
3271
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
32953272 		rtlefuse->epromtype = EEPROM_93C46;
32963273 	} else {
3297
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
3274
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
32983275 		rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
32993276 	}
33003277 
33013278 	if (tmp_u1b & BIT(5)) {
3302
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
3279
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
33033280 		rtlefuse->autoload_failflag = false;
33043281 		_rtl8821ae_read_adapter_info(hw, false);
33053282 	} else {
....@@ -3400,8 +3377,8 @@
34003377 
34013378 	rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
34023379 
3403
-	RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3404
-		 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
3380
+	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
3381
+		"%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
34053382 }
34063383 
34073384 static u32 _rtl8821ae_rate_to_bitmap_2ssvht(__le16 vht_rate)
....@@ -3546,8 +3523,8 @@
35463523 	sta_entry = (struct rtl_sta_info *)sta->drv_priv;
35473524 	wirelessmode = sta_entry->wireless_mode;
35483525 
3549
-	RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3550
-		 "wireless mode = 0x%x\n", wirelessmode);
3526
+	rtl_dbg(rtlpriv, COMP_RATR, DBG_LOUD,
3527
+		"wireless mode = 0x%x\n", wirelessmode);
35513528 	if (mac->opmode == NL80211_IFTYPE_STATION ||
35523529 		mac->opmode == NL80211_IFTYPE_MESH_POINT) {
35533530 		curtxbw_40mhz = mac->bw_40;
....@@ -3697,8 +3674,8 @@
36973674 	ratr_bitmap = _rtl8821ae_set_ra_vht_ratr_bitmap(hw, wirelessmode,
36983675 							ratr_bitmap);
36993676 
3700
-	RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3701
-		 "ratr_bitmap :%x\n", ratr_bitmap);
3677
+	rtl_dbg(rtlpriv, COMP_RATR, DBG_LOUD,
3678
+		"ratr_bitmap :%x\n", ratr_bitmap);
37023679 
37033680 	/* *(u32 *)& rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
37043681 				       (ratr_index << 28)); */
....@@ -3714,10 +3691,10 @@
37143691 	rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
37153692 	rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
37163693 
3717
-	RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3718
-		 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
3719
-		 ratr_index, ratr_bitmap,
3720
-		 rate_mask[0], rate_mask[1],
3694
+	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
3695
+		"Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
3696
+		ratr_index, ratr_bitmap,
3697
+		rate_mask[0], rate_mask[1],
37213698 		 rate_mask[2], rate_mask[3],
37223699 		 rate_mask[4], rate_mask[5],
37233700 		 rate_mask[6]);
....@@ -3732,7 +3709,7 @@
37323709 	if (rtlpriv->dm.useramask)
37333710 		rtl8821ae_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
37343711 	else
3735
-		/*RT_TRACE(rtlpriv, COMP_RATR,DBG_LOUD,
3712
+		/*rtl_dbg(rtlpriv, COMP_RATR,DBG_LOUD,
37363713 			   "rtl8821ae_update_hal_rate_tbl() Error! 8821ae FW RA Only\n");*/
37373714 		rtl8821ae_update_hal_rate_table(hw, sta);
37383715 }
....@@ -3804,16 +3781,16 @@
38043781 		e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
38053782 
38063783 	if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
3807
-		RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3808
-			 "GPIOChangeRF  - HW Radio ON, RF ON\n");
3784
+		rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
3785
+			"GPIOChangeRF  - HW Radio ON, RF ON\n");
38093786 
38103787 		e_rfpowerstate_toset = ERFON;
38113788 		ppsc->hwradiooff = false;
38123789 		b_actuallyset = true;
38133790 	} else if ((!ppsc->hwradiooff)
38143791 		   && (e_rfpowerstate_toset == ERFOFF)) {
3815
-		RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3816
-			 "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
3792
+		rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
3793
+			"GPIOChangeRF  - HW Radio OFF, RF OFF\n");
38173794 
38183795 		e_rfpowerstate_toset = ERFOFF;
38193796 		ppsc->hwradiooff = true;
....@@ -3863,7 +3840,7 @@
38633840 		u8 cam_offset = 0;
38643841 		u8 clear_number = 5;
38653842 
3866
-		RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
3843
+		rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
38673844 
38683845 		for (idx = 0; idx < clear_number; idx++) {
38693846 			rtl_cam_mark_invalid(hw, cam_offset + idx);
....@@ -3890,8 +3867,8 @@
38903867 			enc_algo = CAM_AES;
38913868 			break;
38923869 		default:
3893
-			RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
3894
-				 "switch case %#x not processed\n", enc_algo);
3870
+			rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
3871
+				"switch case %#x not processed\n", enc_algo);
38953872 			enc_algo = CAM_TKIP;
38963873 			break;
38973874 		}
....@@ -3920,26 +3897,26 @@
39203897 		}
39213898 
39223899 		if (rtlpriv->sec.key_len[key_index] == 0) {
3923
-			RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3924
-				 "delete one entry, entry_id is %d\n",
3925
-				 entry_id);
3900
+			rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
3901
+				"delete one entry, entry_id is %d\n",
3902
+				entry_id);
39263903 			if (mac->opmode == NL80211_IFTYPE_AP)
39273904 				rtl_cam_del_entry(hw, p_macaddr);
39283905 			rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
39293906 		} else {
3930
-			RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3931
-				 "add one entry\n");
3907
+			rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
3908
+				"add one entry\n");
39323909 			if (is_pairwise) {
3933
-				RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3934
-					 "set Pairwise key\n");
3910
+				rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
3911
+					"set Pairwise key\n");
39353912 
39363913 				rtl_cam_add_one_entry(hw, macaddr, key_index,
39373914 						      entry_id, enc_algo,
39383915 						      CAM_CONFIG_NO_USEDK,
39393916 						      rtlpriv->sec.key_buf[key_index]);
39403917 			} else {
3941
-				RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
3942
-					 "set group key\n");
3918
+				rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
3919
+					"set group key\n");
39433920 
39443921 				if (mac->opmode == NL80211_IFTYPE_ADHOC) {
39453922 					rtl_cam_add_one_entry(hw,
....@@ -4004,7 +3981,7 @@
40043981 	if (write_into_reg)
40053982 		rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
40063983 
4007
-	RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
3984
+	rtl_dbg(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
40083985 		"receive_config=0x%08X, write_into_reg=%d\n",
40093986 		rtlpci->receive_config, write_into_reg);
40103987 }
....@@ -4033,10 +4010,10 @@
40334010 	rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
40344011 	for (addr = 0; addr < WKFMCAM_ADDR_NUM; addr++) {
40354012 		/* Set Rx packet buffer offset.
4036
-		 * RxBufer pointer increases 1,
4013
+		 * RXBufer pointer increases 1,
40374014 		 * we can access 8 bytes in Rx packet buffer.
40384015 		 * CAM start offset (unit: 1 byte) =  index*WKFMCAM_SIZE
4039
-		 * RxBufer addr = (CAM start offset +
4016
+		 * RXBufer addr = (CAM start offset +
40404017 		 *                 per entry offset of a WKFM CAM)/8
40414018 		 *	* index: The index of the wake up frame mask
40424019 		 *	* WKFMCAM_SIZE: the total size of one WKFM CAM
....@@ -4057,9 +4034,9 @@
40574034 				cam |= BIT(26);
40584035 
40594036 			rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4060
-			RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4061
-				 "WRITE entry[%d] 0x%x: %x\n", addr,
4062
-				  REG_PKTBUF_DBG_DATA_L, cam);
4037
+			rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
4038
+				"WRITE entry[%d] 0x%x: %x\n", addr,
4039
+				REG_PKTBUF_DBG_DATA_L, cam);
40634040 
40644041 			/* Write to Rx packet buffer. */
40654042 			rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
....@@ -4067,18 +4044,18 @@
40674044 			cam = rtl_pattern->mask[addr - 2];
40684045 
40694046 			rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4070
-			RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4071
-				 "WRITE entry[%d] 0x%x: %x\n", addr,
4072
-				  REG_PKTBUF_DBG_DATA_L, cam);
4047
+			rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
4048
+				"WRITE entry[%d] 0x%x: %x\n", addr,
4049
+				REG_PKTBUF_DBG_DATA_L, cam);
40734050 
40744051 			rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
40754052 		} else if (addr == 3 || addr == 5) {/* WKFM[127:0] */
40764053 			cam = rtl_pattern->mask[addr - 2];
40774054 
40784055 			rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_H, cam);
4079
-			RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4080
-				 "WRITE entry[%d] 0x%x: %x\n", addr,
4081
-				  REG_PKTBUF_DBG_DATA_H, cam);
4056
+			rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
4057
+				"WRITE entry[%d] 0x%x: %x\n", addr,
4058
+				REG_PKTBUF_DBG_DATA_H, cam);
40824059 
40834060 			rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0xf001);
40844061 		}