kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/drivers/net/wireless/intel/iwlwifi/iwl-eeprom-read.c
..
..
@@ -6,7 +6,7 @@
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  * GPL LICENSE SUMMARY
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  *
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  * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
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- * Copyright(c) 2018 Intel Corporation
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+ * Copyright(c) 2018 - 2019 Intel Corporation
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  *
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  * This program is free software; you can redistribute it and/or modify
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  * it under the terms of version 2 of the GNU General Public License as
..
..
@@ -16,11 +16,6 @@
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  * WITHOUT ANY WARRANTY; without even the implied warranty of
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  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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  * General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program; if not, write to the Free Software
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- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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- * USA
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  *
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  * The full GNU General Public License is included in this distribution
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  * in the file called COPYING.
..
..
@@ -32,7 +27,7 @@
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  * BSD LICENSE
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  *
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  * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
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- * Copyright(c) 2018 Intel Corporation
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+ * Copyright(c) 2018 - 2019 Intel Corporation
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  * All rights reserved.
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  *
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  * Redistribution and use in source and binary forms, with or without
..
..
@@ -198,34 +193,25 @@
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 {
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 	int ret;
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-	/* Enable 40MHz radio clock */
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-	iwl_write32(trans, CSR_GP_CNTRL,
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-		    iwl_read32(trans, CSR_GP_CNTRL) |
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-		    BIT(trans->cfg->csr->flag_init_done));
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+	ret = iwl_finish_nic_init(trans, trans->trans_cfg);
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+	if (ret)
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+		return ret;
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-	/* wait for clock to be ready */
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-	ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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-			   BIT(trans->cfg->csr->flag_mac_clock_ready),
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-			   BIT(trans->cfg->csr->flag_mac_clock_ready),
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-			   25000);
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-	if (ret < 0) {
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-		IWL_ERR(trans, "Time out access OTP\n");
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-	} else {
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-		iwl_set_bits_prph(trans, APMG_PS_CTRL_REG,
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-				  APMG_PS_CTRL_VAL_RESET_REQ);
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-		udelay(5);
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-		iwl_clear_bits_prph(trans, APMG_PS_CTRL_REG,
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-				    APMG_PS_CTRL_VAL_RESET_REQ);
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+	iwl_set_bits_prph(trans, APMG_PS_CTRL_REG,
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+			  APMG_PS_CTRL_VAL_RESET_REQ);
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+	udelay(5);
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+	iwl_clear_bits_prph(trans, APMG_PS_CTRL_REG,
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+			    APMG_PS_CTRL_VAL_RESET_REQ);
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205
 
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-		/*
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-		 * CSR auto clock gate disable bit -
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-		 * this is only applicable for HW with OTP shadow RAM
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-		 */
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-		if (trans->cfg->base_params->shadow_ram_support)
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-			iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
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-				    CSR_RESET_LINK_PWR_MGMT_DISABLED);
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-	}
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-	return ret;
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+	/*
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+	 * CSR auto clock gate disable bit -
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+	 * this is only applicable for HW with OTP shadow RAM
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+	 */
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+	if (trans->trans_cfg->base_params->shadow_ram_support)
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+		iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
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+			    CSR_RESET_LINK_PWR_MGMT_DISABLED);
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+
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+	return 0;
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 }
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 static int iwl_read_otp_word(struct iwl_trans *trans, u16 addr,
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@@ -342,7 +328,7 @@
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 		}
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 		/* more in the link list, continue */
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 		usedblocks++;
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-	} while (usedblocks <= trans->cfg->base_params->max_ll_items);
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+	} while (usedblocks <= trans->trans_cfg->base_params->max_ll_items);
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332
 
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 	/* OTP has no valid blocks */
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 	IWL_DEBUG_EEPROM(trans->dev, "OTP has no valid blocks\n");
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@@ -375,7 +361,7 @@
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 	if (nvm_is_otp < 0)
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 		return nvm_is_otp;
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-	sz = trans->cfg->base_params->eeprom_size;
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+	sz = trans->trans_cfg->base_params->eeprom_size;
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 	IWL_DEBUG_EEPROM(trans->dev, "NVM size = %d\n", sz);
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 	e = kmalloc(sz, GFP_KERNEL);
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@@ -410,7 +396,7 @@
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 			    CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
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 			    CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
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 		/* traversing the linked list if no shadow ram supported */
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-		if (!trans->cfg->base_params->shadow_ram_support) {
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+		if (!trans->trans_cfg->base_params->shadow_ram_support) {
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 			ret = iwl_find_otp_image(trans, &validblockaddr);
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 			if (ret)
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 				goto err_unlock;