forked from ~ljy/RK356X_SDK_RELEASE

hc
2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f
kernel/drivers/net/wireless/ath/ath10k/coredump.c
....@@ -1,18 +1,7 @@
1
+// SPDX-License-Identifier: ISC
12 /*
23 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
34 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4
- *
5
- * Permission to use, copy, modify, and/or distribute this software for any
6
- * purpose with or without fee is hereby granted, provided that the above
7
- * copyright notice and this permission notice appear in all copies.
8
- *
9
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
165 */
176
187 #include "coredump.h"
....@@ -277,6 +266,277 @@
277266 {0x38070, 0x380E0},
278267 {0x3A000, 0x3A064},
279268 {0x40000, 0x400A4},
269
+ {0x80000, 0x8000C},
270
+ {0x80010, 0x80020},
271
+};
272
+
273
+static const struct ath10k_mem_section qca6174_hw30_sdio_register_sections[] = {
274
+ {0x800, 0x810},
275
+ {0x820, 0x82C},
276
+ {0x830, 0x8F4},
277
+ {0x90C, 0x91C},
278
+ {0xA14, 0xA18},
279
+ {0xA84, 0xA94},
280
+ {0xAA8, 0xAD4},
281
+ {0xADC, 0xB40},
282
+ {0x1000, 0x10A4},
283
+ {0x10BC, 0x111C},
284
+ {0x1134, 0x1138},
285
+ {0x1144, 0x114C},
286
+ {0x1150, 0x115C},
287
+ {0x1160, 0x1178},
288
+ {0x1240, 0x1260},
289
+ {0x2000, 0x207C},
290
+ {0x3000, 0x3014},
291
+ {0x4000, 0x4014},
292
+ {0x5000, 0x5124},
293
+ {0x6000, 0x6040},
294
+ {0x6080, 0x60CC},
295
+ {0x6100, 0x611C},
296
+ {0x6140, 0x61D8},
297
+ {0x6200, 0x6238},
298
+ {0x6240, 0x628C},
299
+ {0x62C0, 0x62EC},
300
+ {0x6380, 0x63E8},
301
+ {0x6400, 0x6440},
302
+ {0x6480, 0x64CC},
303
+ {0x6500, 0x651C},
304
+ {0x6540, 0x6580},
305
+ {0x6600, 0x6638},
306
+ {0x6640, 0x668C},
307
+ {0x66C0, 0x66EC},
308
+ {0x6780, 0x67E8},
309
+ {0x7080, 0x708C},
310
+ {0x70C0, 0x70C8},
311
+ {0x7400, 0x741C},
312
+ {0x7440, 0x7454},
313
+ {0x7800, 0x7818},
314
+ {0x8010, 0x8060},
315
+ {0x8080, 0x8084},
316
+ {0x80A0, 0x80A4},
317
+ {0x80C0, 0x80C4},
318
+ {0x80E0, 0x80ec},
319
+ {0x8110, 0x8128},
320
+ {0x9000, 0x9004},
321
+ {0xF000, 0xF0E0},
322
+ {0xF140, 0xF190},
323
+ {0xF250, 0xF25C},
324
+ {0xF260, 0xF268},
325
+ {0xF26C, 0xF2A8},
326
+ {0x10008, 0x1000C},
327
+ {0x10014, 0x10018},
328
+ {0x1001C, 0x10020},
329
+ {0x10024, 0x10028},
330
+ {0x10030, 0x10034},
331
+ {0x10040, 0x10054},
332
+ {0x10058, 0x1007C},
333
+ {0x10080, 0x100C4},
334
+ {0x100C8, 0x10114},
335
+ {0x1012C, 0x10130},
336
+ {0x10138, 0x10144},
337
+ {0x10200, 0x10220},
338
+ {0x10230, 0x10250},
339
+ {0x10260, 0x10280},
340
+ {0x10290, 0x102B0},
341
+ {0x102C0, 0x102DC},
342
+ {0x102E0, 0x102F4},
343
+ {0x102FC, 0x1037C},
344
+ {0x10380, 0x10390},
345
+ {0x10800, 0x10828},
346
+ {0x10840, 0x10844},
347
+ {0x10880, 0x10884},
348
+ {0x108C0, 0x108E8},
349
+ {0x10900, 0x10928},
350
+ {0x10940, 0x10944},
351
+ {0x10980, 0x10984},
352
+ {0x109C0, 0x109E8},
353
+ {0x10A00, 0x10A28},
354
+ {0x10A40, 0x10A50},
355
+ {0x11000, 0x11028},
356
+ {0x11030, 0x11034},
357
+ {0x11038, 0x11068},
358
+ {0x11070, 0x11074},
359
+ {0x11078, 0x110A8},
360
+ {0x110B0, 0x110B4},
361
+ {0x110B8, 0x110E8},
362
+ {0x110F0, 0x110F4},
363
+ {0x110F8, 0x11128},
364
+ {0x11138, 0x11144},
365
+ {0x11178, 0x11180},
366
+ {0x111B8, 0x111C0},
367
+ {0x111F8, 0x11200},
368
+ {0x11238, 0x1123C},
369
+ {0x11270, 0x11274},
370
+ {0x11278, 0x1127C},
371
+ {0x112B0, 0x112B4},
372
+ {0x112B8, 0x112BC},
373
+ {0x112F0, 0x112F4},
374
+ {0x112F8, 0x112FC},
375
+ {0x11338, 0x1133C},
376
+ {0x11378, 0x1137C},
377
+ {0x113B8, 0x113BC},
378
+ {0x113F8, 0x113FC},
379
+ {0x11438, 0x11440},
380
+ {0x11478, 0x11480},
381
+ {0x114B8, 0x114BC},
382
+ {0x114F8, 0x114FC},
383
+ {0x11538, 0x1153C},
384
+ {0x11578, 0x1157C},
385
+ {0x115B8, 0x115BC},
386
+ {0x115F8, 0x115FC},
387
+ {0x11638, 0x1163C},
388
+ {0x11678, 0x1167C},
389
+ {0x116B8, 0x116BC},
390
+ {0x116F8, 0x116FC},
391
+ {0x11738, 0x1173C},
392
+ {0x11778, 0x1177C},
393
+ {0x117B8, 0x117BC},
394
+ {0x117F8, 0x117FC},
395
+ {0x17000, 0x1701C},
396
+ {0x17020, 0x170AC},
397
+ {0x18000, 0x18050},
398
+ {0x18054, 0x18074},
399
+ {0x18080, 0x180D4},
400
+ {0x180DC, 0x18104},
401
+ {0x18108, 0x1813C},
402
+ {0x18144, 0x18148},
403
+ {0x18168, 0x18174},
404
+ {0x18178, 0x18180},
405
+ {0x181C8, 0x181E0},
406
+ {0x181E4, 0x181E8},
407
+ {0x181EC, 0x1820C},
408
+ {0x1825C, 0x18280},
409
+ {0x18284, 0x18290},
410
+ {0x18294, 0x182A0},
411
+ {0x18300, 0x18304},
412
+ {0x18314, 0x18320},
413
+ {0x18328, 0x18350},
414
+ {0x1835C, 0x1836C},
415
+ {0x18370, 0x18390},
416
+ {0x18398, 0x183AC},
417
+ {0x183BC, 0x183D8},
418
+ {0x183DC, 0x183F4},
419
+ {0x18400, 0x186F4},
420
+ {0x186F8, 0x1871C},
421
+ {0x18720, 0x18790},
422
+ {0x19800, 0x19830},
423
+ {0x19834, 0x19840},
424
+ {0x19880, 0x1989C},
425
+ {0x198A4, 0x198B0},
426
+ {0x198BC, 0x19900},
427
+ {0x19C00, 0x19C88},
428
+ {0x19D00, 0x19D20},
429
+ {0x19E00, 0x19E7C},
430
+ {0x19E80, 0x19E94},
431
+ {0x19E98, 0x19EAC},
432
+ {0x19EB0, 0x19EBC},
433
+ {0x19F70, 0x19F74},
434
+ {0x19F80, 0x19F8C},
435
+ {0x19FA0, 0x19FB4},
436
+ {0x19FC0, 0x19FD8},
437
+ {0x1A000, 0x1A200},
438
+ {0x1A204, 0x1A210},
439
+ {0x1A228, 0x1A22C},
440
+ {0x1A230, 0x1A248},
441
+ {0x1A250, 0x1A270},
442
+ {0x1A280, 0x1A290},
443
+ {0x1A2A0, 0x1A2A4},
444
+ {0x1A2C0, 0x1A2EC},
445
+ {0x1A300, 0x1A3BC},
446
+ {0x1A3F0, 0x1A3F4},
447
+ {0x1A3F8, 0x1A434},
448
+ {0x1A438, 0x1A444},
449
+ {0x1A448, 0x1A468},
450
+ {0x1A580, 0x1A58C},
451
+ {0x1A644, 0x1A654},
452
+ {0x1A670, 0x1A698},
453
+ {0x1A6AC, 0x1A6B0},
454
+ {0x1A6D0, 0x1A6D4},
455
+ {0x1A6EC, 0x1A70C},
456
+ {0x1A710, 0x1A738},
457
+ {0x1A7C0, 0x1A7D0},
458
+ {0x1A7D4, 0x1A7D8},
459
+ {0x1A7DC, 0x1A7E4},
460
+ {0x1A7F0, 0x1A7F8},
461
+ {0x1A888, 0x1A89C},
462
+ {0x1A8A8, 0x1A8AC},
463
+ {0x1A8C0, 0x1A8DC},
464
+ {0x1A8F0, 0x1A8FC},
465
+ {0x1AE04, 0x1AE08},
466
+ {0x1AE18, 0x1AE24},
467
+ {0x1AF80, 0x1AF8C},
468
+ {0x1AFA0, 0x1AFB4},
469
+ {0x1B000, 0x1B200},
470
+ {0x1B284, 0x1B288},
471
+ {0x1B2D0, 0x1B2D8},
472
+ {0x1B2DC, 0x1B2EC},
473
+ {0x1B300, 0x1B340},
474
+ {0x1B374, 0x1B378},
475
+ {0x1B380, 0x1B384},
476
+ {0x1B388, 0x1B38C},
477
+ {0x1B404, 0x1B408},
478
+ {0x1B420, 0x1B428},
479
+ {0x1B440, 0x1B444},
480
+ {0x1B448, 0x1B44C},
481
+ {0x1B450, 0x1B458},
482
+ {0x1B45C, 0x1B468},
483
+ {0x1B584, 0x1B58C},
484
+ {0x1B68C, 0x1B690},
485
+ {0x1B6AC, 0x1B6B0},
486
+ {0x1B7F0, 0x1B7F8},
487
+ {0x1C800, 0x1CC00},
488
+ {0x1CE00, 0x1CE04},
489
+ {0x1CF80, 0x1CF84},
490
+ {0x1D200, 0x1D800},
491
+ {0x1E000, 0x20014},
492
+ {0x20100, 0x20124},
493
+ {0x21400, 0x217A8},
494
+ {0x21800, 0x21BA8},
495
+ {0x21C00, 0x21FA8},
496
+ {0x22000, 0x223A8},
497
+ {0x22400, 0x227A8},
498
+ {0x22800, 0x22BA8},
499
+ {0x22C00, 0x22FA8},
500
+ {0x23000, 0x233A8},
501
+ {0x24000, 0x24034},
502
+
503
+ /* EFUSE0,1,2 is disabled here
504
+ * because its state may be reset
505
+ *
506
+ * {0x24800, 0x24804},
507
+ * {0x25000, 0x25004},
508
+ * {0x25800, 0x25804},
509
+ */
510
+
511
+ {0x26000, 0x26064},
512
+ {0x27000, 0x27024},
513
+ {0x34000, 0x3400C},
514
+ {0x34400, 0x3445C},
515
+ {0x34800, 0x3485C},
516
+ {0x34C00, 0x34C5C},
517
+ {0x35000, 0x3505C},
518
+ {0x35400, 0x3545C},
519
+ {0x35800, 0x3585C},
520
+ {0x35C00, 0x35C5C},
521
+ {0x36000, 0x3605C},
522
+ {0x38000, 0x38064},
523
+ {0x38070, 0x380E0},
524
+ {0x3A000, 0x3A074},
525
+
526
+ /* DBI windows is skipped here, it can be only accessed when pcie
527
+ * is active (not in reset) and CORE_CTRL_PCIE_LTSSM_EN = 0 &&
528
+ * PCIE_CTRL_APP_LTSSM_ENALBE=0.
529
+ * {0x3C000 , 0x3C004},
530
+ */
531
+
532
+ {0x40000, 0x400A4},
533
+
534
+ /* SI register is skiped here.
535
+ * Because it will cause bus hang
536
+ *
537
+ * {0x50000, 0x50018},
538
+ */
539
+
280540 {0x80000, 0x8000C},
281541 {0x80010, 0x80020},
282542 };
....@@ -613,6 +873,59 @@
613873 },
614874 };
615875
876
+static const struct ath10k_mem_region qca6174_hw30_sdio_mem_regions[] = {
877
+ {
878
+ .type = ATH10K_MEM_REGION_TYPE_DRAM,
879
+ .start = 0x400000,
880
+ .len = 0xa8000,
881
+ .name = "DRAM",
882
+ .section_table = {
883
+ .sections = NULL,
884
+ .size = 0,
885
+ },
886
+ },
887
+ {
888
+ .type = ATH10K_MEM_REGION_TYPE_AXI,
889
+ .start = 0xa0000,
890
+ .len = 0x18000,
891
+ .name = "AXI",
892
+ .section_table = {
893
+ .sections = NULL,
894
+ .size = 0,
895
+ },
896
+ },
897
+ {
898
+ .type = ATH10K_MEM_REGION_TYPE_IRAM1,
899
+ .start = 0x00980000,
900
+ .len = 0x00080000,
901
+ .name = "IRAM1",
902
+ .section_table = {
903
+ .sections = NULL,
904
+ .size = 0,
905
+ },
906
+ },
907
+ {
908
+ .type = ATH10K_MEM_REGION_TYPE_IRAM2,
909
+ .start = 0x00a00000,
910
+ .len = 0x00040000,
911
+ .name = "IRAM2",
912
+ .section_table = {
913
+ .sections = NULL,
914
+ .size = 0,
915
+ },
916
+ },
917
+ {
918
+ .type = ATH10K_MEM_REGION_TYPE_REG,
919
+ .start = 0x800,
920
+ .len = 0x80020 - 0x800,
921
+ .name = "REG_TOTAL",
922
+ .section_table = {
923
+ .sections = qca6174_hw30_sdio_register_sections,
924
+ .size = ARRAY_SIZE(qca6174_hw30_sdio_register_sections),
925
+ },
926
+ },
927
+};
928
+
616929 static const struct ath10k_mem_region qca6174_hw30_mem_regions[] = {
617930 {
618931 .type = ATH10K_MEM_REGION_TYPE_DRAM,
....@@ -714,7 +1027,7 @@
7141027 },
7151028 {
7161029 .type = ATH10K_MEM_REGION_TYPE_REG,
717
- .start = 0x98000,
1030
+ .start = 0x980000,
7181031 .len = 0x50000,
7191032 .name = "IRAM",
7201033 .section_table = {
....@@ -797,7 +1110,7 @@
7971110 },
7981111 {
7991112 .type = ATH10K_MEM_REGION_TYPE_REG,
800
- .start = 0x98000,
1113
+ .start = 0x980000,
8011114 .len = 0x50000,
8021115 .name = "IRAM",
8031116 .section_table = {
....@@ -867,9 +1180,119 @@
8671180 },
8681181 };
8691182
1183
+static const struct ath10k_mem_section ipq4019_soc_reg_range[] = {
1184
+ {0x080000, 0x080004},
1185
+ {0x080020, 0x080024},
1186
+ {0x080028, 0x080050},
1187
+ {0x0800d4, 0x0800ec},
1188
+ {0x08010c, 0x080118},
1189
+ {0x080284, 0x080290},
1190
+ {0x0802a8, 0x0802b8},
1191
+ {0x0802dc, 0x08030c},
1192
+ {0x082000, 0x083fff}
1193
+};
1194
+
1195
+static const struct ath10k_mem_region qca4019_hw10_mem_regions[] = {
1196
+ {
1197
+ .type = ATH10K_MEM_REGION_TYPE_DRAM,
1198
+ .start = 0x400000,
1199
+ .len = 0x68000,
1200
+ .name = "DRAM",
1201
+ .section_table = {
1202
+ .sections = NULL,
1203
+ .size = 0,
1204
+ },
1205
+ },
1206
+ {
1207
+ .type = ATH10K_MEM_REGION_TYPE_REG,
1208
+ .start = 0xC0000,
1209
+ .len = 0x40000,
1210
+ .name = "SRAM",
1211
+ .section_table = {
1212
+ .sections = NULL,
1213
+ .size = 0,
1214
+ },
1215
+ },
1216
+ {
1217
+ .type = ATH10K_MEM_REGION_TYPE_REG,
1218
+ .start = 0x980000,
1219
+ .len = 0x50000,
1220
+ .name = "IRAM",
1221
+ .section_table = {
1222
+ .sections = NULL,
1223
+ .size = 0,
1224
+ },
1225
+ },
1226
+ {
1227
+ .type = ATH10K_MEM_REGION_TYPE_IOREG,
1228
+ .start = 0x30000,
1229
+ .len = 0x7000,
1230
+ .name = "APB REG 1",
1231
+ .section_table = {
1232
+ .sections = NULL,
1233
+ .size = 0,
1234
+ },
1235
+ },
1236
+ {
1237
+ .type = ATH10K_MEM_REGION_TYPE_IOREG,
1238
+ .start = 0x3f000,
1239
+ .len = 0x3000,
1240
+ .name = "APB REG 2",
1241
+ .section_table = {
1242
+ .sections = NULL,
1243
+ .size = 0,
1244
+ },
1245
+ },
1246
+ {
1247
+ .type = ATH10K_MEM_REGION_TYPE_IOREG,
1248
+ .start = 0x43000,
1249
+ .len = 0x3000,
1250
+ .name = "WIFI REG",
1251
+ .section_table = {
1252
+ .sections = NULL,
1253
+ .size = 0,
1254
+ },
1255
+ },
1256
+ {
1257
+ .type = ATH10K_MEM_REGION_TYPE_IOREG,
1258
+ .start = 0x4A000,
1259
+ .len = 0x5000,
1260
+ .name = "CE REG",
1261
+ .section_table = {
1262
+ .sections = NULL,
1263
+ .size = 0,
1264
+ },
1265
+ },
1266
+ {
1267
+ .type = ATH10K_MEM_REGION_TYPE_REG,
1268
+ .start = 0x080000,
1269
+ .len = 0x083fff - 0x080000,
1270
+ .name = "REG_TOTAL",
1271
+ .section_table = {
1272
+ .sections = ipq4019_soc_reg_range,
1273
+ .size = ARRAY_SIZE(ipq4019_soc_reg_range),
1274
+ },
1275
+ },
1276
+};
1277
+
1278
+static const struct ath10k_mem_region wcn399x_hw10_mem_regions[] = {
1279
+ {
1280
+ /* MSA region start is not fixed, hence it is assigned at runtime */
1281
+ .type = ATH10K_MEM_REGION_TYPE_MSA,
1282
+ .len = 0x100000,
1283
+ .name = "DRAM",
1284
+ .section_table = {
1285
+ .sections = NULL,
1286
+ .size = 0,
1287
+ },
1288
+ },
1289
+};
1290
+
8701291 static const struct ath10k_hw_mem_layout hw_mem_layouts[] = {
8711292 {
8721293 .hw_id = QCA6174_HW_1_0_VERSION,
1294
+ .hw_rev = ATH10K_HW_QCA6174,
1295
+ .bus = ATH10K_BUS_PCI,
8731296 .region_table = {
8741297 .regions = qca6174_hw10_mem_regions,
8751298 .size = ARRAY_SIZE(qca6174_hw10_mem_regions),
....@@ -877,6 +1300,8 @@
8771300 },
8781301 {
8791302 .hw_id = QCA6174_HW_1_1_VERSION,
1303
+ .hw_rev = ATH10K_HW_QCA6174,
1304
+ .bus = ATH10K_BUS_PCI,
8801305 .region_table = {
8811306 .regions = qca6174_hw10_mem_regions,
8821307 .size = ARRAY_SIZE(qca6174_hw10_mem_regions),
....@@ -884,6 +1309,8 @@
8841309 },
8851310 {
8861311 .hw_id = QCA6174_HW_1_3_VERSION,
1312
+ .hw_rev = ATH10K_HW_QCA6174,
1313
+ .bus = ATH10K_BUS_PCI,
8871314 .region_table = {
8881315 .regions = qca6174_hw10_mem_regions,
8891316 .size = ARRAY_SIZE(qca6174_hw10_mem_regions),
....@@ -891,6 +1318,8 @@
8911318 },
8921319 {
8931320 .hw_id = QCA6174_HW_2_1_VERSION,
1321
+ .hw_rev = ATH10K_HW_QCA6174,
1322
+ .bus = ATH10K_BUS_PCI,
8941323 .region_table = {
8951324 .regions = qca6174_hw21_mem_regions,
8961325 .size = ARRAY_SIZE(qca6174_hw21_mem_regions),
....@@ -898,6 +1327,8 @@
8981327 },
8991328 {
9001329 .hw_id = QCA6174_HW_3_0_VERSION,
1330
+ .hw_rev = ATH10K_HW_QCA6174,
1331
+ .bus = ATH10K_BUS_PCI,
9011332 .region_table = {
9021333 .regions = qca6174_hw30_mem_regions,
9031334 .size = ARRAY_SIZE(qca6174_hw30_mem_regions),
....@@ -905,13 +1336,26 @@
9051336 },
9061337 {
9071338 .hw_id = QCA6174_HW_3_2_VERSION,
1339
+ .hw_rev = ATH10K_HW_QCA6174,
1340
+ .bus = ATH10K_BUS_PCI,
9081341 .region_table = {
9091342 .regions = qca6174_hw30_mem_regions,
9101343 .size = ARRAY_SIZE(qca6174_hw30_mem_regions),
9111344 },
9121345 },
9131346 {
1347
+ .hw_id = QCA6174_HW_3_2_VERSION,
1348
+ .hw_rev = ATH10K_HW_QCA6174,
1349
+ .bus = ATH10K_BUS_SDIO,
1350
+ .region_table = {
1351
+ .regions = qca6174_hw30_sdio_mem_regions,
1352
+ .size = ARRAY_SIZE(qca6174_hw30_sdio_mem_regions),
1353
+ },
1354
+ },
1355
+ {
9141356 .hw_id = QCA9377_HW_1_1_DEV_VERSION,
1357
+ .hw_rev = ATH10K_HW_QCA9377,
1358
+ .bus = ATH10K_BUS_PCI,
9151359 .region_table = {
9161360 .regions = qca6174_hw30_mem_regions,
9171361 .size = ARRAY_SIZE(qca6174_hw30_mem_regions),
....@@ -919,6 +1363,8 @@
9191363 },
9201364 {
9211365 .hw_id = QCA988X_HW_2_0_VERSION,
1366
+ .hw_rev = ATH10K_HW_QCA988X,
1367
+ .bus = ATH10K_BUS_PCI,
9221368 .region_table = {
9231369 .regions = qca988x_hw20_mem_regions,
9241370 .size = ARRAY_SIZE(qca988x_hw20_mem_regions),
....@@ -926,6 +1372,8 @@
9261372 },
9271373 {
9281374 .hw_id = QCA9984_HW_1_0_DEV_VERSION,
1375
+ .hw_rev = ATH10K_HW_QCA9984,
1376
+ .bus = ATH10K_BUS_PCI,
9291377 .region_table = {
9301378 .regions = qca9984_hw10_mem_regions,
9311379 .size = ARRAY_SIZE(qca9984_hw10_mem_regions),
....@@ -933,6 +1381,8 @@
9331381 },
9341382 {
9351383 .hw_id = QCA9888_HW_2_0_DEV_VERSION,
1384
+ .hw_rev = ATH10K_HW_QCA9888,
1385
+ .bus = ATH10K_BUS_PCI,
9361386 .region_table = {
9371387 .regions = qca9984_hw10_mem_regions,
9381388 .size = ARRAY_SIZE(qca9984_hw10_mem_regions),
....@@ -940,12 +1390,31 @@
9401390 },
9411391 {
9421392 .hw_id = QCA99X0_HW_2_0_DEV_VERSION,
1393
+ .hw_rev = ATH10K_HW_QCA99X0,
1394
+ .bus = ATH10K_BUS_PCI,
9431395 .region_table = {
9441396 .regions = qca99x0_hw20_mem_regions,
9451397 .size = ARRAY_SIZE(qca99x0_hw20_mem_regions),
9461398 },
9471399 },
948
-
1400
+ {
1401
+ .hw_id = QCA4019_HW_1_0_DEV_VERSION,
1402
+ .hw_rev = ATH10K_HW_QCA4019,
1403
+ .bus = ATH10K_BUS_AHB,
1404
+ .region_table = {
1405
+ .regions = qca4019_hw10_mem_regions,
1406
+ .size = ARRAY_SIZE(qca4019_hw10_mem_regions),
1407
+ },
1408
+ },
1409
+ {
1410
+ .hw_id = WCN3990_HW_1_0_DEV_VERSION,
1411
+ .hw_rev = ATH10K_HW_WCN3990,
1412
+ .bus = ATH10K_BUS_SNOC,
1413
+ .region_table = {
1414
+ .regions = wcn399x_hw10_mem_regions,
1415
+ .size = ARRAY_SIZE(wcn399x_hw10_mem_regions),
1416
+ },
1417
+ },
9491418 };
9501419
9511420 static u32 ath10k_coredump_get_ramdump_size(struct ath10k *ar)
....@@ -987,7 +1456,9 @@
9871456 return NULL;
9881457
9891458 for (i = 0; i < ARRAY_SIZE(hw_mem_layouts); i++) {
990
- if (ar->target_version == hw_mem_layouts[i].hw_id)
1459
+ if (ar->target_version == hw_mem_layouts[i].hw_id &&
1460
+ ar->hw_rev == hw_mem_layouts[i].hw_rev &&
1461
+ hw_mem_layouts[i].bus == ar->hif.bus)
9911462 return &hw_mem_layouts[i];
9921463 }
9931464
....@@ -999,7 +1470,7 @@
9991470 {
10001471 struct ath10k_fw_crash_data *crash_data = ar->coredump.fw_crash_data;
10011472
1002
- lockdep_assert_held(&ar->data_lock);
1473
+ lockdep_assert_held(&ar->dump_mutex);
10031474
10041475 if (ath10k_coredump_mask == 0)
10051476 /* coredump disabled */
....@@ -1043,7 +1514,7 @@
10431514 if (!buf)
10441515 return NULL;
10451516
1046
- spin_lock_bh(&ar->data_lock);
1517
+ mutex_lock(&ar->dump_mutex);
10471518
10481519 dump_data = (struct ath10k_dump_file_data *)(buf);
10491520 strlcpy(dump_data->df_magic, "ATH10K-FW-DUMP",
....@@ -1053,7 +1524,7 @@
10531524 dump_data->version = cpu_to_le32(ATH10K_FW_CRASH_DUMP_VERSION);
10541525
10551526 guid_copy(&dump_data->guid, &crash_data->guid);
1056
- dump_data->chip_id = cpu_to_le32(ar->chip_id);
1527
+ dump_data->chip_id = cpu_to_le32(ar->bus_param.chip_id);
10571528 dump_data->bus_type = cpu_to_le32(0);
10581529 dump_data->target_version = cpu_to_le32(ar->target_version);
10591530 dump_data->fw_version_major = cpu_to_le32(ar->fw_version_major);
....@@ -1089,8 +1560,8 @@
10891560 if (test_bit(ATH10K_FW_CRASH_DUMP_CE_DATA, &ath10k_coredump_mask)) {
10901561 dump_tlv = (struct ath10k_tlv_dump_data *)(buf + sofar);
10911562 dump_tlv->type = cpu_to_le32(ATH10K_FW_CRASH_DUMP_CE_DATA);
1092
- dump_tlv->tlv_len = cpu_to_le32(sizeof(*ce_hdr) +
1093
- CE_COUNT * sizeof(ce_hdr->entries[0]));
1563
+ dump_tlv->tlv_len = cpu_to_le32(struct_size(ce_hdr, entries,
1564
+ CE_COUNT));
10941565 ce_hdr = (struct ath10k_ce_crash_hdr *)(dump_tlv->tlv_data);
10951566 ce_hdr->ce_count = cpu_to_le32(CE_COUNT);
10961567 memset(ce_hdr->reserved, 0, sizeof(ce_hdr->reserved));
....@@ -1112,7 +1583,7 @@
11121583 }
11131584 }
11141585
1115
- spin_unlock_bh(&ar->data_lock);
1586
+ mutex_unlock(&ar->dump_mutex);
11161587
11171588 return dump_data;
11181589 }