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2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f 
 kernel/drivers/net/ethernet/intel/i40e/i40e_txrx.h
....@@ -18,10 +18,7 @@
1818 #define I40E_ITR_DYNAMIC	0x8000	/* use top bit as a flag */
1919 #define I40E_ITR_MASK		0x1FFE	/* mask for ITR register value */
2020 #define I40E_MIN_ITR		     2	/* reg uses 2 usec resolution */
21
-#define I40E_ITR_100K		    10	/* all values below must be even */
22
-#define I40E_ITR_50K		    20
2321 #define I40E_ITR_20K		    50
24
-#define I40E_ITR_18K		    60
2522 #define I40E_ITR_8K		   122
2623 #define I40E_MAX_ITR		  8160	/* maximum value as per datasheet */
2724 #define ITR_TO_REG(setting) ((setting) & ~I40E_ITR_DYNAMIC)
....@@ -52,9 +49,6 @@
5249 	else
5350 		return 0;
5451 }
55
-#define I40E_INTRL_8K              125     /* 8000 ints/sec */
56
-#define I40E_INTRL_62K             16      /* 62500 ints/sec */
57
-#define I40E_INTRL_83K             12      /* 83333 ints/sec */
5852 
5953 #define I40E_QUEUE_END_OF_LIST 0x7FF
6054 
....@@ -73,7 +67,6 @@
7367 /* these are indexes into ITRN registers */
7468 #define I40E_RX_ITR    I40E_IDX_ITR0
7569 #define I40E_TX_ITR    I40E_IDX_ITR1
76
-#define I40E_PE_ITR    I40E_IDX_ITR2
7770 
7871 /* Supported RSS offloads */
7972 #define I40E_DEFAULT_RSS_HENA ( \
....@@ -117,7 +110,7 @@
117110  */
118111 #define I40E_RX_HDR_SIZE I40E_RXBUFFER_256
119112 #define I40E_PACKET_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2))
120
-#define i40e_rx_desc i40e_32byte_rx_desc
113
+#define i40e_rx_desc i40e_16byte_rx_desc
121114 
122115 #define I40E_RX_DMA_ATTR \
123116 	(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
....@@ -193,13 +186,6 @@
193186 
194187 /* How many Rx Buffers do we bundle into one write to the hardware ? */
195188 #define I40E_RX_BUFFER_WRITE	32	/* Must be power of 2 */
196
-#define I40E_RX_INCREMENT(r, i) \
197
-	do {					\
198
-		(i)++;				\
199
-		if ((i) == (r)->count)		\
200
-			i = 0;			\
201
-		r->next_to_clean = i;		\
202
-	} while (0)
203189 
204190 #define I40E_RX_NEXT_DESC(r, i, n)		\
205191 	do {					\
....@@ -209,11 +195,6 @@
209195 		(n) = I40E_RX_DESC((r), (i));	\
210196 	} while (0)
211197 
212
-#define I40E_RX_NEXT_DESC_PREFETCH(r, i, n)		\
213
-	do {						\
214
-		I40E_RX_NEXT_DESC((r), (i), (n));	\
215
-		prefetch((n));				\
216
-	} while (0)
217198 
218199 #define I40E_MAX_BUFFER_TXD	8
219200 #define I40E_MIN_TX_LEN		17
....@@ -262,15 +243,12 @@
262243 
263244 /* Tx Descriptors needed, worst case */
264245 #define DESC_NEEDED (MAX_SKB_FRAGS + 6)
265
-#define I40E_MIN_DESC_PENDING	4
266246 
267247 #define I40E_TX_FLAGS_HW_VLAN		BIT(1)
268248 #define I40E_TX_FLAGS_SW_VLAN		BIT(2)
269249 #define I40E_TX_FLAGS_TSO		BIT(3)
270250 #define I40E_TX_FLAGS_IPV4		BIT(4)
271251 #define I40E_TX_FLAGS_IPV6		BIT(5)
272
-#define I40E_TX_FLAGS_FCCRC		BIT(6)
273
-#define I40E_TX_FLAGS_FSO		BIT(7)
274252 #define I40E_TX_FLAGS_TSYN		BIT(8)
275253 #define I40E_TX_FLAGS_FD_SB		BIT(9)
276254 #define I40E_TX_FLAGS_UDP_TUNNEL	BIT(10)
....@@ -297,11 +275,7 @@
297275 struct i40e_rx_buffer {
298276 	dma_addr_t dma;
299277 	struct page *page;
300
-#if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
301278 	__u32 page_offset;
302
-#else
303
-	__u16 page_offset;
304
-#endif
305279 	__u16 pagecnt_bias;
306280 };
307281 
....@@ -336,9 +310,7 @@
336310 /* some useful defines for virtchannel interface, which
337311  * is the only remaining user of header split
338312  */
339
-#define I40E_RX_DTYPE_NO_SPLIT      0
340313 #define I40E_RX_DTYPE_HEADER_SPLIT  1
341
-#define I40E_RX_DTYPE_SPLIT_ALWAYS  2
342314 #define I40E_RX_SPLIT_L2      0x1
343315 #define I40E_RX_SPLIT_IP      0x2
344316 #define I40E_RX_SPLIT_TCP_UDP 0x4
....@@ -354,6 +326,7 @@
354326 	union {
355327 		struct i40e_tx_buffer *tx_bi;
356328 		struct i40e_rx_buffer *rx_bi;
329
+		struct xdp_buff **rx_bi_zc;
357330 	};
358331 	DECLARE_BITMAP(state, __I40E_RING_STATE_NBITS);
359332 	u16 queue_index;		/* Queue number of ring */
....@@ -374,6 +347,7 @@
374347 	/* used in interrupt processing */
375348 	u16 next_to_use;
376349 	u16 next_to_clean;
350
+	u16 xdp_tx_active;
377351 
378352 	u8 atr_sample_rate;
379353 	u8 atr_count;
....@@ -414,6 +388,7 @@
414388 
415389 	struct i40e_channel *ch;
416390 	struct xdp_rxq_info xdp_rxq;
391
+	struct xsk_buff_pool *xsk_pool;
417392 } ____cacheline_internodealigned_in_smp;
418393 
419394 static inline bool ring_uses_build_skb(struct i40e_ring *ring)
....@@ -446,7 +421,6 @@
446421 #define I40E_ITR_ADAPTIVE_MAX_USECS	0x007e
447422 #define I40E_ITR_ADAPTIVE_LATENCY	0x8000
448423 #define I40E_ITR_ADAPTIVE_BULK		0x0000
449
-#define ITR_IS_BULK(x) (!((x) & I40E_ITR_ADAPTIVE_LATENCY))
450424 
451425 struct i40e_ring_container {
452426 	struct i40e_ring *ring;		/* pointer to linked list of ring(s) */
....@@ -475,6 +449,8 @@
475449 
476450 bool i40e_alloc_rx_buffers(struct i40e_ring *rxr, u16 cleaned_count);
477451 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
452
+u16 i40e_lan_select_queue(struct net_device *netdev, struct sk_buff *skb,
453
+			  struct net_device *sb_dev);
478454 void i40e_clean_tx_ring(struct i40e_ring *tx_ring);
479455 void i40e_clean_rx_ring(struct i40e_ring *rx_ring);
480456 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring);
....@@ -507,7 +483,6 @@
507483 /**
508484  * i40e_xmit_descriptor_count - calculate number of Tx descriptors needed
509485  * @skb:     send buffer
510
- * @tx_ring: ring to send buffer on
511486  *
512487  * Returns number of data descriptors needed for this skb. Returns 0 to indicate
513488  * there is not enough descriptors available in this ring since we need at least
....@@ -515,7 +490,7 @@
515490  **/
516491 static inline int i40e_xmit_descriptor_count(struct sk_buff *skb)
517492 {
518
-	const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
493
+	const skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
519494 	unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
520495 	int count = 0, size = skb_headlen(skb);
521496