kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/drivers/net/ethernet/intel/i40e/i40e_register.h
..
..
@@ -4,53 +4,14 @@
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 #ifndef _I40E_REGISTER_H_
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 #define _I40E_REGISTER_H_
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-#define I40E_GL_ARQBAH 0x000801C0 /* Reset: EMPR */
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-#define I40E_GL_ARQBAH_ARQBAH_SHIFT 0
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-#define I40E_GL_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ARQBAH_ARQBAH_SHIFT)
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-#define I40E_GL_ARQBAL 0x000800C0 /* Reset: EMPR */
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-#define I40E_GL_ARQBAL_ARQBAL_SHIFT 0
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-#define I40E_GL_ARQBAL_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ARQBAL_ARQBAL_SHIFT)
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-#define I40E_GL_ARQH 0x000803C0 /* Reset: EMPR */
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-#define I40E_GL_ARQH_ARQH_SHIFT 0
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-#define I40E_GL_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_GL_ARQH_ARQH_SHIFT)
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-#define I40E_GL_ARQT 0x000804C0 /* Reset: EMPR */
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-#define I40E_GL_ARQT_ARQT_SHIFT 0
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-#define I40E_GL_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_GL_ARQT_ARQT_SHIFT)
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-#define I40E_GL_ATQBAH 0x00080140 /* Reset: EMPR */
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-#define I40E_GL_ATQBAH_ATQBAH_SHIFT 0
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-#define I40E_GL_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ATQBAH_ATQBAH_SHIFT)
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-#define I40E_GL_ATQBAL 0x00080040 /* Reset: EMPR */
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-#define I40E_GL_ATQBAL_ATQBAL_SHIFT 0
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-#define I40E_GL_ATQBAL_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ATQBAL_ATQBAL_SHIFT)
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-#define I40E_GL_ATQH 0x00080340 /* Reset: EMPR */
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-#define I40E_GL_ATQH_ATQH_SHIFT 0
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-#define I40E_GL_ATQH_ATQH_MASK I40E_MASK(0x3FF, I40E_GL_ATQH_ATQH_SHIFT)
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-#define I40E_GL_ATQLEN 0x00080240 /* Reset: EMPR */
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-#define I40E_GL_ATQLEN_ATQLEN_SHIFT 0
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-#define I40E_GL_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_GL_ATQLEN_ATQLEN_SHIFT)
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-#define I40E_GL_ATQLEN_ATQVFE_SHIFT 28
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-#define I40E_GL_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQVFE_SHIFT)
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-#define I40E_GL_ATQLEN_ATQOVFL_SHIFT 29
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-#define I40E_GL_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQOVFL_SHIFT)
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 #define I40E_GL_ATQLEN_ATQCRIT_SHIFT 30
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 #define I40E_GL_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQCRIT_SHIFT)
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-#define I40E_GL_ATQLEN_ATQENABLE_SHIFT 31
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-#define I40E_GL_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQENABLE_SHIFT)
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-#define I40E_GL_ATQT 0x00080440 /* Reset: EMPR */
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-#define I40E_GL_ATQT_ATQT_SHIFT 0
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-#define I40E_GL_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_GL_ATQT_ATQT_SHIFT)
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 #define I40E_PF_ARQBAH 0x00080180 /* Reset: EMPR */
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-#define I40E_PF_ARQBAH_ARQBAH_SHIFT 0
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-#define I40E_PF_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ARQBAH_ARQBAH_SHIFT)
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 #define I40E_PF_ARQBAL 0x00080080 /* Reset: EMPR */
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-#define I40E_PF_ARQBAL_ARQBAL_SHIFT 0
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-#define I40E_PF_ARQBAL_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ARQBAL_ARQBAL_SHIFT)
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 #define I40E_PF_ARQH 0x00080380 /* Reset: EMPR */
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 #define I40E_PF_ARQH_ARQH_SHIFT 0
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 #define I40E_PF_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_PF_ARQH_ARQH_SHIFT)
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 #define I40E_PF_ARQLEN 0x00080280 /* Reset: EMPR */
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-#define I40E_PF_ARQLEN_ARQLEN_SHIFT 0
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-#define I40E_PF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ARQLEN_ARQLEN_SHIFT)
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 #define I40E_PF_ARQLEN_ARQVFE_SHIFT 28
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 #define I40E_PF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQVFE_SHIFT)
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 #define I40E_PF_ARQLEN_ARQOVFL_SHIFT 29
..
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@@ -58,22 +19,12 @@
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 #define I40E_PF_ARQLEN_ARQCRIT_SHIFT 30
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 #define I40E_PF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQCRIT_SHIFT)
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 #define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31
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-#define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQENABLE_SHIFT)
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+#define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ARQLEN_ARQENABLE_SHIFT)
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 #define I40E_PF_ARQT 0x00080480 /* Reset: EMPR */
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-#define I40E_PF_ARQT_ARQT_SHIFT 0
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-#define I40E_PF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_PF_ARQT_ARQT_SHIFT)
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 #define I40E_PF_ATQBAH 0x00080100 /* Reset: EMPR */
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-#define I40E_PF_ATQBAH_ATQBAH_SHIFT 0
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-#define I40E_PF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAH_ATQBAH_SHIFT)
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 #define I40E_PF_ATQBAL 0x00080000 /* Reset: EMPR */
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-#define I40E_PF_ATQBAL_ATQBAL_SHIFT 0
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-#define I40E_PF_ATQBAL_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAL_ATQBAL_SHIFT)
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 #define I40E_PF_ATQH 0x00080300 /* Reset: EMPR */
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-#define I40E_PF_ATQH_ATQH_SHIFT 0
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-#define I40E_PF_ATQH_ATQH_MASK I40E_MASK(0x3FF, I40E_PF_ATQH_ATQH_SHIFT)
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 #define I40E_PF_ATQLEN 0x00080200 /* Reset: EMPR */
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-#define I40E_PF_ATQLEN_ATQLEN_SHIFT 0
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-#define I40E_PF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ATQLEN_ATQLEN_SHIFT)
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 #define I40E_PF_ATQLEN_ATQVFE_SHIFT 28
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 #define I40E_PF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQVFE_SHIFT)
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 #define I40E_PF_ATQLEN_ATQOVFL_SHIFT 29
..
..
@@ -81,782 +32,143 @@
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 #define I40E_PF_ATQLEN_ATQCRIT_SHIFT 30
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 #define I40E_PF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQCRIT_SHIFT)
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 #define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31
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-#define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQENABLE_SHIFT)
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+#define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ATQLEN_ATQENABLE_SHIFT)
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 #define I40E_PF_ATQT 0x00080400 /* Reset: EMPR */
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-#define I40E_PF_ATQT_ATQT_SHIFT 0
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-#define I40E_PF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_PF_ATQT_ATQT_SHIFT)
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-#define I40E_VF_ARQBAH(_VF) (0x00081400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
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-#define I40E_VF_ARQBAH_MAX_INDEX 127
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-#define I40E_VF_ARQBAH_ARQBAH_SHIFT 0
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-#define I40E_VF_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH_ARQBAH_SHIFT)
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-#define I40E_VF_ARQBAL(_VF) (0x00080C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
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-#define I40E_VF_ARQBAL_MAX_INDEX 127
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-#define I40E_VF_ARQBAL_ARQBAL_SHIFT 0
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-#define I40E_VF_ARQBAL_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAL_ARQBAL_SHIFT)
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-#define I40E_VF_ARQH(_VF) (0x00082400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
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-#define I40E_VF_ARQH_MAX_INDEX 127
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-#define I40E_VF_ARQH_ARQH_SHIFT 0
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-#define I40E_VF_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_VF_ARQH_ARQH_SHIFT)
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-#define I40E_VF_ARQLEN(_VF) (0x00081C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
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-#define I40E_VF_ARQLEN_MAX_INDEX 127
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-#define I40E_VF_ARQLEN_ARQLEN_SHIFT 0
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-#define I40E_VF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN_ARQLEN_SHIFT)
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-#define I40E_VF_ARQLEN_ARQVFE_SHIFT 28
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-#define I40E_VF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQVFE_SHIFT)
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-#define I40E_VF_ARQLEN_ARQOVFL_SHIFT 29
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-#define I40E_VF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQOVFL_SHIFT)
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-#define I40E_VF_ARQLEN_ARQCRIT_SHIFT 30
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-#define I40E_VF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQCRIT_SHIFT)
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-#define I40E_VF_ARQLEN_ARQENABLE_SHIFT 31
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-#define I40E_VF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQENABLE_SHIFT)
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-#define I40E_VF_ARQT(_VF) (0x00082C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
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-#define I40E_VF_ARQT_MAX_INDEX 127
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-#define I40E_VF_ARQT_ARQT_SHIFT 0
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-#define I40E_VF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT_ARQT_SHIFT)
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-#define I40E_VF_ATQBAH(_VF) (0x00081000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
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-#define I40E_VF_ATQBAH_MAX_INDEX 127
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-#define I40E_VF_ATQBAH_ATQBAH_SHIFT 0
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-#define I40E_VF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH_ATQBAH_SHIFT)
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-#define I40E_VF_ATQBAL(_VF) (0x00080800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
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-#define I40E_VF_ATQBAL_MAX_INDEX 127
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-#define I40E_VF_ATQBAL_ATQBAL_SHIFT 0
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-#define I40E_VF_ATQBAL_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL_ATQBAL_SHIFT)
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-#define I40E_VF_ATQH(_VF) (0x00082000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
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-#define I40E_VF_ATQH_MAX_INDEX 127
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-#define I40E_VF_ATQH_ATQH_SHIFT 0
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-#define I40E_VF_ATQH_ATQH_MASK I40E_MASK(0x3FF, I40E_VF_ATQH_ATQH_SHIFT)
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-#define I40E_VF_ATQLEN(_VF) (0x00081800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
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-#define I40E_VF_ATQLEN_MAX_INDEX 127
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-#define I40E_VF_ATQLEN_ATQLEN_SHIFT 0
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-#define I40E_VF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN_ATQLEN_SHIFT)
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-#define I40E_VF_ATQLEN_ATQVFE_SHIFT 28
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-#define I40E_VF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQVFE_SHIFT)
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-#define I40E_VF_ATQLEN_ATQOVFL_SHIFT 29
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-#define I40E_VF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQOVFL_SHIFT)
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-#define I40E_VF_ATQLEN_ATQCRIT_SHIFT 30
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-#define I40E_VF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQCRIT_SHIFT)
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-#define I40E_VF_ATQLEN_ATQENABLE_SHIFT 31
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-#define I40E_VF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQENABLE_SHIFT)
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-#define I40E_VF_ATQT(_VF) (0x00082800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
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-#define I40E_VF_ATQT_MAX_INDEX 127
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-#define I40E_VF_ATQT_ATQT_SHIFT 0
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-#define I40E_VF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT_ATQT_SHIFT)
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-#define I40E_PRT_L2TAGSEN 0x001C0B20 /* Reset: CORER */
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-#define I40E_PRT_L2TAGSEN_ENABLE_SHIFT 0
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-#define I40E_PRT_L2TAGSEN_ENABLE_MASK I40E_MASK(0xFF, I40E_PRT_L2TAGSEN_ENABLE_SHIFT)
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-#define I40E_PFCM_LAN_ERRDATA 0x0010C080 /* Reset: PFR */
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-#define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT 0
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-#define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT)
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-#define I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT 4
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-#define I40E_PFCM_LAN_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT)
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-#define I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT 8
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-#define I40E_PFCM_LAN_ERRDATA_Q_NUM_MASK I40E_MASK(0xFFF, I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT)
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-#define I40E_PFCM_LAN_ERRINFO 0x0010C000 /* Reset: PFR */
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-#define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT 0
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-#define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1, I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT)
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-#define I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT 4
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-#define I40E_PFCM_LAN_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT)
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-#define I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_SHIFT 8
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-#define I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_SHIFT)
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-#define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT 16
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-#define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT)
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-#define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT 24
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-#define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT)
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-#define I40E_PFCM_LANCTXCTL 0x0010C300 /* Reset: CORER */
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-#define I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT 0
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-#define I40E_PFCM_LANCTXCTL_QUEUE_NUM_MASK I40E_MASK(0xFFF, I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT)
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-#define I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT 12
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-#define I40E_PFCM_LANCTXCTL_SUB_LINE_MASK I40E_MASK(0x7, I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT)
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-#define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT 15
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-#define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_MASK I40E_MASK(0x3, I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT)
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-#define I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT 17
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-#define I40E_PFCM_LANCTXCTL_OP_CODE_MASK I40E_MASK(0x3, I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT)
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-#define I40E_PFCM_LANCTXDATA(_i) (0x0010C100 + ((_i) * 128)) /* _i=0...3 */ /* Reset: CORER */
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-#define I40E_PFCM_LANCTXDATA_MAX_INDEX 3
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-#define I40E_PFCM_LANCTXDATA_DATA_SHIFT 0
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-#define I40E_PFCM_LANCTXDATA_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_PFCM_LANCTXDATA_DATA_SHIFT)
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-#define I40E_PFCM_LANCTXSTAT 0x0010C380 /* Reset: CORER */
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-#define I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT 0
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-#define I40E_PFCM_LANCTXSTAT_CTX_DONE_MASK I40E_MASK(0x1, I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT)
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-#define I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT 1
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-#define I40E_PFCM_LANCTXSTAT_CTX_MISS_MASK I40E_MASK(0x1, I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT)
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-#define I40E_VFCM_PE_ERRDATA1(_VF) (0x00138800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
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-#define I40E_VFCM_PE_ERRDATA1_MAX_INDEX 127
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-#define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT 0
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-#define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_MASK I40E_MASK(0xF, I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT)
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-#define I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT 4
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-#define I40E_VFCM_PE_ERRDATA1_Q_TYPE_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT)
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-#define I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT 8
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-#define I40E_VFCM_PE_ERRDATA1_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT)
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-#define I40E_VFCM_PE_ERRINFO1(_VF) (0x00138400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
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-#define I40E_VFCM_PE_ERRINFO1_MAX_INDEX 127
193
-#define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT 0
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-#define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_MASK I40E_MASK(0x1, I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT)
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-#define I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT 4
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-#define I40E_VFCM_PE_ERRINFO1_ERROR_INST_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT)
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-#define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT 8
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-#define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT)
199
-#define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT 16
200
-#define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT)
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-#define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT 24
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-#define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT)
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-#define I40E_GLDCB_GENC 0x00083044 /* Reset: CORER */
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-#define I40E_GLDCB_GENC_PCIRTT_SHIFT 0
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-#define I40E_GLDCB_GENC_PCIRTT_MASK I40E_MASK(0xFFFF, I40E_GLDCB_GENC_PCIRTT_SHIFT)
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-#define I40E_GLDCB_RUPTI 0x00122618 /* Reset: CORER */
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-#define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT 0
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-#define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT)
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-#define I40E_PRTDCB_FCCFG 0x001E4640 /* Reset: GLOBR */
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-#define I40E_PRTDCB_FCCFG_TFCE_SHIFT 3
211
-#define I40E_PRTDCB_FCCFG_TFCE_MASK I40E_MASK(0x3, I40E_PRTDCB_FCCFG_TFCE_SHIFT)
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-#define I40E_PRTDCB_FCRTV 0x001E4600 /* Reset: GLOBR */
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-#define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT 0
214
-#define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT)
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-#define I40E_PRTDCB_FCTTVN(_i) (0x001E4580 + ((_i) * 32)) /* _i=0...3 */ /* Reset: GLOBR */
216
-#define I40E_PRTDCB_FCTTVN_MAX_INDEX 3
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-#define I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT 0
218
-#define I40E_PRTDCB_FCTTVN_TTV_2N_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT)
219
-#define I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT 16
220
-#define I40E_PRTDCB_FCTTVN_TTV_2N_P1_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT)
221
37
 #define I40E_PRTDCB_GENC 0x00083000 /* Reset: CORER */
222
-#define I40E_PRTDCB_GENC_RESERVED_1_SHIFT 0
223
-#define I40E_PRTDCB_GENC_RESERVED_1_MASK I40E_MASK(0x3, I40E_PRTDCB_GENC_RESERVED_1_SHIFT)
224
-#define I40E_PRTDCB_GENC_NUMTC_SHIFT 2
225
-#define I40E_PRTDCB_GENC_NUMTC_MASK I40E_MASK(0xF, I40E_PRTDCB_GENC_NUMTC_SHIFT)
226
-#define I40E_PRTDCB_GENC_FCOEUP_SHIFT 6
227
-#define I40E_PRTDCB_GENC_FCOEUP_MASK I40E_MASK(0x7, I40E_PRTDCB_GENC_FCOEUP_SHIFT)
228
-#define I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT 9
229
-#define I40E_PRTDCB_GENC_FCOEUP_VALID_MASK I40E_MASK(0x1, I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT)
230
38
 #define I40E_PRTDCB_GENC_PFCLDA_SHIFT 16
231
39
 #define I40E_PRTDCB_GENC_PFCLDA_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_GENC_PFCLDA_SHIFT)
232
40
 #define I40E_PRTDCB_GENS 0x00083020 /* Reset: CORER */
233
41
 #define I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT 0
234
42
 #define I40E_PRTDCB_GENS_DCBX_STATUS_MASK I40E_MASK(0x7, I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT)
235
-#define I40E_PRTDCB_MFLCN 0x001E2400 /* Reset: GLOBR */
236
-#define I40E_PRTDCB_MFLCN_PMCF_SHIFT 0
237
-#define I40E_PRTDCB_MFLCN_PMCF_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_PMCF_SHIFT)
238
-#define I40E_PRTDCB_MFLCN_DPF_SHIFT 1
239
-#define I40E_PRTDCB_MFLCN_DPF_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_DPF_SHIFT)
240
-#define I40E_PRTDCB_MFLCN_RPFCM_SHIFT 2
241
-#define I40E_PRTDCB_MFLCN_RPFCM_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_RPFCM_SHIFT)
242
-#define I40E_PRTDCB_MFLCN_RFCE_SHIFT 3
243
-#define I40E_PRTDCB_MFLCN_RFCE_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_RFCE_SHIFT)
244
-#define I40E_PRTDCB_MFLCN_RPFCE_SHIFT 4
245
-#define I40E_PRTDCB_MFLCN_RPFCE_MASK I40E_MASK(0xFF, I40E_PRTDCB_MFLCN_RPFCE_SHIFT)
246
-#define I40E_PRTDCB_RETSC 0x001223E0 /* Reset: CORER */
247
-#define I40E_PRTDCB_RETSC_ETS_MODE_SHIFT 0
248
-#define I40E_PRTDCB_RETSC_ETS_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSC_ETS_MODE_SHIFT)
249
-#define I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT 1
250
-#define I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT)
251
-#define I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT 2
252
-#define I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK I40E_MASK(0xF, I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT)
253
-#define I40E_PRTDCB_RETSC_LLTC_SHIFT 8
254
-#define I40E_PRTDCB_RETSC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_RETSC_LLTC_SHIFT)
255
-#define I40E_PRTDCB_RETSTCC(_i) (0x00122180 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
256
-#define I40E_PRTDCB_RETSTCC_MAX_INDEX 7
257
-#define I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT 0
258
-#define I40E_PRTDCB_RETSTCC_BWSHARE_MASK I40E_MASK(0x7F, I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT)
259
-#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT 30
260
-#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT)
261
-#define I40E_PRTDCB_RETSTCC_ETSTC_SHIFT 31
262
-#define I40E_PRTDCB_RETSTCC_ETSTC_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_ETSTC_SHIFT)
263
-#define I40E_PRTDCB_RPPMC 0x001223A0 /* Reset: CORER */
264
-#define I40E_PRTDCB_RPPMC_LANRPPM_SHIFT 0
265
-#define I40E_PRTDCB_RPPMC_LANRPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_LANRPPM_SHIFT)
266
-#define I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT 8
267
-#define I40E_PRTDCB_RPPMC_RDMARPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT)
268
-#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT 16
269
-#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT)
270
-#define I40E_PRTDCB_RUP 0x001C0B00 /* Reset: CORER */
271
-#define I40E_PRTDCB_RUP_NOVLANUP_SHIFT 0
272
-#define I40E_PRTDCB_RUP_NOVLANUP_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP_NOVLANUP_SHIFT)
273
-#define I40E_PRTDCB_RUP2TC 0x001C09A0 /* Reset: CORER */
274
-#define I40E_PRTDCB_RUP2TC_UP0TC_SHIFT 0
275
-#define I40E_PRTDCB_RUP2TC_UP0TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP0TC_SHIFT)
276
-#define I40E_PRTDCB_RUP2TC_UP1TC_SHIFT 3
277
-#define I40E_PRTDCB_RUP2TC_UP1TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP1TC_SHIFT)
278
-#define I40E_PRTDCB_RUP2TC_UP2TC_SHIFT 6
279
-#define I40E_PRTDCB_RUP2TC_UP2TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP2TC_SHIFT)
280
-#define I40E_PRTDCB_RUP2TC_UP3TC_SHIFT 9
281
-#define I40E_PRTDCB_RUP2TC_UP3TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP3TC_SHIFT)
282
-#define I40E_PRTDCB_RUP2TC_UP4TC_SHIFT 12
283
-#define I40E_PRTDCB_RUP2TC_UP4TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP4TC_SHIFT)
284
-#define I40E_PRTDCB_RUP2TC_UP5TC_SHIFT 15
285
-#define I40E_PRTDCB_RUP2TC_UP5TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP5TC_SHIFT)
286
-#define I40E_PRTDCB_RUP2TC_UP6TC_SHIFT 18
287
-#define I40E_PRTDCB_RUP2TC_UP6TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP6TC_SHIFT)
288
-#define I40E_PRTDCB_RUP2TC_UP7TC_SHIFT 21
289
-#define I40E_PRTDCB_RUP2TC_UP7TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP7TC_SHIFT)
290
-#define I40E_PRTDCB_RUPTQ(_i) (0x00122400 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
291
-#define I40E_PRTDCB_RUPTQ_MAX_INDEX 7
292
-#define I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT 0
293
-#define I40E_PRTDCB_RUPTQ_RXQNUM_MASK I40E_MASK(0x3FFF, I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT)
294
-#define I40E_PRTDCB_TC2PFC 0x001C0980 /* Reset: CORER */
295
-#define I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT 0
296
-#define I40E_PRTDCB_TC2PFC_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT)
297
-#define I40E_PRTDCB_TCMSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
298
-#define I40E_PRTDCB_TCMSTC_MAX_INDEX 7
299
-#define I40E_PRTDCB_TCMSTC_MSTC_SHIFT 0
300
-#define I40E_PRTDCB_TCMSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCMSTC_MSTC_SHIFT)
301
-#define I40E_PRTDCB_TCPMC 0x000A21A0 /* Reset: CORER */
302
-#define I40E_PRTDCB_TCPMC_CPM_SHIFT 0
303
-#define I40E_PRTDCB_TCPMC_CPM_MASK I40E_MASK(0x1FFF, I40E_PRTDCB_TCPMC_CPM_SHIFT)
304
-#define I40E_PRTDCB_TCPMC_LLTC_SHIFT 13
305
-#define I40E_PRTDCB_TCPMC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TCPMC_LLTC_SHIFT)
306
-#define I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT 30
307
-#define I40E_PRTDCB_TCPMC_TCPM_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT)
308
-#define I40E_PRTDCB_TCWSTC(_i) (0x000A2040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
309
-#define I40E_PRTDCB_TCWSTC_MAX_INDEX 7
310
-#define I40E_PRTDCB_TCWSTC_MSTC_SHIFT 0
311
-#define I40E_PRTDCB_TCWSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCWSTC_MSTC_SHIFT)
312
-#define I40E_PRTDCB_TDPMC 0x000A0180 /* Reset: CORER */
313
-#define I40E_PRTDCB_TDPMC_DPM_SHIFT 0
314
-#define I40E_PRTDCB_TDPMC_DPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_TDPMC_DPM_SHIFT)
315
-#define I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT 30
316
-#define I40E_PRTDCB_TDPMC_TCPM_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT)
317
-#define I40E_PRTDCB_TETSC_TCB 0x000AE060 /* Reset: CORER */
318
-#define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT 0
319
-#define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_MASK I40E_MASK(0x1, I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT)
320
-#define I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT 8
321
-#define I40E_PRTDCB_TETSC_TCB_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT)
322
-#define I40E_PRTDCB_TETSC_TPB 0x00098060 /* Reset: CORER */
323
-#define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT 0
324
-#define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_MASK I40E_MASK(0x1, I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT)
325
-#define I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT 8
326
-#define I40E_PRTDCB_TETSC_TPB_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT)
327
-#define I40E_PRTDCB_TFCS 0x001E4560 /* Reset: GLOBR */
328
-#define I40E_PRTDCB_TFCS_TXOFF_SHIFT 0
329
-#define I40E_PRTDCB_TFCS_TXOFF_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF_SHIFT)
330
-#define I40E_PRTDCB_TFCS_TXOFF0_SHIFT 8
331
-#define I40E_PRTDCB_TFCS_TXOFF0_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF0_SHIFT)
332
-#define I40E_PRTDCB_TFCS_TXOFF1_SHIFT 9
333
-#define I40E_PRTDCB_TFCS_TXOFF1_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF1_SHIFT)
334
-#define I40E_PRTDCB_TFCS_TXOFF2_SHIFT 10
335
-#define I40E_PRTDCB_TFCS_TXOFF2_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF2_SHIFT)
336
-#define I40E_PRTDCB_TFCS_TXOFF3_SHIFT 11
337
-#define I40E_PRTDCB_TFCS_TXOFF3_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF3_SHIFT)
338
-#define I40E_PRTDCB_TFCS_TXOFF4_SHIFT 12
339
-#define I40E_PRTDCB_TFCS_TXOFF4_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF4_SHIFT)
340
-#define I40E_PRTDCB_TFCS_TXOFF5_SHIFT 13
341
-#define I40E_PRTDCB_TFCS_TXOFF5_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF5_SHIFT)
342
-#define I40E_PRTDCB_TFCS_TXOFF6_SHIFT 14
343
-#define I40E_PRTDCB_TFCS_TXOFF6_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF6_SHIFT)
344
-#define I40E_PRTDCB_TFCS_TXOFF7_SHIFT 15
345
-#define I40E_PRTDCB_TFCS_TXOFF7_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF7_SHIFT)
346
-#define I40E_PRTDCB_TPFCTS(_i) (0x001E4660 + ((_i) * 32)) /* _i=0...7 */ /* Reset: GLOBR */
347
-#define I40E_PRTDCB_TPFCTS_MAX_INDEX 7
348
-#define I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT 0
349
-#define I40E_PRTDCB_TPFCTS_PFCTIMER_MASK I40E_MASK(0x3FFF, I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT)
350
-#define I40E_GLFCOE_RCTL 0x00269B94 /* Reset: CORER */
351
-#define I40E_GLFCOE_RCTL_FCOEVER_SHIFT 0
352
-#define I40E_GLFCOE_RCTL_FCOEVER_MASK I40E_MASK(0xF, I40E_GLFCOE_RCTL_FCOEVER_SHIFT)
353
-#define I40E_GLFCOE_RCTL_SAVBAD_SHIFT 4
354
-#define I40E_GLFCOE_RCTL_SAVBAD_MASK I40E_MASK(0x1, I40E_GLFCOE_RCTL_SAVBAD_SHIFT)
355
-#define I40E_GLFCOE_RCTL_ICRC_SHIFT 5
356
-#define I40E_GLFCOE_RCTL_ICRC_MASK I40E_MASK(0x1, I40E_GLFCOE_RCTL_ICRC_SHIFT)
357
-#define I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT 16
358
-#define I40E_GLFCOE_RCTL_MAX_SIZE_MASK I40E_MASK(0x3FFF, I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT)
359
43
 #define I40E_GL_FWSTS 0x00083048 /* Reset: POR */
360
-#define I40E_GL_FWSTS_FWS0B_SHIFT 0
361
-#define I40E_GL_FWSTS_FWS0B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS0B_SHIFT)
362
-#define I40E_GL_FWSTS_FWRI_SHIFT 9
363
-#define I40E_GL_FWSTS_FWRI_MASK I40E_MASK(0x1, I40E_GL_FWSTS_FWRI_SHIFT)
364
44
 #define I40E_GL_FWSTS_FWS1B_SHIFT 16
365
45
 #define I40E_GL_FWSTS_FWS1B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS1B_SHIFT)
366
-#define I40E_GLGEN_CLKSTAT 0x000B8184 /* Reset: POR */
367
-#define I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT 0
368
-#define I40E_GLGEN_CLKSTAT_CLKMODE_MASK I40E_MASK(0x1, I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT)
369
-#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT 4
370
-#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_MASK I40E_MASK(0x3, I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT)
371
-#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT 8
372
-#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT)
373
-#define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT 12
374
-#define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT)
375
-#define I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT 16
376
-#define I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT)
377
-#define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT 20
378
-#define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT)
46
+#define I40E_GL_FWSTS_FWS1B_EMPR_0 I40E_MASK(0x20, I40E_GL_FWSTS_FWS1B_SHIFT)
47
+#define I40E_GL_FWSTS_FWS1B_EMPR_10 I40E_MASK(0x2A, I40E_GL_FWSTS_FWS1B_SHIFT)
48
+#define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK I40E_MASK(0x30, I40E_GL_FWSTS_FWS1B_SHIFT)
49
+#define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK I40E_MASK(0x31, I40E_GL_FWSTS_FWS1B_SHIFT)
50
+#define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_TRANSITION_MASK I40E_MASK(0x32, I40E_GL_FWSTS_FWS1B_SHIFT)
51
+#define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_NVM_MASK I40E_MASK(0x33, I40E_GL_FWSTS_FWS1B_SHIFT)
52
+#define I40E_X722_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK I40E_MASK(0xB, I40E_GL_FWSTS_FWS1B_SHIFT)
53
+#define I40E_X722_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK I40E_MASK(0xC, I40E_GL_FWSTS_FWS1B_SHIFT)
379
54
 #define I40E_GLGEN_GPIO_CTL(_i) (0x00088100 + ((_i) * 4)) /* _i=0...29 */ /* Reset: POR */
380
55
 #define I40E_GLGEN_GPIO_CTL_MAX_INDEX 29
381
56
 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT 0
382
57
 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
383
58
 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT 3
384
59
 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT)
385
-#define I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT 4
386
-#define I40E_GLGEN_GPIO_CTL_PIN_DIR_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT)
387
-#define I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT 5
388
-#define I40E_GLGEN_GPIO_CTL_TRI_CTL_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT)
389
-#define I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT 6
390
-#define I40E_GLGEN_GPIO_CTL_OUT_CTL_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT)
391
60
 #define I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT 7
392
61
 #define I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK I40E_MASK(0x7, I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
393
-#define I40E_GLGEN_GPIO_CTL_LED_INVRT_SHIFT 10
394
-#define I40E_GLGEN_GPIO_CTL_LED_INVRT_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_LED_INVRT_SHIFT)
395
62
 #define I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT 11
396
-#define I40E_GLGEN_GPIO_CTL_LED_BLINK_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT)
397
63
 #define I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT 12
398
64
 #define I40E_GLGEN_GPIO_CTL_LED_MODE_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
399
-#define I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT 17
400
-#define I40E_GLGEN_GPIO_CTL_INT_MODE_MASK I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT)
401
-#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT 19
402
-#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT)
403
-#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT 20
404
-#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_MASK I40E_MASK(0x3F, I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT)
405
-#define I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_SHIFT 26
406
-#define I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_MASK I40E_MASK(0xF, I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_SHIFT)
407
-#define I40E_GLGEN_GPIO_SET 0x00088184 /* Reset: POR */
408
-#define I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT 0
409
-#define I40E_GLGEN_GPIO_SET_GPIO_INDX_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT)
410
-#define I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT 5
411
-#define I40E_GLGEN_GPIO_SET_SDP_DATA_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT)
412
-#define I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT 6
413
-#define I40E_GLGEN_GPIO_SET_DRIVE_SDP_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT)
414
-#define I40E_GLGEN_GPIO_STAT 0x0008817C /* Reset: POR */
415
-#define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT 0
416
-#define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_MASK I40E_MASK(0x3FFFFFFF, I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT)
417
-#define I40E_GLGEN_GPIO_TRANSIT 0x00088180 /* Reset: POR */
418
-#define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT 0
419
-#define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_MASK I40E_MASK(0x3FFFFFFF, I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT)
420
-#define I40E_GLGEN_I2CCMD(_i) (0x000881E0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
421
-#define I40E_GLGEN_I2CCMD_MAX_INDEX 3
422
-#define I40E_GLGEN_I2CCMD_DATA_SHIFT 0
423
-#define I40E_GLGEN_I2CCMD_DATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_I2CCMD_DATA_SHIFT)
424
-#define I40E_GLGEN_I2CCMD_REGADD_SHIFT 16
425
-#define I40E_GLGEN_I2CCMD_REGADD_MASK I40E_MASK(0xFF, I40E_GLGEN_I2CCMD_REGADD_SHIFT)
426
-#define I40E_GLGEN_I2CCMD_PHYADD_SHIFT 24
427
-#define I40E_GLGEN_I2CCMD_PHYADD_MASK I40E_MASK(0x7, I40E_GLGEN_I2CCMD_PHYADD_SHIFT)
428
-#define I40E_GLGEN_I2CCMD_OP_SHIFT 27
429
-#define I40E_GLGEN_I2CCMD_OP_MASK I40E_MASK(0x1, I40E_GLGEN_I2CCMD_OP_SHIFT)
430
-#define I40E_GLGEN_I2CCMD_RESET_SHIFT 28
431
-#define I40E_GLGEN_I2CCMD_RESET_MASK I40E_MASK(0x1, I40E_GLGEN_I2CCMD_RESET_SHIFT)
432
-#define I40E_GLGEN_I2CCMD_R_SHIFT 29
433
-#define I40E_GLGEN_I2CCMD_R_MASK I40E_MASK(0x1, I40E_GLGEN_I2CCMD_R_SHIFT)
434
-#define I40E_GLGEN_I2CCMD_E_SHIFT 31
435
-#define I40E_GLGEN_I2CCMD_E_MASK I40E_MASK(0x1, I40E_GLGEN_I2CCMD_E_SHIFT)
436
-#define I40E_GLGEN_I2CPARAMS(_i) (0x000881AC + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
437
-#define I40E_GLGEN_I2CPARAMS_MAX_INDEX 3
438
-#define I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT 0
439
-#define I40E_GLGEN_I2CPARAMS_WRITE_TIME_MASK I40E_MASK(0x1F, I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT)
440
-#define I40E_GLGEN_I2CPARAMS_READ_TIME_SHIFT 5
441
-#define I40E_GLGEN_I2CPARAMS_READ_TIME_MASK I40E_MASK(0x7, I40E_GLGEN_I2CPARAMS_READ_TIME_SHIFT)
442
-#define I40E_GLGEN_I2CPARAMS_I2CBB_EN_SHIFT 8
443
-#define I40E_GLGEN_I2CPARAMS_I2CBB_EN_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_I2CBB_EN_SHIFT)
444
-#define I40E_GLGEN_I2CPARAMS_CLK_SHIFT 9
445
-#define I40E_GLGEN_I2CPARAMS_CLK_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_SHIFT)
446
-#define I40E_GLGEN_I2CPARAMS_DATA_OUT_SHIFT 10
447
-#define I40E_GLGEN_I2CPARAMS_DATA_OUT_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_DATA_OUT_SHIFT)
448
-#define I40E_GLGEN_I2CPARAMS_DATA_OE_N_SHIFT 11
449
-#define I40E_GLGEN_I2CPARAMS_DATA_OE_N_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_DATA_OE_N_SHIFT)
450
-#define I40E_GLGEN_I2CPARAMS_DATA_IN_SHIFT 12
451
-#define I40E_GLGEN_I2CPARAMS_DATA_IN_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_DATA_IN_SHIFT)
452
-#define I40E_GLGEN_I2CPARAMS_CLK_OE_N_SHIFT 13
453
-#define I40E_GLGEN_I2CPARAMS_CLK_OE_N_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_OE_N_SHIFT)
454
-#define I40E_GLGEN_I2CPARAMS_CLK_IN_SHIFT 14
455
-#define I40E_GLGEN_I2CPARAMS_CLK_IN_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_IN_SHIFT)
456
-#define I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT 15
457
-#define I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT)
458
-#define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT 31
459
-#define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT)
460
-#define I40E_GLGEN_LED_CTL 0x00088178 /* Reset: POR */
461
-#define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT 0
462
-#define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_MASK I40E_MASK(0x1, I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT)
463
-#define I40E_GLGEN_MDIO_CTRL(_i) (0x000881D0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
464
-#define I40E_GLGEN_MDIO_CTRL_MAX_INDEX 3
465
-#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT 0
466
-#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_MASK I40E_MASK(0x1FFFF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT)
467
-#define I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT 17
468
-#define I40E_GLGEN_MDIO_CTRL_CONTMDC_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT)
469
-#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT 18
470
-#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK I40E_MASK(0x7FF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT)
471
-#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_SHIFT 29
472
-#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_MASK I40E_MASK(0x7, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_SHIFT)
473
65
 #define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
474
-#define I40E_GLGEN_MDIO_I2C_SEL_MAX_INDEX 3
475
-#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT 0
476
-#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT)
477
-#define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT 1
478
-#define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_MASK I40E_MASK(0xF, I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT)
479
-#define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT 5
480
-#define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT)
481
-#define I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_SHIFT 10
482
-#define I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_SHIFT)
483
-#define I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_SHIFT 15
484
-#define I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_SHIFT)
485
-#define I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_SHIFT 20
486
-#define I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_SHIFT)
487
-#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT 25
488
-#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_MASK I40E_MASK(0xF, I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT)
489
-#define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT 31
490
-#define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT)
491
66
 #define I40E_GLGEN_MSCA(_i) (0x0008818C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
492
-#define I40E_GLGEN_MSCA_MAX_INDEX 3
493
67
 #define I40E_GLGEN_MSCA_MDIADD_SHIFT 0
494
-#define I40E_GLGEN_MSCA_MDIADD_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSCA_MDIADD_SHIFT)
495
68
 #define I40E_GLGEN_MSCA_DEVADD_SHIFT 16
496
-#define I40E_GLGEN_MSCA_DEVADD_MASK I40E_MASK(0x1F, I40E_GLGEN_MSCA_DEVADD_SHIFT)
497
69
 #define I40E_GLGEN_MSCA_PHYADD_SHIFT 21
498
-#define I40E_GLGEN_MSCA_PHYADD_MASK I40E_MASK(0x1F, I40E_GLGEN_MSCA_PHYADD_SHIFT)
499
70
 #define I40E_GLGEN_MSCA_OPCODE_SHIFT 26
500
-#define I40E_GLGEN_MSCA_OPCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_OPCODE_SHIFT)
501
71
 #define I40E_GLGEN_MSCA_STCODE_SHIFT 28
502
-#define I40E_GLGEN_MSCA_STCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_STCODE_SHIFT)
503
72
 #define I40E_GLGEN_MSCA_MDICMD_SHIFT 30
504
73
 #define I40E_GLGEN_MSCA_MDICMD_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDICMD_SHIFT)
505
74
 #define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31
506
-#define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT)
75
+#define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1u, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT)
507
76
 #define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
508
-#define I40E_GLGEN_MSRWD_MAX_INDEX 3
509
77
 #define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0
510
-#define I40E_GLGEN_MSRWD_MDIWRDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT)
511
78
 #define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16
512
79
 #define I40E_GLGEN_MSRWD_MDIRDDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT)
513
-#define I40E_GLGEN_PCIFCNCNT 0x001C0AB4 /* Reset: PCIR */
80
+#define I40E_GLGEN_PCIFCNCNT                0x001C0AB4 /* Reset: PCIR */
514
81
 #define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0
515
-#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK I40E_MASK(0x1F, I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT)
82
+#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK  I40E_MASK(0x1F, I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT)
516
83
 #define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT 16
517
-#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_MASK I40E_MASK(0xFF, I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT)
84
+#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_MASK  I40E_MASK(0xFF, I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT)
518
85
 #define I40E_GLGEN_RSTAT 0x000B8188 /* Reset: POR */
519
86
 #define I40E_GLGEN_RSTAT_DEVSTATE_SHIFT 0
520
87
 #define I40E_GLGEN_RSTAT_DEVSTATE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_DEVSTATE_SHIFT)
521
88
 #define I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT 2
522
89
 #define I40E_GLGEN_RSTAT_RESET_TYPE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT)
523
-#define I40E_GLGEN_RSTAT_CORERCNT_SHIFT 4
524
-#define I40E_GLGEN_RSTAT_CORERCNT_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_CORERCNT_SHIFT)
525
-#define I40E_GLGEN_RSTAT_GLOBRCNT_SHIFT 6
526
-#define I40E_GLGEN_RSTAT_GLOBRCNT_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_GLOBRCNT_SHIFT)
527
-#define I40E_GLGEN_RSTAT_EMPRCNT_SHIFT 8
528
-#define I40E_GLGEN_RSTAT_EMPRCNT_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_EMPRCNT_SHIFT)
529
-#define I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT 10
530
-#define I40E_GLGEN_RSTAT_TIME_TO_RST_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT)
531
90
 #define I40E_GLGEN_RSTCTL 0x000B8180 /* Reset: POR */
532
91
 #define I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT 0
533
92
 #define I40E_GLGEN_RSTCTL_GRSTDEL_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT)
534
-#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT 8
535
-#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_MASK I40E_MASK(0x1, I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT)
536
93
 #define I40E_GLGEN_RTRIG 0x000B8190 /* Reset: CORER */
537
94
 #define I40E_GLGEN_RTRIG_CORER_SHIFT 0
538
95
 #define I40E_GLGEN_RTRIG_CORER_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_CORER_SHIFT)
539
96
 #define I40E_GLGEN_RTRIG_GLOBR_SHIFT 1
540
97
 #define I40E_GLGEN_RTRIG_GLOBR_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_GLOBR_SHIFT)
541
-#define I40E_GLGEN_RTRIG_EMPFWR_SHIFT 2
542
-#define I40E_GLGEN_RTRIG_EMPFWR_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_EMPFWR_SHIFT)
543
98
 #define I40E_GLGEN_STAT 0x000B612C /* Reset: POR */
544
-#define I40E_GLGEN_STAT_HWRSVD0_SHIFT 0
545
-#define I40E_GLGEN_STAT_HWRSVD0_MASK I40E_MASK(0x3, I40E_GLGEN_STAT_HWRSVD0_SHIFT)
546
-#define I40E_GLGEN_STAT_DCBEN_SHIFT 2
547
-#define I40E_GLGEN_STAT_DCBEN_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_DCBEN_SHIFT)
548
-#define I40E_GLGEN_STAT_VTEN_SHIFT 3
549
-#define I40E_GLGEN_STAT_VTEN_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_VTEN_SHIFT)
550
-#define I40E_GLGEN_STAT_FCOEN_SHIFT 4
551
-#define I40E_GLGEN_STAT_FCOEN_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_FCOEN_SHIFT)
552
-#define I40E_GLGEN_STAT_EVBEN_SHIFT 5
553
-#define I40E_GLGEN_STAT_EVBEN_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_EVBEN_SHIFT)
554
-#define I40E_GLGEN_STAT_HWRSVD1_SHIFT 6
555
-#define I40E_GLGEN_STAT_HWRSVD1_MASK I40E_MASK(0x3, I40E_GLGEN_STAT_HWRSVD1_SHIFT)
556
99
 #define I40E_GLGEN_VFLRSTAT(_i) (0x00092600 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */
557
-#define I40E_GLGEN_VFLRSTAT_MAX_INDEX 3
558
-#define I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT 0
559
-#define I40E_GLGEN_VFLRSTAT_VFLRE_MASK I40E_MASK(0xFFFFFFFF, I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT)
560
100
 #define I40E_GLVFGEN_TIMER 0x000881BC /* Reset: CORER */
561
-#define I40E_GLVFGEN_TIMER_GTIME_SHIFT 0
562
-#define I40E_GLVFGEN_TIMER_GTIME_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVFGEN_TIMER_GTIME_SHIFT)
563
101
 #define I40E_PFGEN_CTRL 0x00092400 /* Reset: PFR */
564
102
 #define I40E_PFGEN_CTRL_PFSWR_SHIFT 0
565
103
 #define I40E_PFGEN_CTRL_PFSWR_MASK I40E_MASK(0x1, I40E_PFGEN_CTRL_PFSWR_SHIFT)
566
-#define I40E_PFGEN_DRUN 0x00092500 /* Reset: CORER */
567
-#define I40E_PFGEN_DRUN_DRVUNLD_SHIFT 0
568
-#define I40E_PFGEN_DRUN_DRVUNLD_MASK I40E_MASK(0x1, I40E_PFGEN_DRUN_DRVUNLD_SHIFT)
569
104
 #define I40E_PFGEN_PORTNUM 0x001C0480 /* Reset: CORER */
570
105
 #define I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT 0
571
106
 #define I40E_PFGEN_PORTNUM_PORT_NUM_MASK I40E_MASK(0x3, I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT)
572
-#define I40E_PFGEN_STATE 0x00088000 /* Reset: CORER */
573
-#define I40E_PFGEN_STATE_RESERVED_0_SHIFT 0
574
-#define I40E_PFGEN_STATE_RESERVED_0_MASK I40E_MASK(0x1, I40E_PFGEN_STATE_RESERVED_0_SHIFT)
575
-#define I40E_PFGEN_STATE_PFFCEN_SHIFT 1
576
-#define I40E_PFGEN_STATE_PFFCEN_MASK I40E_MASK(0x1, I40E_PFGEN_STATE_PFFCEN_SHIFT)
577
-#define I40E_PFGEN_STATE_PFLINKEN_SHIFT 2
578
-#define I40E_PFGEN_STATE_PFLINKEN_MASK I40E_MASK(0x1, I40E_PFGEN_STATE_PFLINKEN_SHIFT)
579
-#define I40E_PFGEN_STATE_PFSCEN_SHIFT 3
580
-#define I40E_PFGEN_STATE_PFSCEN_MASK I40E_MASK(0x1, I40E_PFGEN_STATE_PFSCEN_SHIFT)
581
107
 #define I40E_PRTGEN_CNF 0x000B8120 /* Reset: POR */
582
108
 #define I40E_PRTGEN_CNF_PORT_DIS_SHIFT 0
583
109
 #define I40E_PRTGEN_CNF_PORT_DIS_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF_PORT_DIS_SHIFT)
584
-#define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT 1
585
-#define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT)
586
-#define I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT 2
587
-#define I40E_PRTGEN_CNF_EMP_PORT_DIS_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT)
588
-#define I40E_PRTGEN_CNF2 0x000B8160 /* Reset: POR */
589
-#define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT 0
590
-#define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT)
591
110
 #define I40E_PRTGEN_STATUS 0x000B8100 /* Reset: POR */
592
-#define I40E_PRTGEN_STATUS_PORT_VALID_SHIFT 0
593
-#define I40E_PRTGEN_STATUS_PORT_VALID_MASK I40E_MASK(0x1, I40E_PRTGEN_STATUS_PORT_VALID_SHIFT)
594
-#define I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT 1
595
-#define I40E_PRTGEN_STATUS_PORT_ACTIVE_MASK I40E_MASK(0x1, I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT)
596
111
 #define I40E_VFGEN_RSTAT1(_VF) (0x00074400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
597
-#define I40E_VFGEN_RSTAT1_MAX_INDEX 127
598
-#define I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT 0
599
-#define I40E_VFGEN_RSTAT1_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT)
600
112
 #define I40E_VPGEN_VFRSTAT(_VF) (0x00091C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
601
-#define I40E_VPGEN_VFRSTAT_MAX_INDEX 127
602
113
 #define I40E_VPGEN_VFRSTAT_VFRD_SHIFT 0
603
114
 #define I40E_VPGEN_VFRSTAT_VFRD_MASK I40E_MASK(0x1, I40E_VPGEN_VFRSTAT_VFRD_SHIFT)
604
115
 #define I40E_VPGEN_VFRTRIG(_VF) (0x00091800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
605
-#define I40E_VPGEN_VFRTRIG_MAX_INDEX 127
606
116
 #define I40E_VPGEN_VFRTRIG_VFSWR_SHIFT 0
607
117
 #define I40E_VPGEN_VFRTRIG_VFSWR_MASK I40E_MASK(0x1, I40E_VPGEN_VFRTRIG_VFSWR_SHIFT)
608
-#define I40E_VSIGEN_RSTAT(_VSI) (0x00090800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */
609
-#define I40E_VSIGEN_RSTAT_MAX_INDEX 383
610
-#define I40E_VSIGEN_RSTAT_VMRD_SHIFT 0
611
-#define I40E_VSIGEN_RSTAT_VMRD_MASK I40E_MASK(0x1, I40E_VSIGEN_RSTAT_VMRD_SHIFT)
612
-#define I40E_VSIGEN_RTRIG(_VSI) (0x00090000 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */
613
-#define I40E_VSIGEN_RTRIG_MAX_INDEX 383
614
-#define I40E_VSIGEN_RTRIG_VMSWR_SHIFT 0
615
-#define I40E_VSIGEN_RTRIG_VMSWR_MASK I40E_MASK(0x1, I40E_VSIGEN_RTRIG_VMSWR_SHIFT)
616
118
 #define I40E_GLHMC_FCOEDDPBASE(_i) (0x000C6600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
617
-#define I40E_GLHMC_FCOEDDPBASE_MAX_INDEX 15
618
119
 #define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT 0
619
120
 #define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT)
620
121
 #define I40E_GLHMC_FCOEDDPCNT(_i) (0x000C6700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
621
-#define I40E_GLHMC_FCOEDDPCNT_MAX_INDEX 15
622
-#define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT 0
623
-#define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_MASK I40E_MASK(0xFFFFF, I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT)
624
122
 #define I40E_GLHMC_FCOEDDPOBJSZ 0x000C2010 /* Reset: CORER */
625
-#define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT 0
626
-#define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT)
627
123
 #define I40E_GLHMC_FCOEFBASE(_i) (0x000C6800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
628
-#define I40E_GLHMC_FCOEFBASE_MAX_INDEX 15
629
124
 #define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT 0
630
125
 #define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT)
631
126
 #define I40E_GLHMC_FCOEFCNT(_i) (0x000C6900 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
632
-#define I40E_GLHMC_FCOEFCNT_MAX_INDEX 15
633
-#define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT 0
634
-#define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_MASK I40E_MASK(0x7FFFFF, I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT)
635
127
 #define I40E_GLHMC_FCOEFMAX 0x000C20D0 /* Reset: CORER */
636
128
 #define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT 0
637
129
 #define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK I40E_MASK(0xFFFF, I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT)
638
130
 #define I40E_GLHMC_FCOEFOBJSZ 0x000C2018 /* Reset: CORER */
639
-#define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT 0
640
-#define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT)
641
131
 #define I40E_GLHMC_FCOEMAX 0x000C2014 /* Reset: CORER */
642
-#define I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT 0
643
-#define I40E_GLHMC_FCOEMAX_PMFCOEMAX_MASK I40E_MASK(0x1FFF, I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT)
644
-#define I40E_GLHMC_FSIAVBASE(_i) (0x000C5600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
645
-#define I40E_GLHMC_FSIAVBASE_MAX_INDEX 15
646
-#define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT 0
647
-#define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT)
648
-#define I40E_GLHMC_FSIAVCNT(_i) (0x000C5700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
649
-#define I40E_GLHMC_FSIAVCNT_MAX_INDEX 15
650
-#define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT 0
651
-#define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT)
652
-#define I40E_GLHMC_FSIAVCNT_RSVD_SHIFT 29
653
-#define I40E_GLHMC_FSIAVCNT_RSVD_MASK I40E_MASK(0x7, I40E_GLHMC_FSIAVCNT_RSVD_SHIFT)
654
-#define I40E_GLHMC_FSIAVMAX 0x000C2068 /* Reset: CORER */
655
-#define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT 0
656
-#define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_MASK I40E_MASK(0x1FFFF, I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT)
657
-#define I40E_GLHMC_FSIAVOBJSZ 0x000C2064 /* Reset: CORER */
658
-#define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT 0
659
-#define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT)
660
-#define I40E_GLHMC_FSIMCBASE(_i) (0x000C6000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
661
-#define I40E_GLHMC_FSIMCBASE_MAX_INDEX 15
662
-#define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT 0
663
-#define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT)
664
-#define I40E_GLHMC_FSIMCCNT(_i) (0x000C6100 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
665
-#define I40E_GLHMC_FSIMCCNT_MAX_INDEX 15
666
-#define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT 0
667
-#define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT)
668
-#define I40E_GLHMC_FSIMCMAX 0x000C2060 /* Reset: CORER */
669
-#define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT 0
670
-#define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_MASK I40E_MASK(0x3FFF, I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT)
671
-#define I40E_GLHMC_FSIMCOBJSZ 0x000C205c /* Reset: CORER */
672
-#define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT 0
673
-#define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT)
674
132
 #define I40E_GLHMC_LANQMAX 0x000C2008 /* Reset: CORER */
675
-#define I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT 0
676
-#define I40E_GLHMC_LANQMAX_PMLANQMAX_MASK I40E_MASK(0x7FF, I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT)
677
133
 #define I40E_GLHMC_LANRXBASE(_i) (0x000C6400 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
678
-#define I40E_GLHMC_LANRXBASE_MAX_INDEX 15
679
134
 #define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT 0
680
135
 #define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT)
681
136
 #define I40E_GLHMC_LANRXCNT(_i) (0x000C6500 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
682
-#define I40E_GLHMC_LANRXCNT_MAX_INDEX 15
683
-#define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT 0
684
-#define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_MASK I40E_MASK(0x7FF, I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT)
685
137
 #define I40E_GLHMC_LANRXOBJSZ 0x000C200c /* Reset: CORER */
686
-#define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT 0
687
-#define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT)
688
138
 #define I40E_GLHMC_LANTXBASE(_i) (0x000C6200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
689
-#define I40E_GLHMC_LANTXBASE_MAX_INDEX 15
690
139
 #define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT 0
691
140
 #define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT)
692
-#define I40E_GLHMC_LANTXBASE_RSVD_SHIFT 24
693
-#define I40E_GLHMC_LANTXBASE_RSVD_MASK I40E_MASK(0xFF, I40E_GLHMC_LANTXBASE_RSVD_SHIFT)
694
141
 #define I40E_GLHMC_LANTXCNT(_i) (0x000C6300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
695
-#define I40E_GLHMC_LANTXCNT_MAX_INDEX 15
696
-#define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT 0
697
-#define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_MASK I40E_MASK(0x7FF, I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT)
698
142
 #define I40E_GLHMC_LANTXOBJSZ 0x000C2004 /* Reset: CORER */
699
-#define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT 0
700
-#define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT)
701
-#define I40E_GLHMC_PFASSIGN(_i) (0x000C0c00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
702
-#define I40E_GLHMC_PFASSIGN_MAX_INDEX 15
703
-#define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT 0
704
-#define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_MASK I40E_MASK(0xF, I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT)
705
-#define I40E_GLHMC_SDPART(_i) (0x000C0800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
706
-#define I40E_GLHMC_SDPART_MAX_INDEX 15
707
-#define I40E_GLHMC_SDPART_PMSDBASE_SHIFT 0
708
-#define I40E_GLHMC_SDPART_PMSDBASE_MASK I40E_MASK(0xFFF, I40E_GLHMC_SDPART_PMSDBASE_SHIFT)
709
-#define I40E_GLHMC_SDPART_PMSDSIZE_SHIFT 16
710
-#define I40E_GLHMC_SDPART_PMSDSIZE_MASK I40E_MASK(0x1FFF, I40E_GLHMC_SDPART_PMSDSIZE_SHIFT)
711
143
 #define I40E_PFHMC_ERRORDATA 0x000C0500 /* Reset: PFR */
712
-#define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT 0
713
-#define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_MASK I40E_MASK(0x3FFFFFFF, I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT)
714
144
 #define I40E_PFHMC_ERRORINFO 0x000C0400 /* Reset: PFR */
715
-#define I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT 0
716
-#define I40E_PFHMC_ERRORINFO_PMF_INDEX_MASK I40E_MASK(0x1F, I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT)
717
-#define I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT 7
718
-#define I40E_PFHMC_ERRORINFO_PMF_ISVF_MASK I40E_MASK(0x1, I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT)
719
-#define I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT 8
720
-#define I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_MASK I40E_MASK(0xF, I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT)
721
-#define I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT 16
722
-#define I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_MASK I40E_MASK(0x1F, I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT)
723
-#define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT 31
724
-#define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_MASK I40E_MASK(0x1, I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT)
725
145
 #define I40E_PFHMC_PDINV 0x000C0300 /* Reset: PFR */
726
146
 #define I40E_PFHMC_PDINV_PMSDIDX_SHIFT 0
727
-#define I40E_PFHMC_PDINV_PMSDIDX_MASK I40E_MASK(0xFFF, I40E_PFHMC_PDINV_PMSDIDX_SHIFT)
728
147
 #define I40E_PFHMC_PDINV_PMPDIDX_SHIFT 16
729
-#define I40E_PFHMC_PDINV_PMPDIDX_MASK I40E_MASK(0x1FF, I40E_PFHMC_PDINV_PMPDIDX_SHIFT)
730
148
 #define I40E_PFHMC_SDCMD 0x000C0000 /* Reset: PFR */
731
-#define I40E_PFHMC_SDCMD_PMSDIDX_SHIFT 0
732
-#define I40E_PFHMC_SDCMD_PMSDIDX_MASK I40E_MASK(0xFFF, I40E_PFHMC_SDCMD_PMSDIDX_SHIFT)
733
149
 #define I40E_PFHMC_SDCMD_PMSDWR_SHIFT 31
734
-#define I40E_PFHMC_SDCMD_PMSDWR_MASK I40E_MASK(0x1, I40E_PFHMC_SDCMD_PMSDWR_SHIFT)
735
150
 #define I40E_PFHMC_SDDATAHIGH 0x000C0200 /* Reset: PFR */
736
-#define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT 0
737
-#define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT)
738
151
 #define I40E_PFHMC_SDDATALOW 0x000C0100 /* Reset: PFR */
739
152
 #define I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT 0
740
-#define I40E_PFHMC_SDDATALOW_PMSDVALID_MASK I40E_MASK(0x1, I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT)
741
153
 #define I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT 1
742
-#define I40E_PFHMC_SDDATALOW_PMSDTYPE_MASK I40E_MASK(0x1, I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT)
743
154
 #define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT 2
744
-#define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_MASK I40E_MASK(0x3FF, I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT)
745
-#define I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT 12
746
-#define I40E_PFHMC_SDDATALOW_PMSDDATALOW_MASK I40E_MASK(0xFFFFF, I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT)
747
-#define I40E_GL_GP_FUSE(_i) (0x0009400C + ((_i) * 4)) /* _i=0...28 */ /* Reset: POR */
748
-#define I40E_GL_GP_FUSE_MAX_INDEX 28
749
-#define I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT 0
750
-#define I40E_GL_GP_FUSE_GL_GP_FUSE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT)
751
-#define I40E_GL_UFUSE 0x00094008 /* Reset: POR */
752
-#define I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT 1
753
-#define I40E_GL_UFUSE_FOUR_PORT_ENABLE_MASK I40E_MASK(0x1, I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT)
754
-#define I40E_GL_UFUSE_NIC_ID_SHIFT 2
755
-#define I40E_GL_UFUSE_NIC_ID_MASK I40E_MASK(0x1, I40E_GL_UFUSE_NIC_ID_SHIFT)
756
-#define I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT 10
757
-#define I40E_GL_UFUSE_ULT_LOCKOUT_MASK I40E_MASK(0x1, I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT)
758
-#define I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT 11
759
-#define I40E_GL_UFUSE_CLS_LOCKOUT_MASK I40E_MASK(0x1, I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT)
760
-#define I40E_EMPINT_GPIO_ENA 0x00088188 /* Reset: POR */
761
-#define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT 0
762
-#define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT)
763
-#define I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT 1
764
-#define I40E_EMPINT_GPIO_ENA_GPIO1_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT)
765
-#define I40E_EMPINT_GPIO_ENA_GPIO2_ENA_SHIFT 2
766
-#define I40E_EMPINT_GPIO_ENA_GPIO2_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO2_ENA_SHIFT)
767
-#define I40E_EMPINT_GPIO_ENA_GPIO3_ENA_SHIFT 3
768
-#define I40E_EMPINT_GPIO_ENA_GPIO3_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO3_ENA_SHIFT)
769
-#define I40E_EMPINT_GPIO_ENA_GPIO4_ENA_SHIFT 4
770
-#define I40E_EMPINT_GPIO_ENA_GPIO4_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO4_ENA_SHIFT)
771
-#define I40E_EMPINT_GPIO_ENA_GPIO5_ENA_SHIFT 5
772
-#define I40E_EMPINT_GPIO_ENA_GPIO5_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO5_ENA_SHIFT)
773
-#define I40E_EMPINT_GPIO_ENA_GPIO6_ENA_SHIFT 6
774
-#define I40E_EMPINT_GPIO_ENA_GPIO6_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO6_ENA_SHIFT)
775
-#define I40E_EMPINT_GPIO_ENA_GPIO7_ENA_SHIFT 7
776
-#define I40E_EMPINT_GPIO_ENA_GPIO7_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO7_ENA_SHIFT)
777
-#define I40E_EMPINT_GPIO_ENA_GPIO8_ENA_SHIFT 8
778
-#define I40E_EMPINT_GPIO_ENA_GPIO8_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO8_ENA_SHIFT)
779
-#define I40E_EMPINT_GPIO_ENA_GPIO9_ENA_SHIFT 9
780
-#define I40E_EMPINT_GPIO_ENA_GPIO9_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO9_ENA_SHIFT)
781
-#define I40E_EMPINT_GPIO_ENA_GPIO10_ENA_SHIFT 10
782
-#define I40E_EMPINT_GPIO_ENA_GPIO10_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO10_ENA_SHIFT)
783
-#define I40E_EMPINT_GPIO_ENA_GPIO11_ENA_SHIFT 11
784
-#define I40E_EMPINT_GPIO_ENA_GPIO11_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO11_ENA_SHIFT)
785
-#define I40E_EMPINT_GPIO_ENA_GPIO12_ENA_SHIFT 12
786
-#define I40E_EMPINT_GPIO_ENA_GPIO12_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO12_ENA_SHIFT)
787
-#define I40E_EMPINT_GPIO_ENA_GPIO13_ENA_SHIFT 13
788
-#define I40E_EMPINT_GPIO_ENA_GPIO13_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO13_ENA_SHIFT)
789
-#define I40E_EMPINT_GPIO_ENA_GPIO14_ENA_SHIFT 14
790
-#define I40E_EMPINT_GPIO_ENA_GPIO14_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO14_ENA_SHIFT)
791
-#define I40E_EMPINT_GPIO_ENA_GPIO15_ENA_SHIFT 15
792
-#define I40E_EMPINT_GPIO_ENA_GPIO15_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO15_ENA_SHIFT)
793
-#define I40E_EMPINT_GPIO_ENA_GPIO16_ENA_SHIFT 16
794
-#define I40E_EMPINT_GPIO_ENA_GPIO16_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO16_ENA_SHIFT)
795
-#define I40E_EMPINT_GPIO_ENA_GPIO17_ENA_SHIFT 17
796
-#define I40E_EMPINT_GPIO_ENA_GPIO17_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO17_ENA_SHIFT)
797
-#define I40E_EMPINT_GPIO_ENA_GPIO18_ENA_SHIFT 18
798
-#define I40E_EMPINT_GPIO_ENA_GPIO18_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO18_ENA_SHIFT)
799
-#define I40E_EMPINT_GPIO_ENA_GPIO19_ENA_SHIFT 19
800
-#define I40E_EMPINT_GPIO_ENA_GPIO19_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO19_ENA_SHIFT)
801
-#define I40E_EMPINT_GPIO_ENA_GPIO20_ENA_SHIFT 20
802
-#define I40E_EMPINT_GPIO_ENA_GPIO20_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO20_ENA_SHIFT)
803
-#define I40E_EMPINT_GPIO_ENA_GPIO21_ENA_SHIFT 21
804
-#define I40E_EMPINT_GPIO_ENA_GPIO21_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO21_ENA_SHIFT)
805
-#define I40E_EMPINT_GPIO_ENA_GPIO22_ENA_SHIFT 22
806
-#define I40E_EMPINT_GPIO_ENA_GPIO22_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO22_ENA_SHIFT)
807
-#define I40E_EMPINT_GPIO_ENA_GPIO23_ENA_SHIFT 23
808
-#define I40E_EMPINT_GPIO_ENA_GPIO23_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO23_ENA_SHIFT)
809
-#define I40E_EMPINT_GPIO_ENA_GPIO24_ENA_SHIFT 24
810
-#define I40E_EMPINT_GPIO_ENA_GPIO24_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO24_ENA_SHIFT)
811
-#define I40E_EMPINT_GPIO_ENA_GPIO25_ENA_SHIFT 25
812
-#define I40E_EMPINT_GPIO_ENA_GPIO25_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO25_ENA_SHIFT)
813
-#define I40E_EMPINT_GPIO_ENA_GPIO26_ENA_SHIFT 26
814
-#define I40E_EMPINT_GPIO_ENA_GPIO26_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO26_ENA_SHIFT)
815
-#define I40E_EMPINT_GPIO_ENA_GPIO27_ENA_SHIFT 27
816
-#define I40E_EMPINT_GPIO_ENA_GPIO27_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO27_ENA_SHIFT)
817
-#define I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT 28
818
-#define I40E_EMPINT_GPIO_ENA_GPIO28_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT)
819
-#define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT 29
820
-#define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT)
821
155
 #define I40E_PFGEN_PORTMDIO_NUM 0x0003F100 /* Reset: CORER */
822
-#define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT 0
823
-#define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_MASK I40E_MASK(0x3, I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT)
824
156
 #define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT 4
825
157
 #define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK I40E_MASK(0x1, I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT)
826
158
 #define I40E_PFINT_AEQCTL 0x00038700 /* Reset: CORER */
827
159
 #define I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT 0
828
-#define I40E_PFINT_AEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT)
829
160
 #define I40E_PFINT_AEQCTL_ITR_INDX_SHIFT 11
830
-#define I40E_PFINT_AEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_AEQCTL_ITR_INDX_SHIFT)
831
-#define I40E_PFINT_AEQCTL_MSIX0_INDX_SHIFT 13
832
-#define I40E_PFINT_AEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_PFINT_AEQCTL_MSIX0_INDX_SHIFT)
833
161
 #define I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT 30
834
162
 #define I40E_PFINT_AEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT)
835
-#define I40E_PFINT_AEQCTL_INTEVENT_SHIFT 31
836
-#define I40E_PFINT_AEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_AEQCTL_INTEVENT_SHIFT)
837
163
 #define I40E_PFINT_CEQCTL(_INTPF) (0x00036800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: CORER */
838
-#define I40E_PFINT_CEQCTL_MAX_INDEX 511
839
164
 #define I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT 0
840
-#define I40E_PFINT_CEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT)
841
165
 #define I40E_PFINT_CEQCTL_ITR_INDX_SHIFT 11
842
-#define I40E_PFINT_CEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_CEQCTL_ITR_INDX_SHIFT)
843
-#define I40E_PFINT_CEQCTL_MSIX0_INDX_SHIFT 13
844
-#define I40E_PFINT_CEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_PFINT_CEQCTL_MSIX0_INDX_SHIFT)
845
166
 #define I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT 16
846
-#define I40E_PFINT_CEQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT)
847
-#define I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT 27
848
-#define I40E_PFINT_CEQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT)
849
167
 #define I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT 30
850
168
 #define I40E_PFINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT)
851
-#define I40E_PFINT_CEQCTL_INTEVENT_SHIFT 31
852
-#define I40E_PFINT_CEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_INTEVENT_SHIFT)
853
169
 #define I40E_GLINT_CTL 0x0003F800 /* Reset: CORER */
854
-#define I40E_GLINT_CTL_DIS_AUTOMASK_PF0_SHIFT 0
855
-#define I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_PF0_SHIFT)
856
170
 #define I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT 1
857
171
 #define I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT)
858
-#define I40E_GLINT_CTL_DIS_AUTOMASK_N_SHIFT 2
859
-#define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_N_SHIFT)
860
172
 #define I40E_PFINT_DYN_CTL0 0x00038480 /* Reset: PFR */
861
173
 #define I40E_PFINT_DYN_CTL0_INTENA_SHIFT 0
862
174
 #define I40E_PFINT_DYN_CTL0_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_SHIFT)
..
..
@@ -866,8 +178,6 @@
866
178
 #define I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT)
867
179
 #define I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT 3
868
180
 #define I40E_PFINT_DYN_CTL0_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT)
869
-#define I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT 5
870
-#define I40E_PFINT_DYN_CTL0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT)
871
181
 #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24
872
182
 #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT)
873
183
 #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25
..
..
@@ -875,7 +185,6 @@
875
185
 #define I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT 31
876
186
 #define I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT)
877
187
 #define I40E_PFINT_DYN_CTLN(_INTPF) (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
878
-#define I40E_PFINT_DYN_CTLN_MAX_INDEX 511
879
188
 #define I40E_PFINT_DYN_CTLN_INTENA_SHIFT 0
880
189
 #define I40E_PFINT_DYN_CTLN_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_INTENA_SHIFT)
881
190
 #define I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT 1
..
..
@@ -885,93 +194,13 @@
885
194
 #define I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT 3
886
195
 #define I40E_PFINT_DYN_CTLN_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT)
887
196
 #define I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT 5
888
-#define I40E_PFINT_DYN_CTLN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT)
889
197
 #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24
890
198
 #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT)
891
-#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT 25
892
-#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT)
893
-#define I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT 31
894
-#define I40E_PFINT_DYN_CTLN_INTENA_MSK_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT)
895
-#define I40E_PFINT_GPIO_ENA 0x00088080 /* Reset: CORER */
896
-#define I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT 0
897
-#define I40E_PFINT_GPIO_ENA_GPIO0_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT)
898
-#define I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT 1
899
-#define I40E_PFINT_GPIO_ENA_GPIO1_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT)
900
-#define I40E_PFINT_GPIO_ENA_GPIO2_ENA_SHIFT 2
901
-#define I40E_PFINT_GPIO_ENA_GPIO2_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO2_ENA_SHIFT)
902
-#define I40E_PFINT_GPIO_ENA_GPIO3_ENA_SHIFT 3
903
-#define I40E_PFINT_GPIO_ENA_GPIO3_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO3_ENA_SHIFT)
904
-#define I40E_PFINT_GPIO_ENA_GPIO4_ENA_SHIFT 4
905
-#define I40E_PFINT_GPIO_ENA_GPIO4_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO4_ENA_SHIFT)
906
-#define I40E_PFINT_GPIO_ENA_GPIO5_ENA_SHIFT 5
907
-#define I40E_PFINT_GPIO_ENA_GPIO5_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO5_ENA_SHIFT)
908
-#define I40E_PFINT_GPIO_ENA_GPIO6_ENA_SHIFT 6
909
-#define I40E_PFINT_GPIO_ENA_GPIO6_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO6_ENA_SHIFT)
910
-#define I40E_PFINT_GPIO_ENA_GPIO7_ENA_SHIFT 7
911
-#define I40E_PFINT_GPIO_ENA_GPIO7_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO7_ENA_SHIFT)
912
-#define I40E_PFINT_GPIO_ENA_GPIO8_ENA_SHIFT 8
913
-#define I40E_PFINT_GPIO_ENA_GPIO8_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO8_ENA_SHIFT)
914
-#define I40E_PFINT_GPIO_ENA_GPIO9_ENA_SHIFT 9
915
-#define I40E_PFINT_GPIO_ENA_GPIO9_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO9_ENA_SHIFT)
916
-#define I40E_PFINT_GPIO_ENA_GPIO10_ENA_SHIFT 10
917
-#define I40E_PFINT_GPIO_ENA_GPIO10_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO10_ENA_SHIFT)
918
-#define I40E_PFINT_GPIO_ENA_GPIO11_ENA_SHIFT 11
919
-#define I40E_PFINT_GPIO_ENA_GPIO11_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO11_ENA_SHIFT)
920
-#define I40E_PFINT_GPIO_ENA_GPIO12_ENA_SHIFT 12
921
-#define I40E_PFINT_GPIO_ENA_GPIO12_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO12_ENA_SHIFT)
922
-#define I40E_PFINT_GPIO_ENA_GPIO13_ENA_SHIFT 13
923
-#define I40E_PFINT_GPIO_ENA_GPIO13_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO13_ENA_SHIFT)
924
-#define I40E_PFINT_GPIO_ENA_GPIO14_ENA_SHIFT 14
925
-#define I40E_PFINT_GPIO_ENA_GPIO14_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO14_ENA_SHIFT)
926
-#define I40E_PFINT_GPIO_ENA_GPIO15_ENA_SHIFT 15
927
-#define I40E_PFINT_GPIO_ENA_GPIO15_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO15_ENA_SHIFT)
928
-#define I40E_PFINT_GPIO_ENA_GPIO16_ENA_SHIFT 16
929
-#define I40E_PFINT_GPIO_ENA_GPIO16_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO16_ENA_SHIFT)
930
-#define I40E_PFINT_GPIO_ENA_GPIO17_ENA_SHIFT 17
931
-#define I40E_PFINT_GPIO_ENA_GPIO17_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO17_ENA_SHIFT)
932
-#define I40E_PFINT_GPIO_ENA_GPIO18_ENA_SHIFT 18
933
-#define I40E_PFINT_GPIO_ENA_GPIO18_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO18_ENA_SHIFT)
934
-#define I40E_PFINT_GPIO_ENA_GPIO19_ENA_SHIFT 19
935
-#define I40E_PFINT_GPIO_ENA_GPIO19_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO19_ENA_SHIFT)
936
-#define I40E_PFINT_GPIO_ENA_GPIO20_ENA_SHIFT 20
937
-#define I40E_PFINT_GPIO_ENA_GPIO20_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO20_ENA_SHIFT)
938
-#define I40E_PFINT_GPIO_ENA_GPIO21_ENA_SHIFT 21
939
-#define I40E_PFINT_GPIO_ENA_GPIO21_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO21_ENA_SHIFT)
940
-#define I40E_PFINT_GPIO_ENA_GPIO22_ENA_SHIFT 22
941
-#define I40E_PFINT_GPIO_ENA_GPIO22_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO22_ENA_SHIFT)
942
-#define I40E_PFINT_GPIO_ENA_GPIO23_ENA_SHIFT 23
943
-#define I40E_PFINT_GPIO_ENA_GPIO23_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO23_ENA_SHIFT)
944
-#define I40E_PFINT_GPIO_ENA_GPIO24_ENA_SHIFT 24
945
-#define I40E_PFINT_GPIO_ENA_GPIO24_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO24_ENA_SHIFT)
946
-#define I40E_PFINT_GPIO_ENA_GPIO25_ENA_SHIFT 25
947
-#define I40E_PFINT_GPIO_ENA_GPIO25_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO25_ENA_SHIFT)
948
-#define I40E_PFINT_GPIO_ENA_GPIO26_ENA_SHIFT 26
949
-#define I40E_PFINT_GPIO_ENA_GPIO26_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO26_ENA_SHIFT)
950
-#define I40E_PFINT_GPIO_ENA_GPIO27_ENA_SHIFT 27
951
-#define I40E_PFINT_GPIO_ENA_GPIO27_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO27_ENA_SHIFT)
952
-#define I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT 28
953
-#define I40E_PFINT_GPIO_ENA_GPIO28_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT)
954
-#define I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT 29
955
-#define I40E_PFINT_GPIO_ENA_GPIO29_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT)
956
199
 #define I40E_PFINT_ICR0 0x00038780 /* Reset: CORER */
957
200
 #define I40E_PFINT_ICR0_INTEVENT_SHIFT 0
958
201
 #define I40E_PFINT_ICR0_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_INTEVENT_SHIFT)
959
202
 #define I40E_PFINT_ICR0_QUEUE_0_SHIFT 1
960
203
 #define I40E_PFINT_ICR0_QUEUE_0_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_0_SHIFT)
961
-#define I40E_PFINT_ICR0_QUEUE_1_SHIFT 2
962
-#define I40E_PFINT_ICR0_QUEUE_1_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_1_SHIFT)
963
-#define I40E_PFINT_ICR0_QUEUE_2_SHIFT 3
964
-#define I40E_PFINT_ICR0_QUEUE_2_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_2_SHIFT)
965
-#define I40E_PFINT_ICR0_QUEUE_3_SHIFT 4
966
-#define I40E_PFINT_ICR0_QUEUE_3_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_3_SHIFT)
967
-#define I40E_PFINT_ICR0_QUEUE_4_SHIFT 5
968
-#define I40E_PFINT_ICR0_QUEUE_4_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_4_SHIFT)
969
-#define I40E_PFINT_ICR0_QUEUE_5_SHIFT 6
970
-#define I40E_PFINT_ICR0_QUEUE_5_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_5_SHIFT)
971
-#define I40E_PFINT_ICR0_QUEUE_6_SHIFT 7
972
-#define I40E_PFINT_ICR0_QUEUE_6_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_6_SHIFT)
973
-#define I40E_PFINT_ICR0_QUEUE_7_SHIFT 8
974
-#define I40E_PFINT_ICR0_QUEUE_7_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_7_SHIFT)
975
204
 #define I40E_PFINT_ICR0_ECC_ERR_SHIFT 16
976
205
 #define I40E_PFINT_ICR0_ECC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ECC_ERR_SHIFT)
977
206
 #define I40E_PFINT_ICR0_MAL_DETECT_SHIFT 19
..
..
@@ -980,14 +209,8 @@
980
209
 #define I40E_PFINT_ICR0_GRST_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_GRST_SHIFT)
981
210
 #define I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT 21
982
211
 #define I40E_PFINT_ICR0_PCI_EXCEPTION_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT)
983
-#define I40E_PFINT_ICR0_GPIO_SHIFT 22
984
-#define I40E_PFINT_ICR0_GPIO_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_GPIO_SHIFT)
985
212
 #define I40E_PFINT_ICR0_TIMESYNC_SHIFT 23
986
213
 #define I40E_PFINT_ICR0_TIMESYNC_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_TIMESYNC_SHIFT)
987
-#define I40E_PFINT_ICR0_STORM_DETECT_SHIFT 24
988
-#define I40E_PFINT_ICR0_STORM_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_STORM_DETECT_SHIFT)
989
-#define I40E_PFINT_ICR0_LINK_STAT_CHANGE_SHIFT 25
990
-#define I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_LINK_STAT_CHANGE_SHIFT)
991
214
 #define I40E_PFINT_ICR0_HMC_ERR_SHIFT 26
992
215
 #define I40E_PFINT_ICR0_HMC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_HMC_ERR_SHIFT)
993
216
 #define I40E_PFINT_ICR0_PE_CRITERR_SHIFT 28
..
..
@@ -1011,10 +234,6 @@
1011
234
 #define I40E_PFINT_ICR0_ENA_GPIO_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_GPIO_SHIFT)
1012
235
 #define I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT 23
1013
236
 #define I40E_PFINT_ICR0_ENA_TIMESYNC_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT)
1014
-#define I40E_PFINT_ICR0_ENA_STORM_DETECT_SHIFT 24
1015
-#define I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_STORM_DETECT_SHIFT)
1016
-#define I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT 25
1017
-#define I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT)
1018
237
 #define I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT 26
1019
238
 #define I40E_PFINT_ICR0_ENA_HMC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT)
1020
239
 #define I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT 28
..
..
@@ -1023,43 +242,17 @@
1023
242
 #define I40E_PFINT_ICR0_ENA_VFLR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_VFLR_SHIFT)
1024
243
 #define I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT 30
1025
244
 #define I40E_PFINT_ICR0_ENA_ADMINQ_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT)
1026
-#define I40E_PFINT_ICR0_ENA_RSVD_SHIFT 31
1027
-#define I40E_PFINT_ICR0_ENA_RSVD_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_RSVD_SHIFT)
1028
245
 #define I40E_PFINT_ITR0(_i) (0x00038000 + ((_i) * 128)) /* _i=0...2 */ /* Reset: PFR */
1029
-#define I40E_PFINT_ITR0_MAX_INDEX 2
1030
-#define I40E_PFINT_ITR0_INTERVAL_SHIFT 0
1031
-#define I40E_PFINT_ITR0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_ITR0_INTERVAL_SHIFT)
1032
246
 #define I40E_PFINT_ITRN(_i, _INTPF) (0x00030000 + ((_i) * 2048 + (_INTPF) * 4)) /* _i=0...2, _INTPF=0...511 */ /* Reset: PFR */
1033
-#define I40E_PFINT_ITRN_MAX_INDEX 2
1034
-#define I40E_PFINT_ITRN_INTERVAL_SHIFT 0
1035
-#define I40E_PFINT_ITRN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_ITRN_INTERVAL_SHIFT)
1036
247
 #define I40E_PFINT_LNKLST0 0x00038500 /* Reset: PFR */
1037
248
 #define I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT 0
1038
-#define I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT)
1039
-#define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT 11
1040
-#define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT)
1041
249
 #define I40E_PFINT_LNKLSTN(_INTPF) (0x00035000 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
1042
-#define I40E_PFINT_LNKLSTN_MAX_INDEX 511
1043
250
 #define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0
1044
251
 #define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT)
1045
252
 #define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11
1046
-#define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)
1047
-#define I40E_PFINT_RATE0 0x00038580 /* Reset: PFR */
1048
-#define I40E_PFINT_RATE0_INTERVAL_SHIFT 0
1049
-#define I40E_PFINT_RATE0_INTERVAL_MASK I40E_MASK(0x3F, I40E_PFINT_RATE0_INTERVAL_SHIFT)
1050
-#define I40E_PFINT_RATE0_INTRL_ENA_SHIFT 6
1051
-#define I40E_PFINT_RATE0_INTRL_ENA_MASK I40E_MASK(0x1, I40E_PFINT_RATE0_INTRL_ENA_SHIFT)
1052
253
 #define I40E_PFINT_RATEN(_INTPF) (0x00035800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
1053
-#define I40E_PFINT_RATEN_MAX_INDEX 511
1054
-#define I40E_PFINT_RATEN_INTERVAL_SHIFT 0
1055
-#define I40E_PFINT_RATEN_INTERVAL_MASK I40E_MASK(0x3F, I40E_PFINT_RATEN_INTERVAL_SHIFT)
1056
-#define I40E_PFINT_RATEN_INTRL_ENA_SHIFT 6
1057
-#define I40E_PFINT_RATEN_INTRL_ENA_MASK I40E_MASK(0x1, I40E_PFINT_RATEN_INTRL_ENA_SHIFT)
1058
254
 #define I40E_PFINT_STAT_CTL0 0x00038400 /* Reset: CORER */
1059
-#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2
1060
-#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)
1061
255
 #define I40E_QINT_RQCTL(_Q) (0x0003A000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
1062
-#define I40E_QINT_RQCTL_MAX_INDEX 1535
1063
256
 #define I40E_QINT_RQCTL_MSIX_INDX_SHIFT 0
1064
257
 #define I40E_QINT_RQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_RQCTL_MSIX_INDX_SHIFT)
1065
258
 #define I40E_QINT_RQCTL_ITR_INDX_SHIFT 11
..
..
@@ -1069,13 +262,11 @@
1069
262
 #define I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT 16
1070
263
 #define I40E_QINT_RQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)
1071
264
 #define I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT 27
1072
-#define I40E_QINT_RQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT)
1073
265
 #define I40E_QINT_RQCTL_CAUSE_ENA_SHIFT 30
1074
266
 #define I40E_QINT_RQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_QINT_RQCTL_CAUSE_ENA_SHIFT)
1075
267
 #define I40E_QINT_RQCTL_INTEVENT_SHIFT 31
1076
268
 #define I40E_QINT_RQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_QINT_RQCTL_INTEVENT_SHIFT)
1077
269
 #define I40E_QINT_TQCTL(_Q) (0x0003C000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
1078
-#define I40E_QINT_TQCTL_MAX_INDEX 1535
1079
270
 #define I40E_QINT_TQCTL_MSIX_INDX_SHIFT 0
1080
271
 #define I40E_QINT_TQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_TQCTL_MSIX_INDX_SHIFT)
1081
272
 #define I40E_QINT_TQCTL_ITR_INDX_SHIFT 11
..
..
@@ -1085,185 +276,66 @@
1085
276
 #define I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT 16
1086
277
 #define I40E_QINT_TQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)
1087
278
 #define I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT 27
1088
-#define I40E_QINT_TQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT)
1089
279
 #define I40E_QINT_TQCTL_CAUSE_ENA_SHIFT 30
1090
280
 #define I40E_QINT_TQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_QINT_TQCTL_CAUSE_ENA_SHIFT)
1091
281
 #define I40E_QINT_TQCTL_INTEVENT_SHIFT 31
1092
282
 #define I40E_QINT_TQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_QINT_TQCTL_INTEVENT_SHIFT)
1093
283
 #define I40E_VFINT_DYN_CTL0(_VF) (0x0002A400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
1094
-#define I40E_VFINT_DYN_CTL0_MAX_INDEX 127
1095
-#define I40E_VFINT_DYN_CTL0_INTENA_SHIFT 0
1096
-#define I40E_VFINT_DYN_CTL0_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_INTENA_SHIFT)
1097
-#define I40E_VFINT_DYN_CTL0_CLEARPBA_SHIFT 1
1098
-#define I40E_VFINT_DYN_CTL0_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_CLEARPBA_SHIFT)
1099
-#define I40E_VFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2
1100
-#define I40E_VFINT_DYN_CTL0_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_SWINT_TRIG_SHIFT)
1101
-#define I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT 3
1102
-#define I40E_VFINT_DYN_CTL0_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT)
1103
-#define I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT 5
1104
-#define I40E_VFINT_DYN_CTL0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT)
1105
-#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24
1106
-#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT)
1107
-#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25
1108
-#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT)
1109
-#define I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT 31
1110
-#define I40E_VFINT_DYN_CTL0_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT)
1111
284
 #define I40E_VFINT_DYN_CTLN(_INTVF) (0x00024800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */
1112
-#define I40E_VFINT_DYN_CTLN_MAX_INDEX 511
1113
-#define I40E_VFINT_DYN_CTLN_INTENA_SHIFT 0
1114
-#define I40E_VFINT_DYN_CTLN_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_INTENA_SHIFT)
1115
285
 #define I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT 1
1116
286
 #define I40E_VFINT_DYN_CTLN_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT)
1117
-#define I40E_VFINT_DYN_CTLN_SWINT_TRIG_SHIFT 2
1118
-#define I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_SWINT_TRIG_SHIFT)
1119
-#define I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT 3
1120
-#define I40E_VFINT_DYN_CTLN_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT)
1121
-#define I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT 5
1122
-#define I40E_VFINT_DYN_CTLN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT)
1123
-#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24
1124
-#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT)
1125
-#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT 25
1126
-#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT)
1127
-#define I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT 31
1128
-#define I40E_VFINT_DYN_CTLN_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT)
1129
-#define I40E_VFINT_ICR0(_VF) (0x0002BC00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
1130
-#define I40E_VFINT_ICR0_MAX_INDEX 127
1131
-#define I40E_VFINT_ICR0_INTEVENT_SHIFT 0
1132
-#define I40E_VFINT_ICR0_INTEVENT_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_INTEVENT_SHIFT)
1133
-#define I40E_VFINT_ICR0_QUEUE_0_SHIFT 1
1134
-#define I40E_VFINT_ICR0_QUEUE_0_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_0_SHIFT)
1135
-#define I40E_VFINT_ICR0_QUEUE_1_SHIFT 2
1136
-#define I40E_VFINT_ICR0_QUEUE_1_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_1_SHIFT)
1137
-#define I40E_VFINT_ICR0_QUEUE_2_SHIFT 3
1138
-#define I40E_VFINT_ICR0_QUEUE_2_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_2_SHIFT)
1139
-#define I40E_VFINT_ICR0_QUEUE_3_SHIFT 4
1140
-#define I40E_VFINT_ICR0_QUEUE_3_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_3_SHIFT)
1141
-#define I40E_VFINT_ICR0_LINK_STAT_CHANGE_SHIFT 25
1142
-#define I40E_VFINT_ICR0_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_LINK_STAT_CHANGE_SHIFT)
1143
287
 #define I40E_VFINT_ICR0_ADMINQ_SHIFT 30
1144
288
 #define I40E_VFINT_ICR0_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ADMINQ_SHIFT)
1145
-#define I40E_VFINT_ICR0_SWINT_SHIFT 31
1146
-#define I40E_VFINT_ICR0_SWINT_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_SWINT_SHIFT)
1147
289
 #define I40E_VFINT_ICR0_ENA(_VF) (0x0002C000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
1148
-#define I40E_VFINT_ICR0_ENA_MAX_INDEX 127
1149
-#define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT 25
1150
-#define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT)
1151
-#define I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT 30
1152
-#define I40E_VFINT_ICR0_ENA_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT)
1153
-#define I40E_VFINT_ICR0_ENA_RSVD_SHIFT 31
1154
-#define I40E_VFINT_ICR0_ENA_RSVD_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA_RSVD_SHIFT)
1155
-#define I40E_VFINT_ITR0(_i, _VF) (0x00028000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...2, _VF=0...127 */ /* Reset: VFR */
1156
-#define I40E_VFINT_ITR0_MAX_INDEX 2
1157
-#define I40E_VFINT_ITR0_INTERVAL_SHIFT 0
1158
-#define I40E_VFINT_ITR0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR0_INTERVAL_SHIFT)
1159
-#define I40E_VFINT_ITRN(_i, _INTVF) (0x00020000 + ((_i) * 2048 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...511 */ /* Reset: VFR */
1160
-#define I40E_VFINT_ITRN_MAX_INDEX 2
1161
-#define I40E_VFINT_ITRN_INTERVAL_SHIFT 0
1162
-#define I40E_VFINT_ITRN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN_INTERVAL_SHIFT)
1163
-#define I40E_VFINT_STAT_CTL0(_VF) (0x0002A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
1164
-#define I40E_VFINT_STAT_CTL0_MAX_INDEX 127
1165
-#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2
1166
-#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)
1167
290
 #define I40E_VPINT_AEQCTL(_VF) (0x0002B800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
1168
-#define I40E_VPINT_AEQCTL_MAX_INDEX 127
1169
291
 #define I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT 0
1170
-#define I40E_VPINT_AEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT)
1171
292
 #define I40E_VPINT_AEQCTL_ITR_INDX_SHIFT 11
1172
-#define I40E_VPINT_AEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_VPINT_AEQCTL_ITR_INDX_SHIFT)
1173
-#define I40E_VPINT_AEQCTL_MSIX0_INDX_SHIFT 13
1174
-#define I40E_VPINT_AEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_VPINT_AEQCTL_MSIX0_INDX_SHIFT)
1175
293
 #define I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT 30
1176
294
 #define I40E_VPINT_AEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT)
1177
-#define I40E_VPINT_AEQCTL_INTEVENT_SHIFT 31
1178
-#define I40E_VPINT_AEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_VPINT_AEQCTL_INTEVENT_SHIFT)
1179
295
 #define I40E_VPINT_CEQCTL(_INTVF) (0x00026800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: CORER */
1180
-#define I40E_VPINT_CEQCTL_MAX_INDEX 511
1181
296
 #define I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT 0
1182
-#define I40E_VPINT_CEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT)
1183
297
 #define I40E_VPINT_CEQCTL_ITR_INDX_SHIFT 11
1184
-#define I40E_VPINT_CEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_VPINT_CEQCTL_ITR_INDX_SHIFT)
1185
-#define I40E_VPINT_CEQCTL_MSIX0_INDX_SHIFT 13
1186
-#define I40E_VPINT_CEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_VPINT_CEQCTL_MSIX0_INDX_SHIFT)
1187
298
 #define I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT 16
1188
299
 #define I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT)
1189
300
 #define I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT 27
1190
301
 #define I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT)
1191
302
 #define I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT 30
1192
303
 #define I40E_VPINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT)
1193
-#define I40E_VPINT_CEQCTL_INTEVENT_SHIFT 31
1194
-#define I40E_VPINT_CEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_VPINT_CEQCTL_INTEVENT_SHIFT)
1195
304
 #define I40E_VPINT_LNKLST0(_VF) (0x0002A800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
1196
-#define I40E_VPINT_LNKLST0_MAX_INDEX 127
1197
305
 #define I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT 0
1198
306
 #define I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT)
1199
-#define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT 11
1200
-#define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT)
1201
307
 #define I40E_VPINT_LNKLSTN(_INTVF) (0x00025000 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */
1202
-#define I40E_VPINT_LNKLSTN_MAX_INDEX 511
1203
308
 #define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0
1204
309
 #define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT)
1205
310
 #define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11
1206
311
 #define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)
1207
-#define I40E_VPINT_RATE0(_VF) (0x0002AC00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
1208
-#define I40E_VPINT_RATE0_MAX_INDEX 127
1209
-#define I40E_VPINT_RATE0_INTERVAL_SHIFT 0
1210
-#define I40E_VPINT_RATE0_INTERVAL_MASK I40E_MASK(0x3F, I40E_VPINT_RATE0_INTERVAL_SHIFT)
1211
-#define I40E_VPINT_RATE0_INTRL_ENA_SHIFT 6
1212
-#define I40E_VPINT_RATE0_INTRL_ENA_MASK I40E_MASK(0x1, I40E_VPINT_RATE0_INTRL_ENA_SHIFT)
1213
-#define I40E_VPINT_RATEN(_INTVF) (0x00025800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */
1214
-#define I40E_VPINT_RATEN_MAX_INDEX 511
1215
-#define I40E_VPINT_RATEN_INTERVAL_SHIFT 0
1216
-#define I40E_VPINT_RATEN_INTERVAL_MASK I40E_MASK(0x3F, I40E_VPINT_RATEN_INTERVAL_SHIFT)
1217
-#define I40E_VPINT_RATEN_INTRL_ENA_SHIFT 6
1218
-#define I40E_VPINT_RATEN_INTRL_ENA_MASK I40E_MASK(0x1, I40E_VPINT_RATEN_INTRL_ENA_SHIFT)
1219
-#define I40E_GL_RDPU_CNTRL 0x00051060 /* Reset: CORER */
1220
-#define I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT 0
1221
-#define I40E_GL_RDPU_CNTRL_RX_PAD_EN_MASK I40E_MASK(0x1, I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT)
1222
-#define I40E_GL_RDPU_CNTRL_ECO_SHIFT 1
1223
-#define I40E_GL_RDPU_CNTRL_ECO_MASK I40E_MASK(0x7FFFFFFF, I40E_GL_RDPU_CNTRL_ECO_SHIFT)
1224
312
 #define I40E_GLLAN_RCTL_0 0x0012A500 /* Reset: CORER */
1225
313
 #define I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT 0
1226
314
 #define I40E_GLLAN_RCTL_0_PXE_MODE_MASK I40E_MASK(0x1, I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT)
1227
315
 #define I40E_GLLAN_TSOMSK_F 0x000442D8 /* Reset: CORER */
1228
-#define I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT 0
1229
-#define I40E_GLLAN_TSOMSK_F_TCPMSKF_MASK I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT)
1230
316
 #define I40E_GLLAN_TSOMSK_L 0x000442E0 /* Reset: CORER */
1231
-#define I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT 0
1232
-#define I40E_GLLAN_TSOMSK_L_TCPMSKL_MASK I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT)
1233
317
 #define I40E_GLLAN_TSOMSK_M 0x000442DC /* Reset: CORER */
1234
-#define I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT 0
1235
-#define I40E_GLLAN_TSOMSK_M_TCPMSKM_MASK I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT)
1236
318
 #define I40E_GLLAN_TXPRE_QDIS(_i) (0x000e6500 + ((_i) * 4)) /* _i=0...11 */ /* Reset: CORER */
1237
-#define I40E_GLLAN_TXPRE_QDIS_MAX_INDEX 11
1238
319
 #define I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT 0
1239
320
 #define I40E_GLLAN_TXPRE_QDIS_QINDX_MASK I40E_MASK(0x7FF, I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT)
1240
-#define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT 16
1241
-#define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT)
1242
321
 #define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT 30
1243
322
 #define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT)
1244
323
 #define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31
1245
-#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT)
324
+#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK I40E_MASK(0x1u, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT)
1246
325
 #define I40E_PFLAN_QALLOC 0x001C0400 /* Reset: CORER */
1247
326
 #define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0
1248
327
 #define I40E_PFLAN_QALLOC_FIRSTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_FIRSTQ_SHIFT)
1249
328
 #define I40E_PFLAN_QALLOC_LASTQ_SHIFT 16
1250
329
 #define I40E_PFLAN_QALLOC_LASTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_LASTQ_SHIFT)
1251
330
 #define I40E_PFLAN_QALLOC_VALID_SHIFT 31
1252
-#define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1, I40E_PFLAN_QALLOC_VALID_SHIFT)
331
+#define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PFLAN_QALLOC_VALID_SHIFT)
1253
332
 #define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */
1254
-#define I40E_QRX_ENA_MAX_INDEX 1535
1255
333
 #define I40E_QRX_ENA_QENA_REQ_SHIFT 0
1256
334
 #define I40E_QRX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_REQ_SHIFT)
1257
-#define I40E_QRX_ENA_FAST_QDIS_SHIFT 1
1258
-#define I40E_QRX_ENA_FAST_QDIS_MASK I40E_MASK(0x1, I40E_QRX_ENA_FAST_QDIS_SHIFT)
1259
335
 #define I40E_QRX_ENA_QENA_STAT_SHIFT 2
1260
336
 #define I40E_QRX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_STAT_SHIFT)
1261
337
 #define I40E_QRX_TAIL(_Q) (0x00128000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
1262
-#define I40E_QRX_TAIL_MAX_INDEX 1535
1263
-#define I40E_QRX_TAIL_TAIL_SHIFT 0
1264
-#define I40E_QRX_TAIL_TAIL_MASK I40E_MASK(0x1FFF, I40E_QRX_TAIL_TAIL_SHIFT)
1265
338
 #define I40E_QTX_CTL(_Q) (0x00104000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
1266
-#define I40E_QTX_CTL_MAX_INDEX 1535
1267
339
 #define I40E_QTX_CTL_PFVF_Q_SHIFT 0
1268
340
 #define I40E_QTX_CTL_PFVF_Q_MASK I40E_MASK(0x3, I40E_QTX_CTL_PFVF_Q_SHIFT)
1269
341
 #define I40E_QTX_CTL_PF_INDX_SHIFT 2
..
..
@@ -1271,43 +343,22 @@
1271
343
 #define I40E_QTX_CTL_VFVM_INDX_SHIFT 7
1272
344
 #define I40E_QTX_CTL_VFVM_INDX_MASK I40E_MASK(0x1FF, I40E_QTX_CTL_VFVM_INDX_SHIFT)
1273
345
 #define I40E_QTX_ENA(_Q) (0x00100000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */
1274
-#define I40E_QTX_ENA_MAX_INDEX 1535
1275
346
 #define I40E_QTX_ENA_QENA_REQ_SHIFT 0
1276
347
 #define I40E_QTX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QTX_ENA_QENA_REQ_SHIFT)
1277
-#define I40E_QTX_ENA_FAST_QDIS_SHIFT 1
1278
-#define I40E_QTX_ENA_FAST_QDIS_MASK I40E_MASK(0x1, I40E_QTX_ENA_FAST_QDIS_SHIFT)
1279
348
 #define I40E_QTX_ENA_QENA_STAT_SHIFT 2
1280
349
 #define I40E_QTX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QTX_ENA_QENA_STAT_SHIFT)
1281
350
 #define I40E_QTX_HEAD(_Q) (0x000E4000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
1282
-#define I40E_QTX_HEAD_MAX_INDEX 1535
1283
-#define I40E_QTX_HEAD_HEAD_SHIFT 0
1284
-#define I40E_QTX_HEAD_HEAD_MASK I40E_MASK(0x1FFF, I40E_QTX_HEAD_HEAD_SHIFT)
1285
-#define I40E_QTX_HEAD_RS_PENDING_SHIFT 16
1286
-#define I40E_QTX_HEAD_RS_PENDING_MASK I40E_MASK(0x1, I40E_QTX_HEAD_RS_PENDING_SHIFT)
1287
351
 #define I40E_QTX_TAIL(_Q) (0x00108000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */
1288
-#define I40E_QTX_TAIL_MAX_INDEX 1535
1289
-#define I40E_QTX_TAIL_TAIL_SHIFT 0
1290
-#define I40E_QTX_TAIL_TAIL_MASK I40E_MASK(0x1FFF, I40E_QTX_TAIL_TAIL_SHIFT)
1291
352
 #define I40E_VPLAN_MAPENA(_VF) (0x00074000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
1292
-#define I40E_VPLAN_MAPENA_MAX_INDEX 127
1293
353
 #define I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT 0
1294
354
 #define I40E_VPLAN_MAPENA_TXRX_ENA_MASK I40E_MASK(0x1, I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT)
1295
355
 #define I40E_VPLAN_QTABLE(_i, _VF) (0x00070000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: VFR */
1296
-#define I40E_VPLAN_QTABLE_MAX_INDEX 15
1297
356
 #define I40E_VPLAN_QTABLE_QINDEX_SHIFT 0
1298
357
 #define I40E_VPLAN_QTABLE_QINDEX_MASK I40E_MASK(0x7FF, I40E_VPLAN_QTABLE_QINDEX_SHIFT)
1299
358
 #define I40E_VSILAN_QBASE(_VSI) (0x0020C800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */
1300
-#define I40E_VSILAN_QBASE_MAX_INDEX 383
1301
-#define I40E_VSILAN_QBASE_VSIBASE_SHIFT 0
1302
-#define I40E_VSILAN_QBASE_VSIBASE_MASK I40E_MASK(0x7FF, I40E_VSILAN_QBASE_VSIBASE_SHIFT)
1303
359
 #define I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT 11
1304
360
 #define I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK I40E_MASK(0x1, I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT)
1305
361
 #define I40E_VSILAN_QTABLE(_i, _VSI) (0x00200000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...7, _VSI=0...383 */ /* Reset: PFR */
1306
-#define I40E_VSILAN_QTABLE_MAX_INDEX 7
1307
-#define I40E_VSILAN_QTABLE_QINDEX_0_SHIFT 0
1308
-#define I40E_VSILAN_QTABLE_QINDEX_0_MASK I40E_MASK(0x7FF, I40E_VSILAN_QTABLE_QINDEX_0_SHIFT)
1309
-#define I40E_VSILAN_QTABLE_QINDEX_1_SHIFT 16
1310
-#define I40E_VSILAN_QTABLE_QINDEX_1_MASK I40E_MASK(0x7FF, I40E_VSILAN_QTABLE_QINDEX_1_SHIFT)
1311
362
 #define I40E_PRTGL_SAH 0x001E2140 /* Reset: GLOBR */
1312
363
 #define I40E_PRTGL_SAH_FC_SAH_SHIFT 0
1313
364
 #define I40E_PRTGL_SAH_FC_SAH_MASK I40E_MASK(0xFFFF, I40E_PRTGL_SAH_FC_SAH_SHIFT)
..
..
@@ -1316,789 +367,47 @@
1316
367
 #define I40E_PRTGL_SAL 0x001E2120 /* Reset: GLOBR */
1317
368
 #define I40E_PRTGL_SAL_FC_SAL_SHIFT 0
1318
369
 #define I40E_PRTGL_SAL_FC_SAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTGL_SAL_FC_SAL_SHIFT)
1319
-#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP 0x001E30E0 /* Reset: GLOBR */
1320
-#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT 0
1321
-#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_MASK I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT)
1322
-#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP 0x001E3260 /* Reset: GLOBR */
1323
-#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT 0
1324
-#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_MASK I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT)
1325
-#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP 0x001E32E0 /* Reset: GLOBR */
1326
-#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT 0
1327
-#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_MASK I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT)
1328
-#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL 0x001E3360 /* Reset: GLOBR */
1329
-#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT 0
1330
-#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_MASK I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT)
1331
-#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1 0x001E3110 /* Reset: GLOBR */
1332
-#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT 0
1333
-#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT)
1334
-#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2 0x001E3120 /* Reset: GLOBR */
1335
-#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT 0
1336
-#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT)
1337
-#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE 0x001E30C0 /* Reset: GLOBR */
1338
-#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT 0
1339
-#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_MASK I40E_MASK(0x1FF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT)
1340
-#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1 0x001E3140 /* Reset: GLOBR */
1341
-#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT 0
1342
-#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT)
1343
-#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2 0x001E3150 /* Reset: GLOBR */
1344
-#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT 0
1345
-#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT)
1346
-#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE 0x001E30D0 /* Reset: GLOBR */
1347
-#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT 0
1348
-#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_MASK I40E_MASK(0x1FF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT)
1349
-#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i) (0x001E3370 + ((_i) * 16)) /* _i=0...8 */ /* Reset: GLOBR */
1350
-#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8
1351
-#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT 0
1352
-#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT)
1353
-#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3400 + ((_i) * 16)) /* _i=0...8 */ /* Reset: GLOBR */
1354
-#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX 8
1355
-#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT 0
1356
-#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT)
1357
-#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1 0x001E34B0 /* Reset: GLOBR */
1358
-#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT 0
1359
-#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT)
1360
-#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2 0x001E34C0 /* Reset: GLOBR */
1361
-#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT 0
1362
-#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT)
1363
-#define I40E_PRTMAC_PCS_XAUI_SWAP_A 0x0008C480 /* Reset: GLOBR */
1364
-#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT 0
1365
-#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT)
1366
-#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT 2
1367
-#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT)
1368
-#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_SHIFT 4
1369
-#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_SHIFT)
1370
-#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_SHIFT 6
1371
-#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_SHIFT)
1372
-#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_SHIFT 8
1373
-#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_SHIFT)
1374
-#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_SHIFT 10
1375
-#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_SHIFT)
1376
-#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT 12
1377
-#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT)
1378
-#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT 14
1379
-#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT)
1380
-#define I40E_PRTMAC_PCS_XAUI_SWAP_B 0x0008C484 /* Reset: GLOBR */
1381
-#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT 0
1382
-#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT)
1383
-#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT 2
1384
-#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT)
1385
-#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_SHIFT 4
1386
-#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_SHIFT)
1387
-#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_SHIFT 6
1388
-#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_SHIFT)
1389
-#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_SHIFT 8
1390
-#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_SHIFT)
1391
-#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_SHIFT 10
1392
-#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_SHIFT)
1393
-#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT 12
1394
-#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT)
1395
-#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT 14
1396
-#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT)
1397
-#define I40E_GL_FWRESETCNT 0x00083100 /* Reset: POR */
1398
-#define I40E_GL_FWRESETCNT_FWRESETCNT_SHIFT 0
1399
-#define I40E_GL_FWRESETCNT_FWRESETCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FWRESETCNT_FWRESETCNT_SHIFT)
1400
-#define I40E_GL_MNG_FWSM 0x000B6134 /* Reset: POR */
1401
-#define I40E_GL_MNG_FWSM_FW_MODES_SHIFT 0
1402
-#define I40E_GL_MNG_FWSM_FW_MODES_MASK I40E_MASK(0x3, I40E_GL_MNG_FWSM_FW_MODES_SHIFT)
1403
-#define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT 10
1404
-#define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT)
1405
-#define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT 11
1406
-#define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_MASK I40E_MASK(0xF, I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT)
1407
-#define I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT 15
1408
-#define I40E_GL_MNG_FWSM_FW_STATUS_VALID_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT)
1409
-#define I40E_GL_MNG_FWSM_RESET_CNT_SHIFT 16
1410
-#define I40E_GL_MNG_FWSM_RESET_CNT_MASK I40E_MASK(0x7, I40E_GL_MNG_FWSM_RESET_CNT_SHIFT)
1411
-#define I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT 19
1412
-#define I40E_GL_MNG_FWSM_EXT_ERR_IND_MASK I40E_MASK(0x3F, I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT)
1413
-#define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT 26
1414
-#define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT)
1415
-#define I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT 27
1416
-#define I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT)
1417
-#define I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT 28
1418
-#define I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT)
1419
-#define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT 29
1420
-#define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT)
1421
-#define I40E_GL_MNG_HWARB_CTRL 0x000B6130 /* Reset: POR */
1422
-#define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT 0
1423
-#define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_MASK I40E_MASK(0x1, I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT)
1424
-#define I40E_PRT_MNG_FTFT_DATA(_i) (0x000852A0 + ((_i) * 32)) /* _i=0...31 */ /* Reset: POR */
1425
-#define I40E_PRT_MNG_FTFT_DATA_MAX_INDEX 31
1426
-#define I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT 0
1427
-#define I40E_PRT_MNG_FTFT_DATA_DWORD_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT)
1428
-#define I40E_PRT_MNG_FTFT_LENGTH 0x00085260 /* Reset: POR */
1429
-#define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT 0
1430
-#define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_MASK I40E_MASK(0xFF, I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT)
1431
-#define I40E_PRT_MNG_FTFT_MASK(_i) (0x00085160 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */
1432
-#define I40E_PRT_MNG_FTFT_MASK_MAX_INDEX 7
1433
-#define I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT 0
1434
-#define I40E_PRT_MNG_FTFT_MASK_MASK_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT)
1435
-#define I40E_PRT_MNG_MANC 0x00256A20 /* Reset: POR */
1436
-#define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT 0
1437
-#define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT)
1438
-#define I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT 1
1439
-#define I40E_PRT_MNG_MANC_NCSI_DISCARD_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT)
1440
-#define I40E_PRT_MNG_MANC_RCV_TCO_EN_SHIFT 17
1441
-#define I40E_PRT_MNG_MANC_RCV_TCO_EN_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_RCV_TCO_EN_SHIFT)
1442
-#define I40E_PRT_MNG_MANC_RCV_ALL_SHIFT 19
1443
-#define I40E_PRT_MNG_MANC_RCV_ALL_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_RCV_ALL_SHIFT)
1444
-#define I40E_PRT_MNG_MANC_FIXED_NET_TYPE_SHIFT 25
1445
-#define I40E_PRT_MNG_MANC_FIXED_NET_TYPE_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_FIXED_NET_TYPE_SHIFT)
1446
-#define I40E_PRT_MNG_MANC_NET_TYPE_SHIFT 26
1447
-#define I40E_PRT_MNG_MANC_NET_TYPE_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_NET_TYPE_SHIFT)
1448
-#define I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT 28
1449
-#define I40E_PRT_MNG_MANC_EN_BMC2OS_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT)
1450
-#define I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT 29
1451
-#define I40E_PRT_MNG_MANC_EN_BMC2NET_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT)
1452
-#define I40E_PRT_MNG_MAVTV(_i) (0x00255900 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */
1453
-#define I40E_PRT_MNG_MAVTV_MAX_INDEX 7
1454
-#define I40E_PRT_MNG_MAVTV_VID_SHIFT 0
1455
-#define I40E_PRT_MNG_MAVTV_VID_MASK I40E_MASK(0xFFF, I40E_PRT_MNG_MAVTV_VID_SHIFT)
1456
-#define I40E_PRT_MNG_MDEF(_i) (0x00255D00 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */
1457
-#define I40E_PRT_MNG_MDEF_MAX_INDEX 7
1458
-#define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT 0
1459
-#define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT)
1460
-#define I40E_PRT_MNG_MDEF_BROADCAST_AND_SHIFT 4
1461
-#define I40E_PRT_MNG_MDEF_BROADCAST_AND_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_BROADCAST_AND_SHIFT)
1462
-#define I40E_PRT_MNG_MDEF_VLAN_AND_SHIFT 5
1463
-#define I40E_PRT_MNG_MDEF_VLAN_AND_MASK I40E_MASK(0xFF, I40E_PRT_MNG_MDEF_VLAN_AND_SHIFT)
1464
-#define I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_SHIFT 13
1465
-#define I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_SHIFT)
1466
-#define I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_SHIFT 17
1467
-#define I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_SHIFT)
1468
-#define I40E_PRT_MNG_MDEF_MAC_EXACT_OR_SHIFT 21
1469
-#define I40E_PRT_MNG_MDEF_MAC_EXACT_OR_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_MAC_EXACT_OR_SHIFT)
1470
-#define I40E_PRT_MNG_MDEF_BROADCAST_OR_SHIFT 25
1471
-#define I40E_PRT_MNG_MDEF_BROADCAST_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_BROADCAST_OR_SHIFT)
1472
-#define I40E_PRT_MNG_MDEF_MULTICAST_AND_SHIFT 26
1473
-#define I40E_PRT_MNG_MDEF_MULTICAST_AND_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_MULTICAST_AND_SHIFT)
1474
-#define I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_SHIFT 27
1475
-#define I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_SHIFT)
1476
-#define I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_SHIFT 28
1477
-#define I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_SHIFT)
1478
-#define I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_SHIFT 29
1479
-#define I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_SHIFT)
1480
-#define I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT 30
1481
-#define I40E_PRT_MNG_MDEF_PORT_0X298_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT)
1482
-#define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT 31
1483
-#define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT)
1484
-#define I40E_PRT_MNG_MDEF_EXT(_i) (0x00255F00 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */
1485
-#define I40E_PRT_MNG_MDEF_EXT_MAX_INDEX 7
1486
-#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT 0
1487
-#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT)
1488
-#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_SHIFT 4
1489
-#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_SHIFT)
1490
-#define I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_SHIFT 8
1491
-#define I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_SHIFT)
1492
-#define I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_SHIFT 24
1493
-#define I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_SHIFT)
1494
-#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_SHIFT 25
1495
-#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_SHIFT)
1496
-#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_SHIFT 26
1497
-#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_SHIFT)
1498
-#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_SHIFT 27
1499
-#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_SHIFT)
1500
-#define I40E_PRT_MNG_MDEF_EXT_ICMP_OR_SHIFT 28
1501
-#define I40E_PRT_MNG_MDEF_EXT_ICMP_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_ICMP_OR_SHIFT)
1502
-#define I40E_PRT_MNG_MDEF_EXT_MLD_SHIFT 29
1503
-#define I40E_PRT_MNG_MDEF_EXT_MLD_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_MLD_SHIFT)
1504
-#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT 30
1505
-#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT)
1506
-#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT 31
1507
-#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT)
1508
-#define I40E_PRT_MNG_MDEFVSI(_i) (0x00256580 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
1509
-#define I40E_PRT_MNG_MDEFVSI_MAX_INDEX 3
1510
-#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT 0
1511
-#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT)
1512
-#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT 16
1513
-#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT)
1514
-#define I40E_PRT_MNG_METF(_i) (0x00256780 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
1515
-#define I40E_PRT_MNG_METF_MAX_INDEX 3
1516
-#define I40E_PRT_MNG_METF_ETYPE_SHIFT 0
1517
-#define I40E_PRT_MNG_METF_ETYPE_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_METF_ETYPE_SHIFT)
1518
-#define I40E_PRT_MNG_METF_POLARITY_SHIFT 30
1519
-#define I40E_PRT_MNG_METF_POLARITY_MASK I40E_MASK(0x1, I40E_PRT_MNG_METF_POLARITY_SHIFT)
1520
-#define I40E_PRT_MNG_MFUTP(_i) (0x00254E00 + ((_i) * 32)) /* _i=0...15 */ /* Reset: POR */
1521
-#define I40E_PRT_MNG_MFUTP_MAX_INDEX 15
1522
-#define I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT 0
1523
-#define I40E_PRT_MNG_MFUTP_MFUTP_N_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT)
1524
-#define I40E_PRT_MNG_MFUTP_UDP_SHIFT 16
1525
-#define I40E_PRT_MNG_MFUTP_UDP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MFUTP_UDP_SHIFT)
1526
-#define I40E_PRT_MNG_MFUTP_TCP_SHIFT 17
1527
-#define I40E_PRT_MNG_MFUTP_TCP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MFUTP_TCP_SHIFT)
1528
-#define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT 18
1529
-#define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_MASK I40E_MASK(0x1, I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT)
1530
-#define I40E_PRT_MNG_MIPAF4(_i) (0x00256280 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
1531
-#define I40E_PRT_MNG_MIPAF4_MAX_INDEX 3
1532
-#define I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT 0
1533
-#define I40E_PRT_MNG_MIPAF4_MIPAF_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT)
1534
-#define I40E_PRT_MNG_MIPAF6(_i) (0x00254200 + ((_i) * 32)) /* _i=0...15 */ /* Reset: POR */
1535
-#define I40E_PRT_MNG_MIPAF6_MAX_INDEX 15
1536
-#define I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT 0
1537
-#define I40E_PRT_MNG_MIPAF6_MIPAF_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT)
1538
-#define I40E_PRT_MNG_MMAH(_i) (0x00256380 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
1539
-#define I40E_PRT_MNG_MMAH_MAX_INDEX 3
1540
-#define I40E_PRT_MNG_MMAH_MMAH_SHIFT 0
1541
-#define I40E_PRT_MNG_MMAH_MMAH_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MMAH_MMAH_SHIFT)
1542
-#define I40E_PRT_MNG_MMAL(_i) (0x00256480 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
1543
-#define I40E_PRT_MNG_MMAL_MAX_INDEX 3
1544
-#define I40E_PRT_MNG_MMAL_MMAL_SHIFT 0
1545
-#define I40E_PRT_MNG_MMAL_MMAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MMAL_MMAL_SHIFT)
1546
-#define I40E_PRT_MNG_MNGONLY 0x00256A60 /* Reset: POR */
1547
-#define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT 0
1548
-#define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_MASK I40E_MASK(0xFF, I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT)
1549
-#define I40E_PRT_MNG_MSFM 0x00256AA0 /* Reset: POR */
1550
-#define I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT 0
1551
-#define I40E_PRT_MNG_MSFM_PORT_26F_UDP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT)
1552
-#define I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT 1
1553
-#define I40E_PRT_MNG_MSFM_PORT_26F_TCP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT)
1554
-#define I40E_PRT_MNG_MSFM_PORT_298_UDP_SHIFT 2
1555
-#define I40E_PRT_MNG_MSFM_PORT_298_UDP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_298_UDP_SHIFT)
1556
-#define I40E_PRT_MNG_MSFM_PORT_298_TCP_SHIFT 3
1557
-#define I40E_PRT_MNG_MSFM_PORT_298_TCP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_298_TCP_SHIFT)
1558
-#define I40E_PRT_MNG_MSFM_IPV6_0_MASK_SHIFT 4
1559
-#define I40E_PRT_MNG_MSFM_IPV6_0_MASK_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_0_MASK_SHIFT)
1560
-#define I40E_PRT_MNG_MSFM_IPV6_1_MASK_SHIFT 5
1561
-#define I40E_PRT_MNG_MSFM_IPV6_1_MASK_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_1_MASK_SHIFT)
1562
-#define I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT 6
1563
-#define I40E_PRT_MNG_MSFM_IPV6_2_MASK_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT)
1564
-#define I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT 7
1565
-#define I40E_PRT_MNG_MSFM_IPV6_3_MASK_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT)
1566
-#define I40E_MSIX_PBA(_i) (0x00001000 + ((_i) * 4)) /* _i=0...5 */ /* Reset: FLR */
1567
-#define I40E_MSIX_PBA_MAX_INDEX 5
1568
-#define I40E_MSIX_PBA_PENBIT_SHIFT 0
1569
-#define I40E_MSIX_PBA_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_MSIX_PBA_PENBIT_SHIFT)
1570
-#define I40E_MSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */
1571
-#define I40E_MSIX_TADD_MAX_INDEX 128
1572
-#define I40E_MSIX_TADD_MSIXTADD10_SHIFT 0
1573
-#define I40E_MSIX_TADD_MSIXTADD10_MASK I40E_MASK(0x3, I40E_MSIX_TADD_MSIXTADD10_SHIFT)
1574
-#define I40E_MSIX_TADD_MSIXTADD_SHIFT 2
1575
-#define I40E_MSIX_TADD_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_MSIX_TADD_MSIXTADD_SHIFT)
1576
-#define I40E_MSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */
1577
-#define I40E_MSIX_TMSG_MAX_INDEX 128
1578
-#define I40E_MSIX_TMSG_MSIXTMSG_SHIFT 0
1579
-#define I40E_MSIX_TMSG_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_MSIX_TMSG_MSIXTMSG_SHIFT)
1580
-#define I40E_MSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */
1581
-#define I40E_MSIX_TUADD_MAX_INDEX 128
1582
-#define I40E_MSIX_TUADD_MSIXTUADD_SHIFT 0
1583
-#define I40E_MSIX_TUADD_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_MSIX_TUADD_MSIXTUADD_SHIFT)
1584
-#define I40E_MSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */
1585
-#define I40E_MSIX_TVCTRL_MAX_INDEX 128
1586
-#define I40E_MSIX_TVCTRL_MASK_SHIFT 0
1587
-#define I40E_MSIX_TVCTRL_MASK_MASK I40E_MASK(0x1, I40E_MSIX_TVCTRL_MASK_SHIFT)
1588
-#define I40E_VFMSIX_PBA1(_i) (0x00002000 + ((_i) * 4)) /* _i=0...19 */ /* Reset: VFLR */
1589
-#define I40E_VFMSIX_PBA1_MAX_INDEX 19
1590
-#define I40E_VFMSIX_PBA1_PENBIT_SHIFT 0
1591
-#define I40E_VFMSIX_PBA1_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA1_PENBIT_SHIFT)
1592
-#define I40E_VFMSIX_TADD1(_i) (0x00002100 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
1593
-#define I40E_VFMSIX_TADD1_MAX_INDEX 639
1594
-#define I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT 0
1595
-#define I40E_VFMSIX_TADD1_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT)
1596
-#define I40E_VFMSIX_TADD1_MSIXTADD_SHIFT 2
1597
-#define I40E_VFMSIX_TADD1_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD1_MSIXTADD_SHIFT)
1598
-#define I40E_VFMSIX_TMSG1(_i) (0x00002108 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
1599
-#define I40E_VFMSIX_TMSG1_MAX_INDEX 639
1600
-#define I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT 0
1601
-#define I40E_VFMSIX_TMSG1_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT)
1602
-#define I40E_VFMSIX_TUADD1(_i) (0x00002104 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
1603
-#define I40E_VFMSIX_TUADD1_MAX_INDEX 639
1604
-#define I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT 0
1605
-#define I40E_VFMSIX_TUADD1_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT)
1606
-#define I40E_VFMSIX_TVCTRL1(_i) (0x0000210C + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
1607
-#define I40E_VFMSIX_TVCTRL1_MAX_INDEX 639
1608
-#define I40E_VFMSIX_TVCTRL1_MASK_SHIFT 0
1609
-#define I40E_VFMSIX_TVCTRL1_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL1_MASK_SHIFT)
1610
370
 #define I40E_GLNVM_FLA 0x000B6108 /* Reset: POR */
1611
-#define I40E_GLNVM_FLA_FL_SCK_SHIFT 0
1612
-#define I40E_GLNVM_FLA_FL_SCK_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_SCK_SHIFT)
1613
-#define I40E_GLNVM_FLA_FL_CE_SHIFT 1
1614
-#define I40E_GLNVM_FLA_FL_CE_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_CE_SHIFT)
1615
-#define I40E_GLNVM_FLA_FL_SI_SHIFT 2
1616
-#define I40E_GLNVM_FLA_FL_SI_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_SI_SHIFT)
1617
-#define I40E_GLNVM_FLA_FL_SO_SHIFT 3
1618
-#define I40E_GLNVM_FLA_FL_SO_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_SO_SHIFT)
1619
-#define I40E_GLNVM_FLA_FL_REQ_SHIFT 4
1620
-#define I40E_GLNVM_FLA_FL_REQ_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_REQ_SHIFT)
1621
-#define I40E_GLNVM_FLA_FL_GNT_SHIFT 5
1622
-#define I40E_GLNVM_FLA_FL_GNT_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_GNT_SHIFT)
1623
371
 #define I40E_GLNVM_FLA_LOCKED_SHIFT 6
1624
372
 #define I40E_GLNVM_FLA_LOCKED_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_LOCKED_SHIFT)
1625
-#define I40E_GLNVM_FLA_FL_SADDR_SHIFT 18
1626
-#define I40E_GLNVM_FLA_FL_SADDR_MASK I40E_MASK(0x7FF, I40E_GLNVM_FLA_FL_SADDR_SHIFT)
1627
-#define I40E_GLNVM_FLA_FL_BUSY_SHIFT 30
1628
-#define I40E_GLNVM_FLA_FL_BUSY_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_BUSY_SHIFT)
1629
-#define I40E_GLNVM_FLA_FL_DER_SHIFT 31
1630
-#define I40E_GLNVM_FLA_FL_DER_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_DER_SHIFT)
1631
-#define I40E_GLNVM_FLASHID 0x000B6104 /* Reset: POR */
1632
-#define I40E_GLNVM_FLASHID_FLASHID_SHIFT 0
1633
-#define I40E_GLNVM_FLASHID_FLASHID_MASK I40E_MASK(0xFFFFFF, I40E_GLNVM_FLASHID_FLASHID_SHIFT)
1634
-#define I40E_GLNVM_FLASHID_FLEEP_PERF_SHIFT 31
1635
-#define I40E_GLNVM_FLASHID_FLEEP_PERF_MASK I40E_MASK(0x1, I40E_GLNVM_FLASHID_FLEEP_PERF_SHIFT)
1636
373
 #define I40E_GLNVM_GENS 0x000B6100 /* Reset: POR */
1637
-#define I40E_GLNVM_GENS_NVM_PRES_SHIFT 0
1638
-#define I40E_GLNVM_GENS_NVM_PRES_MASK I40E_MASK(0x1, I40E_GLNVM_GENS_NVM_PRES_SHIFT)
1639
374
 #define I40E_GLNVM_GENS_SR_SIZE_SHIFT 5
1640
375
 #define I40E_GLNVM_GENS_SR_SIZE_MASK I40E_MASK(0x7, I40E_GLNVM_GENS_SR_SIZE_SHIFT)
1641
-#define I40E_GLNVM_GENS_BANK1VAL_SHIFT 8
1642
-#define I40E_GLNVM_GENS_BANK1VAL_MASK I40E_MASK(0x1, I40E_GLNVM_GENS_BANK1VAL_SHIFT)
1643
-#define I40E_GLNVM_GENS_ALT_PRST_SHIFT 23
1644
-#define I40E_GLNVM_GENS_ALT_PRST_MASK I40E_MASK(0x1, I40E_GLNVM_GENS_ALT_PRST_SHIFT)
1645
-#define I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT 25
1646
-#define I40E_GLNVM_GENS_FL_AUTO_RD_MASK I40E_MASK(0x1, I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT)
1647
-#define I40E_GLNVM_PROTCSR(_i) (0x000B6010 + ((_i) * 4)) /* _i=0...59 */ /* Reset: POR */
1648
-#define I40E_GLNVM_PROTCSR_MAX_INDEX 59
1649
-#define I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT 0
1650
-#define I40E_GLNVM_PROTCSR_ADDR_BLOCK_MASK I40E_MASK(0xFFFFFF, I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT)
1651
376
 #define I40E_GLNVM_SRCTL 0x000B6110 /* Reset: POR */
1652
-#define I40E_GLNVM_SRCTL_SRBUSY_SHIFT 0
1653
-#define I40E_GLNVM_SRCTL_SRBUSY_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_SRBUSY_SHIFT)
1654
377
 #define I40E_GLNVM_SRCTL_ADDR_SHIFT 14
1655
-#define I40E_GLNVM_SRCTL_ADDR_MASK I40E_MASK(0x7FFF, I40E_GLNVM_SRCTL_ADDR_SHIFT)
1656
-#define I40E_GLNVM_SRCTL_WRITE_SHIFT 29
1657
-#define I40E_GLNVM_SRCTL_WRITE_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_WRITE_SHIFT)
1658
378
 #define I40E_GLNVM_SRCTL_START_SHIFT 30
1659
-#define I40E_GLNVM_SRCTL_START_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_START_SHIFT)
1660
379
 #define I40E_GLNVM_SRCTL_DONE_SHIFT 31
1661
-#define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_DONE_SHIFT)
380
+#define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1u, I40E_GLNVM_SRCTL_DONE_SHIFT)
1662
381
 #define I40E_GLNVM_SRDATA 0x000B6114 /* Reset: POR */
1663
-#define I40E_GLNVM_SRDATA_WRDATA_SHIFT 0
1664
-#define I40E_GLNVM_SRDATA_WRDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_WRDATA_SHIFT)
1665
382
 #define I40E_GLNVM_SRDATA_RDDATA_SHIFT 16
1666
383
 #define I40E_GLNVM_SRDATA_RDDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_RDDATA_SHIFT)
1667
384
 #define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */
1668
-#define I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT 0
1669
-#define I40E_GLNVM_ULD_CONF_PCIR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT)
1670
-#define I40E_GLNVM_ULD_CONF_PCIRTL_DONE_SHIFT 1
1671
-#define I40E_GLNVM_ULD_CONF_PCIRTL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIRTL_DONE_SHIFT)
1672
-#define I40E_GLNVM_ULD_CONF_LCB_DONE_SHIFT 2
1673
-#define I40E_GLNVM_ULD_CONF_LCB_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_LCB_DONE_SHIFT)
1674
385
 #define I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT 3
1675
386
 #define I40E_GLNVM_ULD_CONF_CORE_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT)
1676
387
 #define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT 4
1677
388
 #define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT)
1678
-#define I40E_GLNVM_ULD_CONF_POR_DONE_SHIFT 5
1679
-#define I40E_GLNVM_ULD_CONF_POR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_POR_DONE_SHIFT)
1680
-#define I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_SHIFT 6
1681
-#define I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_SHIFT)
1682
-#define I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_SHIFT 7
1683
-#define I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_SHIFT)
1684
-#define I40E_GLNVM_ULD_CONF_EMP_DONE_SHIFT 8
1685
-#define I40E_GLNVM_ULD_CONF_EMP_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_EMP_DONE_SHIFT)
1686
-#define I40E_GLNVM_ULD_CONF_PCIALT_DONE_SHIFT 9
1687
-#define I40E_GLNVM_ULD_CONF_PCIALT_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIALT_DONE_SHIFT)
1688
-#define I40E_GLPCI_BYTCTH 0x0009C484 /* Reset: PCIR */
1689
-#define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT 0
1690
-#define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT)
1691
-#define I40E_GLPCI_BYTCTL 0x0009C488 /* Reset: PCIR */
1692
-#define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT 0
1693
-#define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT)
1694
-#define I40E_GLPCI_CAPCTRL 0x000BE4A4 /* Reset: PCIR */
1695
-#define I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT 0
1696
-#define I40E_GLPCI_CAPCTRL_VPD_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT)
1697
389
 #define I40E_GLPCI_CAPSUP 0x000BE4A8 /* Reset: PCIR */
1698
-#define I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT 0
1699
-#define I40E_GLPCI_CAPSUP_PCIE_VER_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT)
1700
-#define I40E_GLPCI_CAPSUP_LTR_EN_SHIFT 2
1701
-#define I40E_GLPCI_CAPSUP_LTR_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_LTR_EN_SHIFT)
1702
-#define I40E_GLPCI_CAPSUP_TPH_EN_SHIFT 3
1703
-#define I40E_GLPCI_CAPSUP_TPH_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_TPH_EN_SHIFT)
1704
390
 #define I40E_GLPCI_CAPSUP_ARI_EN_SHIFT 4
1705
391
 #define I40E_GLPCI_CAPSUP_ARI_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ARI_EN_SHIFT)
1706
-#define I40E_GLPCI_CAPSUP_IOV_EN_SHIFT 5
1707
-#define I40E_GLPCI_CAPSUP_IOV_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_IOV_EN_SHIFT)
1708
-#define I40E_GLPCI_CAPSUP_ACS_EN_SHIFT 6
1709
-#define I40E_GLPCI_CAPSUP_ACS_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ACS_EN_SHIFT)
1710
-#define I40E_GLPCI_CAPSUP_SEC_EN_SHIFT 7
1711
-#define I40E_GLPCI_CAPSUP_SEC_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_SEC_EN_SHIFT)
1712
-#define I40E_GLPCI_CAPSUP_ECRC_GEN_EN_SHIFT 16
1713
-#define I40E_GLPCI_CAPSUP_ECRC_GEN_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ECRC_GEN_EN_SHIFT)
1714
-#define I40E_GLPCI_CAPSUP_ECRC_CHK_EN_SHIFT 17
1715
-#define I40E_GLPCI_CAPSUP_ECRC_CHK_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ECRC_CHK_EN_SHIFT)
1716
-#define I40E_GLPCI_CAPSUP_IDO_EN_SHIFT 18
1717
-#define I40E_GLPCI_CAPSUP_IDO_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_IDO_EN_SHIFT)
1718
-#define I40E_GLPCI_CAPSUP_MSI_MASK_SHIFT 19
1719
-#define I40E_GLPCI_CAPSUP_MSI_MASK_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_MSI_MASK_SHIFT)
1720
-#define I40E_GLPCI_CAPSUP_CSR_CONF_EN_SHIFT 20
1721
-#define I40E_GLPCI_CAPSUP_CSR_CONF_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_CSR_CONF_EN_SHIFT)
1722
-#define I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT 30
1723
-#define I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT)
1724
-#define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT 31
1725
-#define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT)
1726
-#define I40E_GLPCI_CNF 0x000BE4C0 /* Reset: POR */
1727
-#define I40E_GLPCI_CNF_FLEX10_SHIFT 1
1728
-#define I40E_GLPCI_CNF_FLEX10_MASK I40E_MASK(0x1, I40E_GLPCI_CNF_FLEX10_SHIFT)
1729
-#define I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT 2
1730
-#define I40E_GLPCI_CNF_WAKE_PIN_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT)
1731
392
 #define I40E_GLPCI_CNF2 0x000BE494 /* Reset: PCIR */
1732
-#define I40E_GLPCI_CNF2_RO_DIS_SHIFT 0
1733
-#define I40E_GLPCI_CNF2_RO_DIS_MASK I40E_MASK(0x1, I40E_GLPCI_CNF2_RO_DIS_SHIFT)
1734
-#define I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT 1
1735
-#define I40E_GLPCI_CNF2_CACHELINE_SIZE_MASK I40E_MASK(0x1, I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT)
1736
393
 #define I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT 2
1737
394
 #define I40E_GLPCI_CNF2_MSI_X_PF_N_MASK I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT)
1738
395
 #define I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT 13
1739
396
 #define I40E_GLPCI_CNF2_MSI_X_VF_N_MASK I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT)
1740
-#define I40E_GLPCI_DREVID 0x0009C480 /* Reset: PCIR */
1741
-#define I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT 0
1742
-#define I40E_GLPCI_DREVID_DEFAULT_REVID_MASK I40E_MASK(0xFF, I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT)
1743
-#define I40E_GLPCI_GSCL_1 0x0009C48C /* Reset: PCIR */
1744
-#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT 0
1745
-#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT)
1746
-#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT 1
1747
-#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT)
1748
-#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_SHIFT 2
1749
-#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_SHIFT)
1750
-#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_SHIFT 3
1751
-#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_SHIFT)
1752
-#define I40E_GLPCI_GSCL_1_LBC_ENABLE_0_SHIFT 4
1753
-#define I40E_GLPCI_GSCL_1_LBC_ENABLE_0_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_0_SHIFT)
1754
-#define I40E_GLPCI_GSCL_1_LBC_ENABLE_1_SHIFT 5
1755
-#define I40E_GLPCI_GSCL_1_LBC_ENABLE_1_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_1_SHIFT)
1756
-#define I40E_GLPCI_GSCL_1_LBC_ENABLE_2_SHIFT 6
1757
-#define I40E_GLPCI_GSCL_1_LBC_ENABLE_2_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_2_SHIFT)
1758
-#define I40E_GLPCI_GSCL_1_LBC_ENABLE_3_SHIFT 7
1759
-#define I40E_GLPCI_GSCL_1_LBC_ENABLE_3_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_3_SHIFT)
1760
-#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_SHIFT 8
1761
-#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_SHIFT)
1762
-#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_SHIFT 9
1763
-#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_MASK I40E_MASK(0x1F, I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_SHIFT)
1764
-#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_SHIFT 14
1765
-#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_SHIFT)
1766
-#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_SHIFT 15
1767
-#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_MASK I40E_MASK(0x1F, I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_SHIFT)
1768
-#define I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_SHIFT 28
1769
-#define I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_SHIFT)
1770
-#define I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_SHIFT 29
1771
-#define I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_SHIFT)
1772
-#define I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT 30
1773
-#define I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT)
1774
-#define I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT 31
1775
-#define I40E_GLPCI_GSCL_1_GIO_COUNT_START_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT)
1776
-#define I40E_GLPCI_GSCL_2 0x0009C490 /* Reset: PCIR */
1777
-#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT 0
1778
-#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT)
1779
-#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT 8
1780
-#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT)
1781
-#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT 16
1782
-#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT)
1783
-#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT 24
1784
-#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT)
1785
-#define I40E_GLPCI_GSCL_5_8(_i) (0x0009C494 + ((_i) * 4)) /* _i=0...3 */ /* Reset: PCIR */
1786
-#define I40E_GLPCI_GSCL_5_8_MAX_INDEX 3
1787
-#define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT 0
1788
-#define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_MASK I40E_MASK(0xFFFF, I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT)
1789
-#define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT 16
1790
-#define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_MASK I40E_MASK(0xFFFF, I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT)
1791
-#define I40E_GLPCI_GSCN_0_3(_i) (0x0009C4A4 + ((_i) * 4)) /* _i=0...3 */ /* Reset: PCIR */
1792
-#define I40E_GLPCI_GSCN_0_3_MAX_INDEX 3
1793
-#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT 0
1794
-#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT)
1795
397
 #define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */
1796
-#define I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT 0
1797
-#define I40E_GLPCI_LBARCTRL_PREFBAR_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT)
1798
-#define I40E_GLPCI_LBARCTRL_BAR32_SHIFT 1
1799
-#define I40E_GLPCI_LBARCTRL_BAR32_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_BAR32_SHIFT)
1800
-#define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT 3
1801
-#define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT)
1802
-#define I40E_GLPCI_LBARCTRL_RSVD_4_SHIFT 4
1803
-#define I40E_GLPCI_LBARCTRL_RSVD_4_MASK I40E_MASK(0x3, I40E_GLPCI_LBARCTRL_RSVD_4_SHIFT)
1804
398
 #define I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT 6
1805
399
 #define I40E_GLPCI_LBARCTRL_FL_SIZE_MASK I40E_MASK(0x7, I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT)
1806
-#define I40E_GLPCI_LBARCTRL_RSVD_10_SHIFT 10
1807
-#define I40E_GLPCI_LBARCTRL_RSVD_10_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_RSVD_10_SHIFT)
1808
-#define I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT 11
1809
-#define I40E_GLPCI_LBARCTRL_EXROM_SIZE_MASK I40E_MASK(0x7, I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT)
1810
-#define I40E_GLPCI_LINKCAP 0x000BE4AC /* Reset: PCIR */
1811
-#define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT 0
1812
-#define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_MASK I40E_MASK(0x3F, I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT)
1813
-#define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT 6
1814
-#define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_MASK I40E_MASK(0x7, I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT)
1815
-#define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT 9
1816
-#define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_MASK I40E_MASK(0xF, I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT)
1817
-#define I40E_GLPCI_PCIERR 0x000BE4FC /* Reset: PCIR */
1818
-#define I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT 0
1819
-#define I40E_GLPCI_PCIERR_PCIE_ERR_REP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT)
1820
-#define I40E_GLPCI_PKTCT 0x0009C4BC /* Reset: PCIR */
1821
-#define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT 0
1822
-#define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT)
1823
-#define I40E_GLPCI_PM_MUX_NPQ 0x0009C4F4 /* Reset: PCIR */
1824
-#define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT 0
1825
-#define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_MASK I40E_MASK(0x7, I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT)
1826
-#define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT 16
1827
-#define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_MASK I40E_MASK(0x1F, I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT)
1828
-#define I40E_GLPCI_PM_MUX_PFB 0x0009C4F0 /* Reset: PCIR */
1829
-#define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT 0
1830
-#define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_MASK I40E_MASK(0x1F, I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT)
1831
-#define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT 16
1832
-#define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_MASK I40E_MASK(0x7, I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT)
1833
-#define I40E_GLPCI_PMSUP 0x000BE4B0 /* Reset: PCIR */
1834
-#define I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT 0
1835
-#define I40E_GLPCI_PMSUP_ASPM_SUP_MASK I40E_MASK(0x3, I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT)
1836
-#define I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT 2
1837
-#define I40E_GLPCI_PMSUP_L0S_EXIT_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT)
1838
-#define I40E_GLPCI_PMSUP_L1_EXIT_LAT_SHIFT 5
1839
-#define I40E_GLPCI_PMSUP_L1_EXIT_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L1_EXIT_LAT_SHIFT)
1840
-#define I40E_GLPCI_PMSUP_L0S_ACC_LAT_SHIFT 8
1841
-#define I40E_GLPCI_PMSUP_L0S_ACC_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L0S_ACC_LAT_SHIFT)
1842
-#define I40E_GLPCI_PMSUP_L1_ACC_LAT_SHIFT 11
1843
-#define I40E_GLPCI_PMSUP_L1_ACC_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L1_ACC_LAT_SHIFT)
1844
-#define I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT 14
1845
-#define I40E_GLPCI_PMSUP_SLOT_CLK_MASK I40E_MASK(0x1, I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT)
1846
-#define I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT 15
1847
-#define I40E_GLPCI_PMSUP_OBFF_SUP_MASK I40E_MASK(0x3, I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT)
1848
-#define I40E_GLPCI_PQ_MAX_USED_SPC 0x0009C4EC /* Reset: PCIR */
1849
-#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT 0
1850
-#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_MASK I40E_MASK(0xFF, I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT)
1851
-#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT 8
1852
-#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_MASK I40E_MASK(0xFF, I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT)
1853
-#define I40E_GLPCI_PWRDATA 0x000BE490 /* Reset: PCIR */
1854
-#define I40E_GLPCI_PWRDATA_D0_POWER_SHIFT 0
1855
-#define I40E_GLPCI_PWRDATA_D0_POWER_MASK I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_D0_POWER_SHIFT)
1856
-#define I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT 8
1857
-#define I40E_GLPCI_PWRDATA_COMM_POWER_MASK I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT)
1858
-#define I40E_GLPCI_PWRDATA_D3_POWER_SHIFT 16
1859
-#define I40E_GLPCI_PWRDATA_D3_POWER_MASK I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_D3_POWER_SHIFT)
1860
-#define I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT 24
1861
-#define I40E_GLPCI_PWRDATA_DATA_SCALE_MASK I40E_MASK(0x3, I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT)
1862
-#define I40E_GLPCI_REVID 0x000BE4B4 /* Reset: PCIR */
1863
-#define I40E_GLPCI_REVID_NVM_REVID_SHIFT 0
1864
-#define I40E_GLPCI_REVID_NVM_REVID_MASK I40E_MASK(0xFF, I40E_GLPCI_REVID_NVM_REVID_SHIFT)
1865
-#define I40E_GLPCI_SERH 0x000BE49C /* Reset: PCIR */
1866
-#define I40E_GLPCI_SERH_SER_NUM_H_SHIFT 0
1867
-#define I40E_GLPCI_SERH_SER_NUM_H_MASK I40E_MASK(0xFFFF, I40E_GLPCI_SERH_SER_NUM_H_SHIFT)
1868
-#define I40E_GLPCI_SERL 0x000BE498 /* Reset: PCIR */
1869
-#define I40E_GLPCI_SERL_SER_NUM_L_SHIFT 0
1870
-#define I40E_GLPCI_SERL_SER_NUM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SERL_SER_NUM_L_SHIFT)
1871
-#define I40E_GLPCI_SPARE_BITS_0 0x0009C4F8 /* Reset: PCIR */
1872
-#define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT 0
1873
-#define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT)
1874
-#define I40E_GLPCI_SPARE_BITS_1 0x0009C4FC /* Reset: PCIR */
1875
-#define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT 0
1876
-#define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT)
1877
-#define I40E_GLPCI_SUBVENID 0x000BE48C /* Reset: PCIR */
1878
-#define I40E_GLPCI_SUBVENID_SUB_VEN_ID_SHIFT 0
1879
-#define I40E_GLPCI_SUBVENID_SUB_VEN_ID_MASK I40E_MASK(0xFFFF, I40E_GLPCI_SUBVENID_SUB_VEN_ID_SHIFT)
1880
-#define I40E_GLPCI_UPADD 0x000BE4F8 /* Reset: PCIR */
1881
-#define I40E_GLPCI_UPADD_ADDRESS_SHIFT 1
1882
-#define I40E_GLPCI_UPADD_ADDRESS_MASK I40E_MASK(0x7FFFFFFF, I40E_GLPCI_UPADD_ADDRESS_SHIFT)
1883
-#define I40E_GLPCI_VENDORID 0x000BE518 /* Reset: PCIR */
1884
-#define I40E_GLPCI_VENDORID_VENDORID_SHIFT 0
1885
-#define I40E_GLPCI_VENDORID_VENDORID_MASK I40E_MASK(0xFFFF, I40E_GLPCI_VENDORID_VENDORID_SHIFT)
1886
-#define I40E_GLPCI_VFSUP 0x000BE4B8 /* Reset: PCIR */
1887
-#define I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT 0
1888
-#define I40E_GLPCI_VFSUP_VF_PREFETCH_MASK I40E_MASK(0x1, I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT)
1889
-#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT 1
1890
-#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_MASK I40E_MASK(0x1, I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT)
1891
-#define I40E_GLTPH_CTRL 0x000BE480 /* Reset: PCIR */
1892
-#define I40E_GLTPH_CTRL_DESC_PH_SHIFT 9
1893
-#define I40E_GLTPH_CTRL_DESC_PH_MASK I40E_MASK(0x3, I40E_GLTPH_CTRL_DESC_PH_SHIFT)
1894
-#define I40E_GLTPH_CTRL_DATA_PH_SHIFT 11
1895
-#define I40E_GLTPH_CTRL_DATA_PH_MASK I40E_MASK(0x3, I40E_GLTPH_CTRL_DATA_PH_SHIFT)
1896
400
 #define I40E_PF_FUNC_RID 0x0009C000 /* Reset: PCIR */
1897
-#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT 0
1898
-#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_MASK I40E_MASK(0x7, I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT)
1899
-#define I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT 3
1900
-#define I40E_PF_FUNC_RID_DEVICE_NUMBER_MASK I40E_MASK(0x1F, I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT)
1901
-#define I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT 8
1902
-#define I40E_PF_FUNC_RID_BUS_NUMBER_MASK I40E_MASK(0xFF, I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT)
1903
401
 #define I40E_PF_PCI_CIAA 0x0009C080 /* Reset: FLR */
1904
-#define I40E_PF_PCI_CIAA_ADDRESS_SHIFT 0
1905
-#define I40E_PF_PCI_CIAA_ADDRESS_MASK I40E_MASK(0xFFF, I40E_PF_PCI_CIAA_ADDRESS_SHIFT)
1906
402
 #define I40E_PF_PCI_CIAA_VF_NUM_SHIFT 12
1907
-#define I40E_PF_PCI_CIAA_VF_NUM_MASK I40E_MASK(0x7F, I40E_PF_PCI_CIAA_VF_NUM_SHIFT)
1908
403
 #define I40E_PF_PCI_CIAD 0x0009C100 /* Reset: FLR */
1909
-#define I40E_PF_PCI_CIAD_DATA_SHIFT 0
1910
-#define I40E_PF_PCI_CIAD_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_PCI_CIAD_DATA_SHIFT)
1911
-#define I40E_PFPCI_CLASS 0x000BE400 /* Reset: PCIR */
1912
-#define I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT 0
1913
-#define I40E_PFPCI_CLASS_STORAGE_CLASS_MASK I40E_MASK(0x1, I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT)
1914
-#define I40E_PFPCI_CLASS_RESERVED_1_SHIFT 1
1915
-#define I40E_PFPCI_CLASS_RESERVED_1_MASK I40E_MASK(0x1, I40E_PFPCI_CLASS_RESERVED_1_SHIFT)
1916
-#define I40E_PFPCI_CLASS_PF_IS_LAN_SHIFT 2
1917
-#define I40E_PFPCI_CLASS_PF_IS_LAN_MASK I40E_MASK(0x1, I40E_PFPCI_CLASS_PF_IS_LAN_SHIFT)
1918
-#define I40E_PFPCI_CNF 0x000BE000 /* Reset: PCIR */
1919
-#define I40E_PFPCI_CNF_MSI_EN_SHIFT 2
1920
-#define I40E_PFPCI_CNF_MSI_EN_MASK I40E_MASK(0x1, I40E_PFPCI_CNF_MSI_EN_SHIFT)
1921
-#define I40E_PFPCI_CNF_EXROM_DIS_SHIFT 3
1922
-#define I40E_PFPCI_CNF_EXROM_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_CNF_EXROM_DIS_SHIFT)
1923
-#define I40E_PFPCI_CNF_IO_BAR_SHIFT 4
1924
-#define I40E_PFPCI_CNF_IO_BAR_MASK I40E_MASK(0x1, I40E_PFPCI_CNF_IO_BAR_SHIFT)
1925
-#define I40E_PFPCI_CNF_INT_PIN_SHIFT 5
1926
-#define I40E_PFPCI_CNF_INT_PIN_MASK I40E_MASK(0x3, I40E_PFPCI_CNF_INT_PIN_SHIFT)
1927
-#define I40E_PFPCI_DEVID 0x000BE080 /* Reset: PCIR */
1928
-#define I40E_PFPCI_DEVID_PF_DEV_ID_SHIFT 0
1929
-#define I40E_PFPCI_DEVID_PF_DEV_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_DEVID_PF_DEV_ID_SHIFT)
1930
-#define I40E_PFPCI_DEVID_VF_DEV_ID_SHIFT 16
1931
-#define I40E_PFPCI_DEVID_VF_DEV_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_DEVID_VF_DEV_ID_SHIFT)
1932
-#define I40E_PFPCI_FACTPS 0x0009C180 /* Reset: FLR */
1933
-#define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT 0
1934
-#define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_MASK I40E_MASK(0x3, I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT)
1935
-#define I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT 3
1936
-#define I40E_PFPCI_FACTPS_FUNC_AUX_EN_MASK I40E_MASK(0x1, I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT)
1937
-#define I40E_PFPCI_FUNC 0x000BE200 /* Reset: POR */
1938
-#define I40E_PFPCI_FUNC_FUNC_DIS_SHIFT 0
1939
-#define I40E_PFPCI_FUNC_FUNC_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_FUNC_FUNC_DIS_SHIFT)
1940
-#define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT 1
1941
-#define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT)
1942
-#define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT 2
1943
-#define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT)
1944
-#define I40E_PFPCI_FUNC2 0x000BE180 /* Reset: PCIR */
1945
-#define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT 0
1946
-#define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT)
1947
-#define I40E_PFPCI_ICAUSE 0x0009C200 /* Reset: PFR */
1948
-#define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT 0
1949
-#define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT)
1950
-#define I40E_PFPCI_IENA 0x0009C280 /* Reset: PFR */
1951
-#define I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT 0
1952
-#define I40E_PFPCI_IENA_PCIE_ERR_EN_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT)
1953
-#define I40E_PFPCI_PF_FLUSH_DONE 0x0009C800 /* Reset: PCIR */
1954
-#define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT 0
1955
-#define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_MASK I40E_MASK(0x1, I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT)
1956
-#define I40E_PFPCI_PM 0x000BE300 /* Reset: POR */
1957
-#define I40E_PFPCI_PM_PME_EN_SHIFT 0
1958
-#define I40E_PFPCI_PM_PME_EN_MASK I40E_MASK(0x1, I40E_PFPCI_PM_PME_EN_SHIFT)
1959
-#define I40E_PFPCI_STATUS1 0x000BE280 /* Reset: POR */
1960
-#define I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT 0
1961
-#define I40E_PFPCI_STATUS1_FUNC_VALID_MASK I40E_MASK(0x1, I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT)
1962
-#define I40E_PFPCI_SUBSYSID 0x000BE100 /* Reset: PCIR */
1963
-#define I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_SHIFT 0
1964
-#define I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_SHIFT)
1965
-#define I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_SHIFT 16
1966
-#define I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_SHIFT)
1967
-#define I40E_PFPCI_VF_FLUSH_DONE 0x0000E400 /* Reset: PCIR */
1968
-#define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT 0
1969
-#define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_MASK I40E_MASK(0x1, I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT)
1970
-#define I40E_PFPCI_VF_FLUSH_DONE1(_VF) (0x0009C600 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: PCIR */
1971
-#define I40E_PFPCI_VF_FLUSH_DONE1_MAX_INDEX 127
1972
-#define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT 0
1973
-#define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_MASK I40E_MASK(0x1, I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT)
1974
-#define I40E_PFPCI_VM_FLUSH_DONE 0x0009C880 /* Reset: PCIR */
1975
-#define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT 0
1976
-#define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_MASK I40E_MASK(0x1, I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT)
1977
-#define I40E_PFPCI_VMINDEX 0x0009C300 /* Reset: PCIR */
1978
-#define I40E_PFPCI_VMINDEX_VMINDEX_SHIFT 0
1979
-#define I40E_PFPCI_VMINDEX_VMINDEX_MASK I40E_MASK(0x1FF, I40E_PFPCI_VMINDEX_VMINDEX_SHIFT)
1980
-#define I40E_PFPCI_VMPEND 0x0009C380 /* Reset: PCIR */
1981
-#define I40E_PFPCI_VMPEND_PENDING_SHIFT 0
1982
-#define I40E_PFPCI_VMPEND_PENDING_MASK I40E_MASK(0x1, I40E_PFPCI_VMPEND_PENDING_SHIFT)
1983
404
 #define I40E_PRTPM_EEE_STAT 0x001E4320 /* Reset: GLOBR */
1984
-#define I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT 29
1985
-#define I40E_PRTPM_EEE_STAT_EEE_NEG_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT)
1986
405
 #define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT 30
1987
406
 #define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT)
1988
407
 #define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT 31
1989
408
 #define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT)
1990
-#define I40E_PRTPM_EEEC 0x001E4380 /* Reset: GLOBR */
1991
-#define I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT 16
1992
-#define I40E_PRTPM_EEEC_TW_WAKE_MIN_MASK I40E_MASK(0x3F, I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT)
1993
-#define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT 24
1994
-#define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_MASK I40E_MASK(0x3, I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT)
1995
-#define I40E_PRTPM_EEEC_TEEE_DLY_SHIFT 26
1996
-#define I40E_PRTPM_EEEC_TEEE_DLY_MASK I40E_MASK(0x3F, I40E_PRTPM_EEEC_TEEE_DLY_SHIFT)
1997
-#define I40E_PRTPM_EEEFWD 0x001E4400 /* Reset: GLOBR */
1998
-#define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT 31
1999
-#define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_MASK I40E_MASK(0x1, I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT)
2000
-#define I40E_PRTPM_EEER 0x001E4360 /* Reset: GLOBR */
2001
-#define I40E_PRTPM_EEER_TW_SYSTEM_SHIFT 0
2002
-#define I40E_PRTPM_EEER_TW_SYSTEM_MASK I40E_MASK(0xFFFF, I40E_PRTPM_EEER_TW_SYSTEM_SHIFT)
2003
-#define I40E_PRTPM_EEER_TX_LPI_EN_SHIFT 16
2004
-#define I40E_PRTPM_EEER_TX_LPI_EN_MASK I40E_MASK(0x1, I40E_PRTPM_EEER_TX_LPI_EN_SHIFT)
2005
-#define I40E_PRTPM_EEETXC 0x001E43E0 /* Reset: GLOBR */
2006
-#define I40E_PRTPM_EEETXC_TW_PHY_SHIFT 0
2007
-#define I40E_PRTPM_EEETXC_TW_PHY_MASK I40E_MASK(0xFFFF, I40E_PRTPM_EEETXC_TW_PHY_SHIFT)
2008
-#define I40E_PRTPM_GC 0x000B8140 /* Reset: POR */
2009
-#define I40E_PRTPM_GC_EMP_LINK_ON_SHIFT 0
2010
-#define I40E_PRTPM_GC_EMP_LINK_ON_MASK I40E_MASK(0x1, I40E_PRTPM_GC_EMP_LINK_ON_SHIFT)
2011
-#define I40E_PRTPM_GC_MNG_VETO_SHIFT 1
2012
-#define I40E_PRTPM_GC_MNG_VETO_MASK I40E_MASK(0x1, I40E_PRTPM_GC_MNG_VETO_SHIFT)
2013
-#define I40E_PRTPM_GC_RATD_SHIFT 2
2014
-#define I40E_PRTPM_GC_RATD_MASK I40E_MASK(0x1, I40E_PRTPM_GC_RATD_SHIFT)
2015
-#define I40E_PRTPM_GC_LCDMP_SHIFT 3
2016
-#define I40E_PRTPM_GC_LCDMP_MASK I40E_MASK(0x1, I40E_PRTPM_GC_LCDMP_SHIFT)
2017
-#define I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT 31
2018
-#define I40E_PRTPM_GC_LPLU_ASSERTED_MASK I40E_MASK(0x1, I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT)
2019
409
 #define I40E_PRTPM_RLPIC 0x001E43A0 /* Reset: GLOBR */
2020
-#define I40E_PRTPM_RLPIC_ERLPIC_SHIFT 0
2021
-#define I40E_PRTPM_RLPIC_ERLPIC_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_RLPIC_ERLPIC_SHIFT)
2022
410
 #define I40E_PRTPM_TLPIC 0x001E43C0 /* Reset: GLOBR */
2023
-#define I40E_PRTPM_TLPIC_ETLPIC_SHIFT 0
2024
-#define I40E_PRTPM_TLPIC_ETLPIC_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_TLPIC_ETLPIC_SHIFT)
2025
-#define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */
2026
-#define I40E_GL_PRS_FVBM_MAX_INDEX 3
2027
-#define I40E_GL_PRS_FVBM_FV_BYTE_INDX_SHIFT 0
2028
-#define I40E_GL_PRS_FVBM_FV_BYTE_INDX_MASK I40E_MASK(0x7F, I40E_GL_PRS_FVBM_FV_BYTE_INDX_SHIFT)
2029
-#define I40E_GL_PRS_FVBM_RULE_BUS_INDX_SHIFT 8
2030
-#define I40E_GL_PRS_FVBM_RULE_BUS_INDX_MASK I40E_MASK(0x3F, I40E_GL_PRS_FVBM_RULE_BUS_INDX_SHIFT)
2031
-#define I40E_GL_PRS_FVBM_MSK_ENA_SHIFT 31
2032
-#define I40E_GL_PRS_FVBM_MSK_ENA_MASK I40E_MASK(0x1, I40E_GL_PRS_FVBM_MSK_ENA_SHIFT)
2033
-#define I40E_GLRPB_DPSS 0x000AC828 /* Reset: CORER */
2034
-#define I40E_GLRPB_DPSS_DPS_TCN_SHIFT 0
2035
-#define I40E_GLRPB_DPSS_DPS_TCN_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_DPSS_DPS_TCN_SHIFT)
2036
-#define I40E_GLRPB_GHW 0x000AC830 /* Reset: CORER */
2037
-#define I40E_GLRPB_GHW_GHW_SHIFT 0
2038
-#define I40E_GLRPB_GHW_GHW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_GHW_GHW_SHIFT)
2039
-#define I40E_GLRPB_GLW 0x000AC834 /* Reset: CORER */
2040
-#define I40E_GLRPB_GLW_GLW_SHIFT 0
2041
-#define I40E_GLRPB_GLW_GLW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_GLW_GLW_SHIFT)
2042
-#define I40E_GLRPB_PHW 0x000AC844 /* Reset: CORER */
2043
-#define I40E_GLRPB_PHW_PHW_SHIFT 0
2044
-#define I40E_GLRPB_PHW_PHW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_PHW_PHW_SHIFT)
2045
-#define I40E_GLRPB_PLW 0x000AC848 /* Reset: CORER */
2046
-#define I40E_GLRPB_PLW_PLW_SHIFT 0
2047
-#define I40E_GLRPB_PLW_PLW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_PLW_PLW_SHIFT)
2048
-#define I40E_PRTRPB_DHW(_i) (0x000AC100 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
2049
-#define I40E_PRTRPB_DHW_MAX_INDEX 7
2050
-#define I40E_PRTRPB_DHW_DHW_TCN_SHIFT 0
2051
-#define I40E_PRTRPB_DHW_DHW_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DHW_DHW_TCN_SHIFT)
2052
-#define I40E_PRTRPB_DLW(_i) (0x000AC220 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
2053
-#define I40E_PRTRPB_DLW_MAX_INDEX 7
2054
-#define I40E_PRTRPB_DLW_DLW_TCN_SHIFT 0
2055
-#define I40E_PRTRPB_DLW_DLW_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DLW_DLW_TCN_SHIFT)
2056
-#define I40E_PRTRPB_DPS(_i) (0x000AC320 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
2057
-#define I40E_PRTRPB_DPS_MAX_INDEX 7
2058
-#define I40E_PRTRPB_DPS_DPS_TCN_SHIFT 0
2059
-#define I40E_PRTRPB_DPS_DPS_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DPS_DPS_TCN_SHIFT)
2060
-#define I40E_PRTRPB_SHT(_i) (0x000AC480 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
2061
-#define I40E_PRTRPB_SHT_MAX_INDEX 7
2062
-#define I40E_PRTRPB_SHT_SHT_TCN_SHIFT 0
2063
-#define I40E_PRTRPB_SHT_SHT_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SHT_SHT_TCN_SHIFT)
2064
-#define I40E_PRTRPB_SHW 0x000AC580 /* Reset: CORER */
2065
-#define I40E_PRTRPB_SHW_SHW_SHIFT 0
2066
-#define I40E_PRTRPB_SHW_SHW_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SHW_SHW_SHIFT)
2067
-#define I40E_PRTRPB_SLT(_i) (0x000AC5A0 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
2068
-#define I40E_PRTRPB_SLT_MAX_INDEX 7
2069
-#define I40E_PRTRPB_SLT_SLT_TCN_SHIFT 0
2070
-#define I40E_PRTRPB_SLT_SLT_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SLT_SLT_TCN_SHIFT)
2071
-#define I40E_PRTRPB_SLW 0x000AC6A0 /* Reset: CORER */
2072
-#define I40E_PRTRPB_SLW_SLW_SHIFT 0
2073
-#define I40E_PRTRPB_SLW_SLW_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SLW_SLW_SHIFT)
2074
-#define I40E_PRTRPB_SPS 0x000AC7C0 /* Reset: CORER */
2075
-#define I40E_PRTRPB_SPS_SPS_SHIFT 0
2076
-#define I40E_PRTRPB_SPS_SPS_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SPS_SPS_SHIFT)
2077
-#define I40E_GLQF_CTL 0x00269BA4 /* Reset: CORER */
2078
-#define I40E_GLQF_CTL_HTOEP_SHIFT 1
2079
-#define I40E_GLQF_CTL_HTOEP_MASK I40E_MASK(0x1, I40E_GLQF_CTL_HTOEP_SHIFT)
2080
-#define I40E_GLQF_CTL_HTOEP_FCOE_SHIFT 2
2081
-#define I40E_GLQF_CTL_HTOEP_FCOE_MASK I40E_MASK(0x1, I40E_GLQF_CTL_HTOEP_FCOE_SHIFT)
2082
-#define I40E_GLQF_CTL_PCNT_ALLOC_SHIFT 3
2083
-#define I40E_GLQF_CTL_PCNT_ALLOC_MASK I40E_MASK(0x7, I40E_GLQF_CTL_PCNT_ALLOC_SHIFT)
2084
-#define I40E_GLQF_CTL_FD_AUTO_PCTYPE_SHIFT 6
2085
-#define I40E_GLQF_CTL_FD_AUTO_PCTYPE_MASK I40E_MASK(0x1, I40E_GLQF_CTL_FD_AUTO_PCTYPE_SHIFT)
2086
-#define I40E_GLQF_CTL_RSVD_SHIFT 7
2087
-#define I40E_GLQF_CTL_RSVD_MASK I40E_MASK(0x1, I40E_GLQF_CTL_RSVD_SHIFT)
2088
-#define I40E_GLQF_CTL_MAXPEBLEN_SHIFT 8
2089
-#define I40E_GLQF_CTL_MAXPEBLEN_MASK I40E_MASK(0x7, I40E_GLQF_CTL_MAXPEBLEN_SHIFT)
2090
-#define I40E_GLQF_CTL_MAXFCBLEN_SHIFT 11
2091
-#define I40E_GLQF_CTL_MAXFCBLEN_MASK I40E_MASK(0x7, I40E_GLQF_CTL_MAXFCBLEN_SHIFT)
2092
-#define I40E_GLQF_CTL_MAXFDBLEN_SHIFT 14
2093
-#define I40E_GLQF_CTL_MAXFDBLEN_MASK I40E_MASK(0x7, I40E_GLQF_CTL_MAXFDBLEN_SHIFT)
2094
-#define I40E_GLQF_CTL_FDBEST_SHIFT 17
2095
-#define I40E_GLQF_CTL_FDBEST_MASK I40E_MASK(0xFF, I40E_GLQF_CTL_FDBEST_SHIFT)
2096
-#define I40E_GLQF_CTL_PROGPRIO_SHIFT 25
2097
-#define I40E_GLQF_CTL_PROGPRIO_MASK I40E_MASK(0x1, I40E_GLQF_CTL_PROGPRIO_SHIFT)
2098
-#define I40E_GLQF_CTL_INVALPRIO_SHIFT 26
2099
-#define I40E_GLQF_CTL_INVALPRIO_MASK I40E_MASK(0x1, I40E_GLQF_CTL_INVALPRIO_SHIFT)
2100
-#define I40E_GLQF_CTL_IGNORE_IP_SHIFT 27
2101
-#define I40E_GLQF_CTL_IGNORE_IP_MASK I40E_MASK(0x1, I40E_GLQF_CTL_IGNORE_IP_SHIFT)
2102
411
 #define I40E_GLQF_FDCNT_0 0x00269BAC /* Reset: CORER */
2103
412
 #define I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT 0
2104
413
 #define I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT)
..
..
@@ -2106,36 +415,7 @@
2106
415
 #define I40E_GLQF_FDCNT_0_BESTCNT_MASK I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_BESTCNT_SHIFT)
2107
416
 #define I40E_GLQF_HKEY(_i) (0x00270140 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */
2108
417
 #define I40E_GLQF_HKEY_MAX_INDEX 12
2109
-#define I40E_GLQF_HKEY_KEY_0_SHIFT 0
2110
-#define I40E_GLQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_0_SHIFT)
2111
-#define I40E_GLQF_HKEY_KEY_1_SHIFT 8
2112
-#define I40E_GLQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_1_SHIFT)
2113
-#define I40E_GLQF_HKEY_KEY_2_SHIFT 16
2114
-#define I40E_GLQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_2_SHIFT)
2115
-#define I40E_GLQF_HKEY_KEY_3_SHIFT 24
2116
-#define I40E_GLQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_3_SHIFT)
2117
-#define I40E_GLQF_HSYM(_i) (0x00269D00 + ((_i) * 4)) /* _i=0...63 */ /* Reset: CORER */
2118
-#define I40E_GLQF_HSYM_MAX_INDEX 63
2119
-#define I40E_GLQF_HSYM_SYMH_ENA_SHIFT 0
2120
-#define I40E_GLQF_HSYM_SYMH_ENA_MASK I40E_MASK(0x1, I40E_GLQF_HSYM_SYMH_ENA_SHIFT)
2121
418
 #define I40E_GLQF_PCNT(_i) (0x00266800 + ((_i) * 4)) /* _i=0...511 */ /* Reset: CORER */
2122
-#define I40E_GLQF_PCNT_MAX_INDEX 511
2123
-#define I40E_GLQF_PCNT_PCNT_SHIFT 0
2124
-#define I40E_GLQF_PCNT_PCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLQF_PCNT_PCNT_SHIFT)
2125
-#define I40E_GLQF_SWAP(_i, _j) (0x00267E00 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */
2126
-#define I40E_GLQF_SWAP_MAX_INDEX 1
2127
-#define I40E_GLQF_SWAP_OFF0_SRC0_SHIFT 0
2128
-#define I40E_GLQF_SWAP_OFF0_SRC0_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF0_SRC0_SHIFT)
2129
-#define I40E_GLQF_SWAP_OFF0_SRC1_SHIFT 6
2130
-#define I40E_GLQF_SWAP_OFF0_SRC1_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF0_SRC1_SHIFT)
2131
-#define I40E_GLQF_SWAP_FLEN0_SHIFT 12
2132
-#define I40E_GLQF_SWAP_FLEN0_MASK I40E_MASK(0xF, I40E_GLQF_SWAP_FLEN0_SHIFT)
2133
-#define I40E_GLQF_SWAP_OFF1_SRC0_SHIFT 16
2134
-#define I40E_GLQF_SWAP_OFF1_SRC0_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF1_SRC0_SHIFT)
2135
-#define I40E_GLQF_SWAP_OFF1_SRC1_SHIFT 22
2136
-#define I40E_GLQF_SWAP_OFF1_SRC1_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF1_SRC1_SHIFT)
2137
-#define I40E_GLQF_SWAP_FLEN1_SHIFT 28
2138
-#define I40E_GLQF_SWAP_FLEN1_MASK I40E_MASK(0xF, I40E_GLQF_SWAP_FLEN1_SHIFT)
2139
419
 #define I40E_PFQF_CTL_0 0x001C0AC0 /* Reset: CORER */
2140
420
 #define I40E_PFQF_CTL_0_PEHSIZE_SHIFT 0
2141
421
 #define I40E_PFQF_CTL_0_PEHSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEHSIZE_SHIFT)
..
..
@@ -2153,54 +433,19 @@
2153
433
 #define I40E_PFQF_CTL_0_ETYPE_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT)
2154
434
 #define I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT 19
2155
435
 #define I40E_PFQF_CTL_0_MACVLAN_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT)
2156
-#define I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT 20
2157
-#define I40E_PFQF_CTL_0_VFFCHSIZE_MASK I40E_MASK(0xF, I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT)
2158
-#define I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT 24
2159
-#define I40E_PFQF_CTL_0_VFFCDSIZE_MASK I40E_MASK(0x3, I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT)
2160
436
 #define I40E_PFQF_CTL_1 0x00245D80 /* Reset: CORER */
2161
437
 #define I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT 0
2162
438
 #define I40E_PFQF_CTL_1_CLEARFDTABLE_MASK I40E_MASK(0x1, I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT)
2163
-#define I40E_PFQF_FDALLOC 0x00246280 /* Reset: CORER */
2164
-#define I40E_PFQF_FDALLOC_FDALLOC_SHIFT 0
2165
-#define I40E_PFQF_FDALLOC_FDALLOC_MASK I40E_MASK(0xFF, I40E_PFQF_FDALLOC_FDALLOC_SHIFT)
2166
-#define I40E_PFQF_FDALLOC_FDBEST_SHIFT 8
2167
-#define I40E_PFQF_FDALLOC_FDBEST_MASK I40E_MASK(0xFF, I40E_PFQF_FDALLOC_FDBEST_SHIFT)
2168
439
 #define I40E_PFQF_FDSTAT 0x00246380 /* Reset: CORER */
2169
440
 #define I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT 0
2170
441
 #define I40E_PFQF_FDSTAT_GUARANT_CNT_MASK I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT)
2171
442
 #define I40E_PFQF_FDSTAT_BEST_CNT_SHIFT 16
2172
443
 #define I40E_PFQF_FDSTAT_BEST_CNT_MASK I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_BEST_CNT_SHIFT)
2173
444
 #define I40E_PFQF_HENA(_i) (0x00245900 + ((_i) * 128)) /* _i=0...1 */ /* Reset: CORER */
2174
-#define I40E_PFQF_HENA_MAX_INDEX 1
2175
-#define I40E_PFQF_HENA_PTYPE_ENA_SHIFT 0
2176
-#define I40E_PFQF_HENA_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_PFQF_HENA_PTYPE_ENA_SHIFT)
2177
445
 #define I40E_PFQF_HKEY(_i) (0x00244800 + ((_i) * 128)) /* _i=0...12 */ /* Reset: CORER */
2178
446
 #define I40E_PFQF_HKEY_MAX_INDEX 12
2179
-#define I40E_PFQF_HKEY_KEY_0_SHIFT 0
2180
-#define I40E_PFQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_0_SHIFT)
2181
-#define I40E_PFQF_HKEY_KEY_1_SHIFT 8
2182
-#define I40E_PFQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_1_SHIFT)
2183
-#define I40E_PFQF_HKEY_KEY_2_SHIFT 16
2184
-#define I40E_PFQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_2_SHIFT)
2185
-#define I40E_PFQF_HKEY_KEY_3_SHIFT 24
2186
-#define I40E_PFQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_3_SHIFT)
2187
447
 #define I40E_PFQF_HLUT(_i) (0x00240000 + ((_i) * 128)) /* _i=0...127 */ /* Reset: CORER */
2188
448
 #define I40E_PFQF_HLUT_MAX_INDEX 127
2189
-#define I40E_PFQF_HLUT_LUT0_SHIFT 0
2190
-#define I40E_PFQF_HLUT_LUT0_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT0_SHIFT)
2191
-#define I40E_PFQF_HLUT_LUT1_SHIFT 8
2192
-#define I40E_PFQF_HLUT_LUT1_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT1_SHIFT)
2193
-#define I40E_PFQF_HLUT_LUT2_SHIFT 16
2194
-#define I40E_PFQF_HLUT_LUT2_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT2_SHIFT)
2195
-#define I40E_PFQF_HLUT_LUT3_SHIFT 24
2196
-#define I40E_PFQF_HLUT_LUT3_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT3_SHIFT)
2197
-#define I40E_PRTQF_CTL_0 0x00256E60 /* Reset: CORER */
2198
-#define I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT 0
2199
-#define I40E_PRTQF_CTL_0_HSYM_ENA_MASK I40E_MASK(0x1, I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT)
2200
-#define I40E_PRTQF_FD_FLXINSET(_i) (0x00253800 + ((_i) * 32)) /* _i=0...63 */ /* Reset: CORER */
2201
-#define I40E_PRTQF_FD_FLXINSET_MAX_INDEX 63
2202
-#define I40E_PRTQF_FD_FLXINSET_INSET_SHIFT 0
2203
-#define I40E_PRTQF_FD_FLXINSET_INSET_MASK I40E_MASK(0xFF, I40E_PRTQF_FD_FLXINSET_INSET_SHIFT)
2204
449
 #define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */
2205
450
 #define I40E_PRTQF_FD_INSET_MAX_INDEX 63
2206
451
 #define I40E_PRTQF_FD_INSET_INSET_SHIFT 0
..
..
@@ -2209,14 +454,7 @@
2209
454
 #define I40E_PRTQF_FD_INSET_MAX_INDEX 63
2210
455
 #define I40E_PRTQF_FD_INSET_INSET_SHIFT 0
2211
456
 #define I40E_PRTQF_FD_INSET_INSET_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTQF_FD_INSET_INSET_SHIFT)
2212
-#define I40E_PRTQF_FD_MSK(_i, _j) (0x00252000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */
2213
-#define I40E_PRTQF_FD_MSK_MAX_INDEX 63
2214
-#define I40E_PRTQF_FD_MSK_MASK_SHIFT 0
2215
-#define I40E_PRTQF_FD_MSK_MASK_MASK I40E_MASK(0xFFFF, I40E_PRTQF_FD_MSK_MASK_SHIFT)
2216
-#define I40E_PRTQF_FD_MSK_OFFSET_SHIFT 16
2217
-#define I40E_PRTQF_FD_MSK_OFFSET_MASK I40E_MASK(0x3F, I40E_PRTQF_FD_MSK_OFFSET_SHIFT)
2218
457
 #define I40E_PRTQF_FLX_PIT(_i) (0x00255200 + ((_i) * 32)) /* _i=0...8 */ /* Reset: CORER */
2219
-#define I40E_PRTQF_FLX_PIT_MAX_INDEX 8
2220
458
 #define I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT 0
2221
459
 #define I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK I40E_MASK(0x1F, I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT)
2222
460
 #define I40E_PRTQF_FLX_PIT_FSIZE_SHIFT 5
..
..
@@ -2224,775 +462,156 @@
2224
462
 #define I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT 10
2225
463
 #define I40E_PRTQF_FLX_PIT_DEST_OFF_MASK I40E_MASK(0x3F, I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT)
2226
464
 #define I40E_VFQF_HENA1(_i, _VF) (0x00230800 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...1, _VF=0...127 */ /* Reset: CORER */
2227
-#define I40E_VFQF_HENA1_MAX_INDEX 1
2228
-#define I40E_VFQF_HENA1_PTYPE_ENA_SHIFT 0
2229
-#define I40E_VFQF_HENA1_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_VFQF_HENA1_PTYPE_ENA_SHIFT)
2230
465
 #define I40E_VFQF_HKEY1(_i, _VF) (0x00228000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...12, _VF=0...127 */ /* Reset: CORER */
2231
466
 #define I40E_VFQF_HKEY1_MAX_INDEX 12
2232
-#define I40E_VFQF_HKEY1_KEY_0_SHIFT 0
2233
-#define I40E_VFQF_HKEY1_KEY_0_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_0_SHIFT)
2234
-#define I40E_VFQF_HKEY1_KEY_1_SHIFT 8
2235
-#define I40E_VFQF_HKEY1_KEY_1_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_1_SHIFT)
2236
-#define I40E_VFQF_HKEY1_KEY_2_SHIFT 16
2237
-#define I40E_VFQF_HKEY1_KEY_2_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_2_SHIFT)
2238
-#define I40E_VFQF_HKEY1_KEY_3_SHIFT 24
2239
-#define I40E_VFQF_HKEY1_KEY_3_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_3_SHIFT)
2240
467
 #define I40E_VFQF_HLUT1(_i, _VF) (0x00220000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: CORER */
2241
468
 #define I40E_VFQF_HLUT1_MAX_INDEX 15
2242
-#define I40E_VFQF_HLUT1_LUT0_SHIFT 0
2243
-#define I40E_VFQF_HLUT1_LUT0_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT0_SHIFT)
2244
-#define I40E_VFQF_HLUT1_LUT1_SHIFT 8
2245
-#define I40E_VFQF_HLUT1_LUT1_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT1_SHIFT)
2246
-#define I40E_VFQF_HLUT1_LUT2_SHIFT 16
2247
-#define I40E_VFQF_HLUT1_LUT2_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT2_SHIFT)
2248
-#define I40E_VFQF_HLUT1_LUT3_SHIFT 24
2249
-#define I40E_VFQF_HLUT1_LUT3_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT3_SHIFT)
2250
-#define I40E_VFQF_HREGION1(_i, _VF) (0x0022E000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...7, _VF=0...127 */ /* Reset: CORER */
2251
-#define I40E_VFQF_HREGION1_MAX_INDEX 7
2252
-#define I40E_VFQF_HREGION1_OVERRIDE_ENA_0_SHIFT 0
2253
-#define I40E_VFQF_HREGION1_OVERRIDE_ENA_0_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_0_SHIFT)
2254
-#define I40E_VFQF_HREGION1_REGION_0_SHIFT 1
2255
-#define I40E_VFQF_HREGION1_REGION_0_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_0_SHIFT)
2256
-#define I40E_VFQF_HREGION1_OVERRIDE_ENA_1_SHIFT 4
2257
-#define I40E_VFQF_HREGION1_OVERRIDE_ENA_1_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_1_SHIFT)
2258
-#define I40E_VFQF_HREGION1_REGION_1_SHIFT 5
2259
-#define I40E_VFQF_HREGION1_REGION_1_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_1_SHIFT)
2260
-#define I40E_VFQF_HREGION1_OVERRIDE_ENA_2_SHIFT 8
2261
-#define I40E_VFQF_HREGION1_OVERRIDE_ENA_2_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_2_SHIFT)
2262
-#define I40E_VFQF_HREGION1_REGION_2_SHIFT 9
2263
-#define I40E_VFQF_HREGION1_REGION_2_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_2_SHIFT)
2264
-#define I40E_VFQF_HREGION1_OVERRIDE_ENA_3_SHIFT 12
2265
-#define I40E_VFQF_HREGION1_OVERRIDE_ENA_3_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_3_SHIFT)
2266
-#define I40E_VFQF_HREGION1_REGION_3_SHIFT 13
2267
-#define I40E_VFQF_HREGION1_REGION_3_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_3_SHIFT)
2268
-#define I40E_VFQF_HREGION1_OVERRIDE_ENA_4_SHIFT 16
2269
-#define I40E_VFQF_HREGION1_OVERRIDE_ENA_4_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_4_SHIFT)
2270
-#define I40E_VFQF_HREGION1_REGION_4_SHIFT 17
2271
-#define I40E_VFQF_HREGION1_REGION_4_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_4_SHIFT)
2272
-#define I40E_VFQF_HREGION1_OVERRIDE_ENA_5_SHIFT 20
2273
-#define I40E_VFQF_HREGION1_OVERRIDE_ENA_5_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_5_SHIFT)
2274
-#define I40E_VFQF_HREGION1_REGION_5_SHIFT 21
2275
-#define I40E_VFQF_HREGION1_REGION_5_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_5_SHIFT)
2276
-#define I40E_VFQF_HREGION1_OVERRIDE_ENA_6_SHIFT 24
2277
-#define I40E_VFQF_HREGION1_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_6_SHIFT)
2278
-#define I40E_VFQF_HREGION1_REGION_6_SHIFT 25
2279
-#define I40E_VFQF_HREGION1_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_6_SHIFT)
2280
-#define I40E_VFQF_HREGION1_OVERRIDE_ENA_7_SHIFT 28
2281
-#define I40E_VFQF_HREGION1_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_7_SHIFT)
2282
-#define I40E_VFQF_HREGION1_REGION_7_SHIFT 29
2283
-#define I40E_VFQF_HREGION1_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_7_SHIFT)
2284
-#define I40E_VPQF_CTL(_VF) (0x001C0000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
2285
-#define I40E_VPQF_CTL_MAX_INDEX 127
2286
-#define I40E_VPQF_CTL_PEHSIZE_SHIFT 0
2287
-#define I40E_VPQF_CTL_PEHSIZE_MASK I40E_MASK(0x1F, I40E_VPQF_CTL_PEHSIZE_SHIFT)
2288
-#define I40E_VPQF_CTL_PEDSIZE_SHIFT 5
2289
-#define I40E_VPQF_CTL_PEDSIZE_MASK I40E_MASK(0x1F, I40E_VPQF_CTL_PEDSIZE_SHIFT)
2290
-#define I40E_VPQF_CTL_FCHSIZE_SHIFT 10
2291
-#define I40E_VPQF_CTL_FCHSIZE_MASK I40E_MASK(0xF, I40E_VPQF_CTL_FCHSIZE_SHIFT)
2292
-#define I40E_VPQF_CTL_FCDSIZE_SHIFT 14
2293
-#define I40E_VPQF_CTL_FCDSIZE_MASK I40E_MASK(0x3, I40E_VPQF_CTL_FCDSIZE_SHIFT)
2294
-#define I40E_VSIQF_CTL(_VSI) (0x0020D800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */
2295
-#define I40E_VSIQF_CTL_MAX_INDEX 383
2296
-#define I40E_VSIQF_CTL_FCOE_ENA_SHIFT 0
2297
-#define I40E_VSIQF_CTL_FCOE_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_FCOE_ENA_SHIFT)
2298
-#define I40E_VSIQF_CTL_PETCP_ENA_SHIFT 1
2299
-#define I40E_VSIQF_CTL_PETCP_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PETCP_ENA_SHIFT)
2300
-#define I40E_VSIQF_CTL_PEUUDP_ENA_SHIFT 2
2301
-#define I40E_VSIQF_CTL_PEUUDP_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PEUUDP_ENA_SHIFT)
2302
-#define I40E_VSIQF_CTL_PEMUDP_ENA_SHIFT 3
2303
-#define I40E_VSIQF_CTL_PEMUDP_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PEMUDP_ENA_SHIFT)
2304
-#define I40E_VSIQF_CTL_PEUFRAG_ENA_SHIFT 4
2305
-#define I40E_VSIQF_CTL_PEUFRAG_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PEUFRAG_ENA_SHIFT)
2306
-#define I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT 5
2307
-#define I40E_VSIQF_CTL_PEMFRAG_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT)
2308
-#define I40E_VSIQF_TCREGION(_i, _VSI) (0x00206000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...3, _VSI=0...383 */ /* Reset: PFR */
2309
-#define I40E_VSIQF_TCREGION_MAX_INDEX 3
2310
-#define I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT 0
2311
-#define I40E_VSIQF_TCREGION_TC_OFFSET_MASK I40E_MASK(0x1FF, I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT)
2312
-#define I40E_VSIQF_TCREGION_TC_SIZE_SHIFT 9
2313
-#define I40E_VSIQF_TCREGION_TC_SIZE_MASK I40E_MASK(0x7, I40E_VSIQF_TCREGION_TC_SIZE_SHIFT)
2314
-#define I40E_VSIQF_TCREGION_TC_OFFSET2_SHIFT 16
2315
-#define I40E_VSIQF_TCREGION_TC_OFFSET2_MASK I40E_MASK(0x1FF, I40E_VSIQF_TCREGION_TC_OFFSET2_SHIFT)
2316
-#define I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT 25
2317
-#define I40E_VSIQF_TCREGION_TC_SIZE2_MASK I40E_MASK(0x7, I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT)
2318
-#define I40E_GL_FCOECRC(_i) (0x00314d80 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
2319
-#define I40E_GL_FCOECRC_MAX_INDEX 143
2320
-#define I40E_GL_FCOECRC_FCOECRC_SHIFT 0
2321
-#define I40E_GL_FCOECRC_FCOECRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOECRC_FCOECRC_SHIFT)
2322
-#define I40E_GL_FCOEDDPC(_i) (0x00314480 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
2323
-#define I40E_GL_FCOEDDPC_MAX_INDEX 143
2324
-#define I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT 0
2325
-#define I40E_GL_FCOEDDPC_FCOEDDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT)
2326
-#define I40E_GL_FCOEDIFEC(_i) (0x00318480 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
2327
-#define I40E_GL_FCOEDIFEC_MAX_INDEX 143
2328
-#define I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT 0
2329
-#define I40E_GL_FCOEDIFEC_FCOEDIFRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT)
2330
-#define I40E_GL_FCOEDIFTCL(_i) (0x00354000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
2331
-#define I40E_GL_FCOEDIFTCL_MAX_INDEX 143
2332
-#define I40E_GL_FCOEDIFTCL_FCOEDIFTC_SHIFT 0
2333
-#define I40E_GL_FCOEDIFTCL_FCOEDIFTC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIFTCL_FCOEDIFTC_SHIFT)
2334
-#define I40E_GL_FCOEDIXEC(_i) (0x0034c000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
2335
-#define I40E_GL_FCOEDIXEC_MAX_INDEX 143
2336
-#define I40E_GL_FCOEDIXEC_FCOEDIXEC_SHIFT 0
2337
-#define I40E_GL_FCOEDIXEC_FCOEDIXEC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIXEC_FCOEDIXEC_SHIFT)
2338
-#define I40E_GL_FCOEDIXVC(_i) (0x00350000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
2339
-#define I40E_GL_FCOEDIXVC_MAX_INDEX 143
2340
-#define I40E_GL_FCOEDIXVC_FCOEDIXVC_SHIFT 0
2341
-#define I40E_GL_FCOEDIXVC_FCOEDIXVC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIXVC_FCOEDIXVC_SHIFT)
2342
-#define I40E_GL_FCOEDWRCH(_i) (0x00320004 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
2343
-#define I40E_GL_FCOEDWRCH_MAX_INDEX 143
2344
-#define I40E_GL_FCOEDWRCH_FCOEDWRCH_SHIFT 0
2345
-#define I40E_GL_FCOEDWRCH_FCOEDWRCH_MASK I40E_MASK(0xFFFF, I40E_GL_FCOEDWRCH_FCOEDWRCH_SHIFT)
2346
-#define I40E_GL_FCOEDWRCL(_i) (0x00320000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
2347
-#define I40E_GL_FCOEDWRCL_MAX_INDEX 143
2348
-#define I40E_GL_FCOEDWRCL_FCOEDWRCL_SHIFT 0
2349
-#define I40E_GL_FCOEDWRCL_FCOEDWRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDWRCL_FCOEDWRCL_SHIFT)
2350
-#define I40E_GL_FCOEDWTCH(_i) (0x00348084 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
2351
-#define I40E_GL_FCOEDWTCH_MAX_INDEX 143
2352
-#define I40E_GL_FCOEDWTCH_FCOEDWTCH_SHIFT 0
2353
-#define I40E_GL_FCOEDWTCH_FCOEDWTCH_MASK I40E_MASK(0xFFFF, I40E_GL_FCOEDWTCH_FCOEDWTCH_SHIFT)
2354
-#define I40E_GL_FCOEDWTCL(_i) (0x00348080 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
2355
-#define I40E_GL_FCOEDWTCL_MAX_INDEX 143
2356
-#define I40E_GL_FCOEDWTCL_FCOEDWTCL_SHIFT 0
2357
-#define I40E_GL_FCOEDWTCL_FCOEDWTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDWTCL_FCOEDWTCL_SHIFT)
2358
-#define I40E_GL_FCOELAST(_i) (0x00314000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
2359
-#define I40E_GL_FCOELAST_MAX_INDEX 143
2360
-#define I40E_GL_FCOELAST_FCOELAST_SHIFT 0
2361
-#define I40E_GL_FCOELAST_FCOELAST_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOELAST_FCOELAST_SHIFT)
2362
-#define I40E_GL_FCOEPRC(_i) (0x00315200 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
2363
-#define I40E_GL_FCOEPRC_MAX_INDEX 143
2364
-#define I40E_GL_FCOEPRC_FCOEPRC_SHIFT 0
2365
-#define I40E_GL_FCOEPRC_FCOEPRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEPRC_FCOEPRC_SHIFT)
2366
-#define I40E_GL_FCOEPTC(_i) (0x00344C00 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
2367
-#define I40E_GL_FCOEPTC_MAX_INDEX 143
2368
-#define I40E_GL_FCOEPTC_FCOEPTC_SHIFT 0
2369
-#define I40E_GL_FCOEPTC_FCOEPTC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEPTC_FCOEPTC_SHIFT)
2370
-#define I40E_GL_FCOERPDC(_i) (0x00324000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
2371
-#define I40E_GL_FCOERPDC_MAX_INDEX 143
2372
-#define I40E_GL_FCOERPDC_FCOERPDC_SHIFT 0
2373
-#define I40E_GL_FCOERPDC_FCOERPDC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOERPDC_FCOERPDC_SHIFT)
2374
-#define I40E_GL_RXERR1_L(_i) (0x00318000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
2375
-#define I40E_GL_RXERR1_L_MAX_INDEX 143
2376
-#define I40E_GL_RXERR1_L_FCOEDIFRC_SHIFT 0
2377
-#define I40E_GL_RXERR1_L_FCOEDIFRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1_L_FCOEDIFRC_SHIFT)
2378
-#define I40E_GL_RXERR2_L(_i) (0x0031c000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
2379
-#define I40E_GL_RXERR2_L_MAX_INDEX 143
2380
-#define I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT 0
2381
-#define I40E_GL_RXERR2_L_FCOEDIXAC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT)
469
+#define I40E_GL_RXERR1H(_i)             (0x00318004 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
470
+#define I40E_GL_RXERR1H_MAX_INDEX       143
471
+#define I40E_GL_RXERR1H_RXERR1H_SHIFT   0
472
+#define I40E_GL_RXERR1H_RXERR1H_MASK    I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1H_RXERR1H_SHIFT)
473
+#define I40E_GL_RXERR1L(_i)             (0x00318000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
474
+#define I40E_GL_RXERR1L_MAX_INDEX       143
475
+#define I40E_GL_RXERR1L_RXERR1L_SHIFT   0
476
+#define I40E_GL_RXERR1L_RXERR1L_MASK    I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1L_RXERR1L_SHIFT)
2382
477
 #define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2383
-#define I40E_GLPRT_BPRCH_MAX_INDEX 3
2384
-#define I40E_GLPRT_BPRCH_BPRCH_SHIFT 0
2385
-#define I40E_GLPRT_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPRCH_BPRCH_SHIFT)
2386
478
 #define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2387
-#define I40E_GLPRT_BPRCL_MAX_INDEX 3
2388
-#define I40E_GLPRT_BPRCL_BPRCL_SHIFT 0
2389
-#define I40E_GLPRT_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPRCL_BPRCL_SHIFT)
2390
479
 #define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2391
-#define I40E_GLPRT_BPTCH_MAX_INDEX 3
2392
-#define I40E_GLPRT_BPTCH_BPTCH_SHIFT 0
2393
-#define I40E_GLPRT_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPTCH_BPTCH_SHIFT)
2394
480
 #define I40E_GLPRT_BPTCL(_i) (0x00300A00 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2395
-#define I40E_GLPRT_BPTCL_MAX_INDEX 3
2396
-#define I40E_GLPRT_BPTCL_BPTCL_SHIFT 0
2397
-#define I40E_GLPRT_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPTCL_BPTCL_SHIFT)
2398
481
 #define I40E_GLPRT_CRCERRS(_i) (0x00300080 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2399
-#define I40E_GLPRT_CRCERRS_MAX_INDEX 3
2400
-#define I40E_GLPRT_CRCERRS_CRCERRS_SHIFT 0
2401
-#define I40E_GLPRT_CRCERRS_CRCERRS_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_CRCERRS_CRCERRS_SHIFT)
2402
482
 #define I40E_GLPRT_GORCH(_i) (0x00300004 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2403
-#define I40E_GLPRT_GORCH_MAX_INDEX 3
2404
-#define I40E_GLPRT_GORCH_GORCH_SHIFT 0
2405
-#define I40E_GLPRT_GORCH_GORCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_GORCH_GORCH_SHIFT)
2406
483
 #define I40E_GLPRT_GORCL(_i) (0x00300000 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2407
-#define I40E_GLPRT_GORCL_MAX_INDEX 3
2408
-#define I40E_GLPRT_GORCL_GORCL_SHIFT 0
2409
-#define I40E_GLPRT_GORCL_GORCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_GORCL_GORCL_SHIFT)
2410
484
 #define I40E_GLPRT_GOTCH(_i) (0x00300684 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2411
-#define I40E_GLPRT_GOTCH_MAX_INDEX 3
2412
-#define I40E_GLPRT_GOTCH_GOTCH_SHIFT 0
2413
-#define I40E_GLPRT_GOTCH_GOTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_GOTCH_GOTCH_SHIFT)
2414
485
 #define I40E_GLPRT_GOTCL(_i) (0x00300680 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2415
-#define I40E_GLPRT_GOTCL_MAX_INDEX 3
2416
-#define I40E_GLPRT_GOTCL_GOTCL_SHIFT 0
2417
-#define I40E_GLPRT_GOTCL_GOTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_GOTCL_GOTCL_SHIFT)
2418
486
 #define I40E_GLPRT_ILLERRC(_i) (0x003000E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2419
-#define I40E_GLPRT_ILLERRC_MAX_INDEX 3
2420
-#define I40E_GLPRT_ILLERRC_ILLERRC_SHIFT 0
2421
-#define I40E_GLPRT_ILLERRC_ILLERRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_ILLERRC_ILLERRC_SHIFT)
2422
-#define I40E_GLPRT_LDPC(_i) (0x00300620 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2423
-#define I40E_GLPRT_LDPC_MAX_INDEX 3
2424
-#define I40E_GLPRT_LDPC_LDPC_SHIFT 0
2425
-#define I40E_GLPRT_LDPC_LDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LDPC_LDPC_SHIFT)
2426
487
 #define I40E_GLPRT_LXOFFRXC(_i) (0x00300160 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2427
-#define I40E_GLPRT_LXOFFRXC_MAX_INDEX 3
2428
-#define I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_SHIFT 0
2429
-#define I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_SHIFT)
2430
488
 #define I40E_GLPRT_LXOFFTXC(_i) (0x003009A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2431
-#define I40E_GLPRT_LXOFFTXC_MAX_INDEX 3
2432
-#define I40E_GLPRT_LXOFFTXC_LXOFFTXC_SHIFT 0
2433
-#define I40E_GLPRT_LXOFFTXC_LXOFFTXC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXOFFTXC_LXOFFTXC_SHIFT)
2434
489
 #define I40E_GLPRT_LXONRXC(_i) (0x00300140 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2435
-#define I40E_GLPRT_LXONRXC_MAX_INDEX 3
2436
-#define I40E_GLPRT_LXONRXC_LXONRXCNT_SHIFT 0
2437
-#define I40E_GLPRT_LXONRXC_LXONRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXONRXC_LXONRXCNT_SHIFT)
2438
490
 #define I40E_GLPRT_LXONTXC(_i) (0x00300980 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2439
-#define I40E_GLPRT_LXONTXC_MAX_INDEX 3
2440
-#define I40E_GLPRT_LXONTXC_LXONTXC_SHIFT 0
2441
-#define I40E_GLPRT_LXONTXC_LXONTXC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXONTXC_LXONTXC_SHIFT)
2442
491
 #define I40E_GLPRT_MLFC(_i) (0x00300020 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2443
-#define I40E_GLPRT_MLFC_MAX_INDEX 3
2444
-#define I40E_GLPRT_MLFC_MLFC_SHIFT 0
2445
-#define I40E_GLPRT_MLFC_MLFC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MLFC_MLFC_SHIFT)
2446
492
 #define I40E_GLPRT_MPRCH(_i) (0x003005C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2447
-#define I40E_GLPRT_MPRCH_MAX_INDEX 3
2448
-#define I40E_GLPRT_MPRCH_MPRCH_SHIFT 0
2449
-#define I40E_GLPRT_MPRCH_MPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_MPRCH_MPRCH_SHIFT)
2450
493
 #define I40E_GLPRT_MPRCL(_i) (0x003005C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2451
-#define I40E_GLPRT_MPRCL_MAX_INDEX 3
2452
-#define I40E_GLPRT_MPRCL_MPRCL_SHIFT 0
2453
-#define I40E_GLPRT_MPRCL_MPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MPRCL_MPRCL_SHIFT)
2454
494
 #define I40E_GLPRT_MPTCH(_i) (0x003009E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2455
-#define I40E_GLPRT_MPTCH_MAX_INDEX 3
2456
-#define I40E_GLPRT_MPTCH_MPTCH_SHIFT 0
2457
-#define I40E_GLPRT_MPTCH_MPTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_MPTCH_MPTCH_SHIFT)
2458
495
 #define I40E_GLPRT_MPTCL(_i) (0x003009E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2459
-#define I40E_GLPRT_MPTCL_MAX_INDEX 3
2460
-#define I40E_GLPRT_MPTCL_MPTCL_SHIFT 0
2461
-#define I40E_GLPRT_MPTCL_MPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MPTCL_MPTCL_SHIFT)
2462
496
 #define I40E_GLPRT_MRFC(_i) (0x00300040 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2463
-#define I40E_GLPRT_MRFC_MAX_INDEX 3
2464
-#define I40E_GLPRT_MRFC_MRFC_SHIFT 0
2465
-#define I40E_GLPRT_MRFC_MRFC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MRFC_MRFC_SHIFT)
2466
497
 #define I40E_GLPRT_PRC1023H(_i) (0x00300504 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2467
-#define I40E_GLPRT_PRC1023H_MAX_INDEX 3
2468
-#define I40E_GLPRT_PRC1023H_PRC1023H_SHIFT 0
2469
-#define I40E_GLPRT_PRC1023H_PRC1023H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC1023H_PRC1023H_SHIFT)
2470
498
 #define I40E_GLPRT_PRC1023L(_i) (0x00300500 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2471
-#define I40E_GLPRT_PRC1023L_MAX_INDEX 3
2472
-#define I40E_GLPRT_PRC1023L_PRC1023L_SHIFT 0
2473
-#define I40E_GLPRT_PRC1023L_PRC1023L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC1023L_PRC1023L_SHIFT)
2474
499
 #define I40E_GLPRT_PRC127H(_i) (0x003004A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2475
-#define I40E_GLPRT_PRC127H_MAX_INDEX 3
2476
-#define I40E_GLPRT_PRC127H_PRC127H_SHIFT 0
2477
-#define I40E_GLPRT_PRC127H_PRC127H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC127H_PRC127H_SHIFT)
2478
500
 #define I40E_GLPRT_PRC127L(_i) (0x003004A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2479
-#define I40E_GLPRT_PRC127L_MAX_INDEX 3
2480
-#define I40E_GLPRT_PRC127L_PRC127L_SHIFT 0
2481
-#define I40E_GLPRT_PRC127L_PRC127L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC127L_PRC127L_SHIFT)
2482
501
 #define I40E_GLPRT_PRC1522H(_i) (0x00300524 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2483
-#define I40E_GLPRT_PRC1522H_MAX_INDEX 3
2484
-#define I40E_GLPRT_PRC1522H_PRC1522H_SHIFT 0
2485
-#define I40E_GLPRT_PRC1522H_PRC1522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC1522H_PRC1522H_SHIFT)
2486
502
 #define I40E_GLPRT_PRC1522L(_i) (0x00300520 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2487
-#define I40E_GLPRT_PRC1522L_MAX_INDEX 3
2488
-#define I40E_GLPRT_PRC1522L_PRC1522L_SHIFT 0
2489
-#define I40E_GLPRT_PRC1522L_PRC1522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC1522L_PRC1522L_SHIFT)
2490
503
 #define I40E_GLPRT_PRC255H(_i) (0x003004C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2491
-#define I40E_GLPRT_PRC255H_MAX_INDEX 3
2492
-#define I40E_GLPRT_PRC255H_PRTPRC255H_SHIFT 0
2493
-#define I40E_GLPRT_PRC255H_PRTPRC255H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC255H_PRTPRC255H_SHIFT)
2494
504
 #define I40E_GLPRT_PRC255L(_i) (0x003004C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2495
-#define I40E_GLPRT_PRC255L_MAX_INDEX 3
2496
-#define I40E_GLPRT_PRC255L_PRC255L_SHIFT 0
2497
-#define I40E_GLPRT_PRC255L_PRC255L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC255L_PRC255L_SHIFT)
2498
505
 #define I40E_GLPRT_PRC511H(_i) (0x003004E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2499
-#define I40E_GLPRT_PRC511H_MAX_INDEX 3
2500
-#define I40E_GLPRT_PRC511H_PRC511H_SHIFT 0
2501
-#define I40E_GLPRT_PRC511H_PRC511H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC511H_PRC511H_SHIFT)
2502
506
 #define I40E_GLPRT_PRC511L(_i) (0x003004E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2503
-#define I40E_GLPRT_PRC511L_MAX_INDEX 3
2504
-#define I40E_GLPRT_PRC511L_PRC511L_SHIFT 0
2505
-#define I40E_GLPRT_PRC511L_PRC511L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC511L_PRC511L_SHIFT)
2506
507
 #define I40E_GLPRT_PRC64H(_i) (0x00300484 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2507
-#define I40E_GLPRT_PRC64H_MAX_INDEX 3
2508
-#define I40E_GLPRT_PRC64H_PRC64H_SHIFT 0
2509
-#define I40E_GLPRT_PRC64H_PRC64H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC64H_PRC64H_SHIFT)
2510
508
 #define I40E_GLPRT_PRC64L(_i) (0x00300480 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2511
-#define I40E_GLPRT_PRC64L_MAX_INDEX 3
2512
-#define I40E_GLPRT_PRC64L_PRC64L_SHIFT 0
2513
-#define I40E_GLPRT_PRC64L_PRC64L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC64L_PRC64L_SHIFT)
2514
509
 #define I40E_GLPRT_PRC9522H(_i) (0x00300544 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2515
-#define I40E_GLPRT_PRC9522H_MAX_INDEX 3
2516
-#define I40E_GLPRT_PRC9522H_PRC1522H_SHIFT 0
2517
-#define I40E_GLPRT_PRC9522H_PRC1522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC9522H_PRC1522H_SHIFT)
2518
510
 #define I40E_GLPRT_PRC9522L(_i) (0x00300540 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2519
-#define I40E_GLPRT_PRC9522L_MAX_INDEX 3
2520
-#define I40E_GLPRT_PRC9522L_PRC1522L_SHIFT 0
2521
-#define I40E_GLPRT_PRC9522L_PRC1522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC9522L_PRC1522L_SHIFT)
2522
511
 #define I40E_GLPRT_PTC1023H(_i) (0x00300724 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2523
-#define I40E_GLPRT_PTC1023H_MAX_INDEX 3
2524
-#define I40E_GLPRT_PTC1023H_PTC1023H_SHIFT 0
2525
-#define I40E_GLPRT_PTC1023H_PTC1023H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC1023H_PTC1023H_SHIFT)
2526
512
 #define I40E_GLPRT_PTC1023L(_i) (0x00300720 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2527
-#define I40E_GLPRT_PTC1023L_MAX_INDEX 3
2528
-#define I40E_GLPRT_PTC1023L_PTC1023L_SHIFT 0
2529
-#define I40E_GLPRT_PTC1023L_PTC1023L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC1023L_PTC1023L_SHIFT)
2530
513
 #define I40E_GLPRT_PTC127H(_i) (0x003006C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2531
-#define I40E_GLPRT_PTC127H_MAX_INDEX 3
2532
-#define I40E_GLPRT_PTC127H_PTC127H_SHIFT 0
2533
-#define I40E_GLPRT_PTC127H_PTC127H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC127H_PTC127H_SHIFT)
2534
514
 #define I40E_GLPRT_PTC127L(_i) (0x003006C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2535
-#define I40E_GLPRT_PTC127L_MAX_INDEX 3
2536
-#define I40E_GLPRT_PTC127L_PTC127L_SHIFT 0
2537
-#define I40E_GLPRT_PTC127L_PTC127L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC127L_PTC127L_SHIFT)
2538
515
 #define I40E_GLPRT_PTC1522H(_i) (0x00300744 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2539
-#define I40E_GLPRT_PTC1522H_MAX_INDEX 3
2540
-#define I40E_GLPRT_PTC1522H_PTC1522H_SHIFT 0
2541
-#define I40E_GLPRT_PTC1522H_PTC1522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC1522H_PTC1522H_SHIFT)
2542
516
 #define I40E_GLPRT_PTC1522L(_i) (0x00300740 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2543
-#define I40E_GLPRT_PTC1522L_MAX_INDEX 3
2544
-#define I40E_GLPRT_PTC1522L_PTC1522L_SHIFT 0
2545
-#define I40E_GLPRT_PTC1522L_PTC1522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC1522L_PTC1522L_SHIFT)
2546
517
 #define I40E_GLPRT_PTC255H(_i) (0x003006E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2547
-#define I40E_GLPRT_PTC255H_MAX_INDEX 3
2548
-#define I40E_GLPRT_PTC255H_PTC255H_SHIFT 0
2549
-#define I40E_GLPRT_PTC255H_PTC255H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC255H_PTC255H_SHIFT)
2550
518
 #define I40E_GLPRT_PTC255L(_i) (0x003006E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2551
-#define I40E_GLPRT_PTC255L_MAX_INDEX 3
2552
-#define I40E_GLPRT_PTC255L_PTC255L_SHIFT 0
2553
-#define I40E_GLPRT_PTC255L_PTC255L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC255L_PTC255L_SHIFT)
2554
519
 #define I40E_GLPRT_PTC511H(_i) (0x00300704 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2555
-#define I40E_GLPRT_PTC511H_MAX_INDEX 3
2556
-#define I40E_GLPRT_PTC511H_PTC511H_SHIFT 0
2557
-#define I40E_GLPRT_PTC511H_PTC511H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC511H_PTC511H_SHIFT)
2558
520
 #define I40E_GLPRT_PTC511L(_i) (0x00300700 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2559
-#define I40E_GLPRT_PTC511L_MAX_INDEX 3
2560
-#define I40E_GLPRT_PTC511L_PTC511L_SHIFT 0
2561
-#define I40E_GLPRT_PTC511L_PTC511L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC511L_PTC511L_SHIFT)
2562
521
 #define I40E_GLPRT_PTC64H(_i) (0x003006A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2563
-#define I40E_GLPRT_PTC64H_MAX_INDEX 3
2564
-#define I40E_GLPRT_PTC64H_PTC64H_SHIFT 0
2565
-#define I40E_GLPRT_PTC64H_PTC64H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC64H_PTC64H_SHIFT)
2566
522
 #define I40E_GLPRT_PTC64L(_i) (0x003006A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2567
-#define I40E_GLPRT_PTC64L_MAX_INDEX 3
2568
-#define I40E_GLPRT_PTC64L_PTC64L_SHIFT 0
2569
-#define I40E_GLPRT_PTC64L_PTC64L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC64L_PTC64L_SHIFT)
2570
523
 #define I40E_GLPRT_PTC9522H(_i) (0x00300764 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2571
-#define I40E_GLPRT_PTC9522H_MAX_INDEX 3
2572
-#define I40E_GLPRT_PTC9522H_PTC9522H_SHIFT 0
2573
-#define I40E_GLPRT_PTC9522H_PTC9522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC9522H_PTC9522H_SHIFT)
2574
524
 #define I40E_GLPRT_PTC9522L(_i) (0x00300760 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2575
-#define I40E_GLPRT_PTC9522L_MAX_INDEX 3
2576
-#define I40E_GLPRT_PTC9522L_PTC9522L_SHIFT 0
2577
-#define I40E_GLPRT_PTC9522L_PTC9522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC9522L_PTC9522L_SHIFT)
2578
525
 #define I40E_GLPRT_PXOFFRXC(_i, _j) (0x00300280 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
2579
-#define I40E_GLPRT_PXOFFRXC_MAX_INDEX 3
2580
-#define I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_SHIFT 0
2581
-#define I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_SHIFT)
2582
526
 #define I40E_GLPRT_PXOFFTXC(_i, _j) (0x00300880 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
2583
-#define I40E_GLPRT_PXOFFTXC_MAX_INDEX 3
2584
-#define I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_SHIFT 0
2585
-#define I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_SHIFT)
2586
527
 #define I40E_GLPRT_PXONRXC(_i, _j) (0x00300180 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
2587
-#define I40E_GLPRT_PXONRXC_MAX_INDEX 3
2588
-#define I40E_GLPRT_PXONRXC_PRPXONRXCNT_SHIFT 0
2589
-#define I40E_GLPRT_PXONRXC_PRPXONRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXONRXC_PRPXONRXCNT_SHIFT)
2590
528
 #define I40E_GLPRT_PXONTXC(_i, _j) (0x00300780 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
2591
-#define I40E_GLPRT_PXONTXC_MAX_INDEX 3
2592
-#define I40E_GLPRT_PXONTXC_PRPXONTXC_SHIFT 0
2593
-#define I40E_GLPRT_PXONTXC_PRPXONTXC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXONTXC_PRPXONTXC_SHIFT)
2594
529
 #define I40E_GLPRT_RDPC(_i) (0x00300600 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2595
-#define I40E_GLPRT_RDPC_MAX_INDEX 3
2596
-#define I40E_GLPRT_RDPC_RDPC_SHIFT 0
2597
-#define I40E_GLPRT_RDPC_RDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RDPC_RDPC_SHIFT)
2598
530
 #define I40E_GLPRT_RFC(_i) (0x00300560 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2599
-#define I40E_GLPRT_RFC_MAX_INDEX 3
2600
-#define I40E_GLPRT_RFC_RFC_SHIFT 0
2601
-#define I40E_GLPRT_RFC_RFC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RFC_RFC_SHIFT)
2602
531
 #define I40E_GLPRT_RJC(_i) (0x00300580 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2603
-#define I40E_GLPRT_RJC_MAX_INDEX 3
2604
-#define I40E_GLPRT_RJC_RJC_SHIFT 0
2605
-#define I40E_GLPRT_RJC_RJC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RJC_RJC_SHIFT)
2606
532
 #define I40E_GLPRT_RLEC(_i) (0x003000A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2607
-#define I40E_GLPRT_RLEC_MAX_INDEX 3
2608
-#define I40E_GLPRT_RLEC_RLEC_SHIFT 0
2609
-#define I40E_GLPRT_RLEC_RLEC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RLEC_RLEC_SHIFT)
2610
533
 #define I40E_GLPRT_ROC(_i) (0x00300120 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2611
-#define I40E_GLPRT_ROC_MAX_INDEX 3
2612
-#define I40E_GLPRT_ROC_ROC_SHIFT 0
2613
-#define I40E_GLPRT_ROC_ROC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_ROC_ROC_SHIFT)
2614
534
 #define I40E_GLPRT_RUC(_i) (0x00300100 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2615
-#define I40E_GLPRT_RUC_MAX_INDEX 3
2616
-#define I40E_GLPRT_RUC_RUC_SHIFT 0
2617
-#define I40E_GLPRT_RUC_RUC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RUC_RUC_SHIFT)
2618
-#define I40E_GLPRT_RUPP(_i) (0x00300660 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2619
-#define I40E_GLPRT_RUPP_MAX_INDEX 3
2620
-#define I40E_GLPRT_RUPP_RUPP_SHIFT 0
2621
-#define I40E_GLPRT_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RUPP_RUPP_SHIFT)
2622
535
 #define I40E_GLPRT_RXON2OFFCNT(_i, _j) (0x00300380 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */
2623
-#define I40E_GLPRT_RXON2OFFCNT_MAX_INDEX 3
2624
-#define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT 0
2625
-#define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT)
2626
536
 #define I40E_GLPRT_TDOLD(_i) (0x00300A20 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2627
-#define I40E_GLPRT_TDOLD_MAX_INDEX 3
2628
-#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT 0
2629
-#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT)
2630
537
 #define I40E_GLPRT_UPRCH(_i) (0x003005A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2631
-#define I40E_GLPRT_UPRCH_MAX_INDEX 3
2632
-#define I40E_GLPRT_UPRCH_UPRCH_SHIFT 0
2633
-#define I40E_GLPRT_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_UPRCH_UPRCH_SHIFT)
2634
538
 #define I40E_GLPRT_UPRCL(_i) (0x003005A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2635
-#define I40E_GLPRT_UPRCL_MAX_INDEX 3
2636
-#define I40E_GLPRT_UPRCL_UPRCL_SHIFT 0
2637
-#define I40E_GLPRT_UPRCL_UPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_UPRCL_UPRCL_SHIFT)
2638
539
 #define I40E_GLPRT_UPTCH(_i) (0x003009C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2639
-#define I40E_GLPRT_UPTCH_MAX_INDEX 3
2640
-#define I40E_GLPRT_UPTCH_UPTCH_SHIFT 0
2641
-#define I40E_GLPRT_UPTCH_UPTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_UPTCH_UPTCH_SHIFT)
2642
540
 #define I40E_GLPRT_UPTCL(_i) (0x003009C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
2643
-#define I40E_GLPRT_UPTCL_MAX_INDEX 3
2644
-#define I40E_GLPRT_UPTCL_VUPTCH_SHIFT 0
2645
-#define I40E_GLPRT_UPTCL_VUPTCH_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_UPTCL_VUPTCH_SHIFT)
2646
541
 #define I40E_GLSW_BPRCH(_i) (0x00370104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
2647
-#define I40E_GLSW_BPRCH_MAX_INDEX 15
2648
-#define I40E_GLSW_BPRCH_BPRCH_SHIFT 0
2649
-#define I40E_GLSW_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_BPRCH_BPRCH_SHIFT)
2650
542
 #define I40E_GLSW_BPRCL(_i) (0x00370100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
2651
-#define I40E_GLSW_BPRCL_MAX_INDEX 15
2652
-#define I40E_GLSW_BPRCL_BPRCL_SHIFT 0
2653
-#define I40E_GLSW_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_BPRCL_BPRCL_SHIFT)
2654
543
 #define I40E_GLSW_BPTCH(_i) (0x00340104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
2655
-#define I40E_GLSW_BPTCH_MAX_INDEX 15
2656
-#define I40E_GLSW_BPTCH_BPTCH_SHIFT 0
2657
-#define I40E_GLSW_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_BPTCH_BPTCH_SHIFT)
2658
544
 #define I40E_GLSW_BPTCL(_i) (0x00340100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
2659
-#define I40E_GLSW_BPTCL_MAX_INDEX 15
2660
-#define I40E_GLSW_BPTCL_BPTCL_SHIFT 0
2661
-#define I40E_GLSW_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_BPTCL_BPTCL_SHIFT)
2662
545
 #define I40E_GLSW_GORCH(_i) (0x0035C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
2663
-#define I40E_GLSW_GORCH_MAX_INDEX 15
2664
-#define I40E_GLSW_GORCH_GORCH_SHIFT 0
2665
-#define I40E_GLSW_GORCH_GORCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_GORCH_GORCH_SHIFT)
2666
546
 #define I40E_GLSW_GORCL(_i) (0x0035c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
2667
-#define I40E_GLSW_GORCL_MAX_INDEX 15
2668
-#define I40E_GLSW_GORCL_GORCL_SHIFT 0
2669
-#define I40E_GLSW_GORCL_GORCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_GORCL_GORCL_SHIFT)
2670
547
 #define I40E_GLSW_GOTCH(_i) (0x0032C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
2671
-#define I40E_GLSW_GOTCH_MAX_INDEX 15
2672
-#define I40E_GLSW_GOTCH_GOTCH_SHIFT 0
2673
-#define I40E_GLSW_GOTCH_GOTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_GOTCH_GOTCH_SHIFT)
2674
548
 #define I40E_GLSW_GOTCL(_i) (0x0032c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
2675
-#define I40E_GLSW_GOTCL_MAX_INDEX 15
2676
-#define I40E_GLSW_GOTCL_GOTCL_SHIFT 0
2677
-#define I40E_GLSW_GOTCL_GOTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_GOTCL_GOTCL_SHIFT)
2678
549
 #define I40E_GLSW_MPRCH(_i) (0x00370084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
2679
-#define I40E_GLSW_MPRCH_MAX_INDEX 15
2680
-#define I40E_GLSW_MPRCH_MPRCH_SHIFT 0
2681
-#define I40E_GLSW_MPRCH_MPRCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_MPRCH_MPRCH_SHIFT)
2682
550
 #define I40E_GLSW_MPRCL(_i) (0x00370080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
2683
-#define I40E_GLSW_MPRCL_MAX_INDEX 15
2684
-#define I40E_GLSW_MPRCL_MPRCL_SHIFT 0
2685
-#define I40E_GLSW_MPRCL_MPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_MPRCL_MPRCL_SHIFT)
2686
551
 #define I40E_GLSW_MPTCH(_i) (0x00340084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
2687
-#define I40E_GLSW_MPTCH_MAX_INDEX 15
2688
-#define I40E_GLSW_MPTCH_MPTCH_SHIFT 0
2689
-#define I40E_GLSW_MPTCH_MPTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_MPTCH_MPTCH_SHIFT)
2690
552
 #define I40E_GLSW_MPTCL(_i) (0x00340080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
2691
-#define I40E_GLSW_MPTCL_MAX_INDEX 15
2692
-#define I40E_GLSW_MPTCL_MPTCL_SHIFT 0
2693
-#define I40E_GLSW_MPTCL_MPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_MPTCL_MPTCL_SHIFT)
2694
553
 #define I40E_GLSW_RUPP(_i) (0x00370180 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
2695
-#define I40E_GLSW_RUPP_MAX_INDEX 15
2696
-#define I40E_GLSW_RUPP_RUPP_SHIFT 0
2697
-#define I40E_GLSW_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_RUPP_RUPP_SHIFT)
2698
554
 #define I40E_GLSW_TDPC(_i) (0x00348000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
2699
-#define I40E_GLSW_TDPC_MAX_INDEX 15
2700
-#define I40E_GLSW_TDPC_TDPC_SHIFT 0
2701
-#define I40E_GLSW_TDPC_TDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_TDPC_TDPC_SHIFT)
2702
555
 #define I40E_GLSW_UPRCH(_i) (0x00370004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
2703
-#define I40E_GLSW_UPRCH_MAX_INDEX 15
2704
-#define I40E_GLSW_UPRCH_UPRCH_SHIFT 0
2705
-#define I40E_GLSW_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_UPRCH_UPRCH_SHIFT)
2706
556
 #define I40E_GLSW_UPRCL(_i) (0x00370000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
2707
-#define I40E_GLSW_UPRCL_MAX_INDEX 15
2708
-#define I40E_GLSW_UPRCL_UPRCL_SHIFT 0
2709
-#define I40E_GLSW_UPRCL_UPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_UPRCL_UPRCL_SHIFT)
2710
557
 #define I40E_GLSW_UPTCH(_i) (0x00340004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
2711
-#define I40E_GLSW_UPTCH_MAX_INDEX 15
2712
-#define I40E_GLSW_UPTCH_UPTCH_SHIFT 0
2713
-#define I40E_GLSW_UPTCH_UPTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_UPTCH_UPTCH_SHIFT)
2714
558
 #define I40E_GLSW_UPTCL(_i) (0x00340000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */
2715
-#define I40E_GLSW_UPTCL_MAX_INDEX 15
2716
-#define I40E_GLSW_UPTCL_UPTCL_SHIFT 0
2717
-#define I40E_GLSW_UPTCL_UPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_UPTCL_UPTCL_SHIFT)
2718
559
 #define I40E_GLV_BPRCH(_i) (0x0036D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
2719
-#define I40E_GLV_BPRCH_MAX_INDEX 383
2720
-#define I40E_GLV_BPRCH_BPRCH_SHIFT 0
2721
-#define I40E_GLV_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_BPRCH_BPRCH_SHIFT)
2722
560
 #define I40E_GLV_BPRCL(_i) (0x0036d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
2723
-#define I40E_GLV_BPRCL_MAX_INDEX 383
2724
-#define I40E_GLV_BPRCL_BPRCL_SHIFT 0
2725
-#define I40E_GLV_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_BPRCL_BPRCL_SHIFT)
2726
561
 #define I40E_GLV_BPTCH(_i) (0x0033D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
2727
-#define I40E_GLV_BPTCH_MAX_INDEX 383
2728
-#define I40E_GLV_BPTCH_BPTCH_SHIFT 0
2729
-#define I40E_GLV_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_BPTCH_BPTCH_SHIFT)
2730
562
 #define I40E_GLV_BPTCL(_i) (0x0033d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
2731
-#define I40E_GLV_BPTCL_MAX_INDEX 383
2732
-#define I40E_GLV_BPTCL_BPTCL_SHIFT 0
2733
-#define I40E_GLV_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_BPTCL_BPTCL_SHIFT)
2734
563
 #define I40E_GLV_GORCH(_i) (0x00358004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
2735
-#define I40E_GLV_GORCH_MAX_INDEX 383
2736
-#define I40E_GLV_GORCH_GORCH_SHIFT 0
2737
-#define I40E_GLV_GORCH_GORCH_MASK I40E_MASK(0xFFFF, I40E_GLV_GORCH_GORCH_SHIFT)
2738
564
 #define I40E_GLV_GORCL(_i) (0x00358000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
2739
-#define I40E_GLV_GORCL_MAX_INDEX 383
2740
-#define I40E_GLV_GORCL_GORCL_SHIFT 0
2741
-#define I40E_GLV_GORCL_GORCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_GORCL_GORCL_SHIFT)
2742
565
 #define I40E_GLV_GOTCH(_i) (0x00328004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
2743
-#define I40E_GLV_GOTCH_MAX_INDEX 383
2744
-#define I40E_GLV_GOTCH_GOTCH_SHIFT 0
2745
-#define I40E_GLV_GOTCH_GOTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_GOTCH_GOTCH_SHIFT)
2746
566
 #define I40E_GLV_GOTCL(_i) (0x00328000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
2747
-#define I40E_GLV_GOTCL_MAX_INDEX 383
2748
-#define I40E_GLV_GOTCL_GOTCL_SHIFT 0
2749
-#define I40E_GLV_GOTCL_GOTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_GOTCL_GOTCL_SHIFT)
2750
567
 #define I40E_GLV_MPRCH(_i) (0x0036CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
2751
-#define I40E_GLV_MPRCH_MAX_INDEX 383
2752
-#define I40E_GLV_MPRCH_MPRCH_SHIFT 0
2753
-#define I40E_GLV_MPRCH_MPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_MPRCH_MPRCH_SHIFT)
2754
568
 #define I40E_GLV_MPRCL(_i) (0x0036cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
2755
-#define I40E_GLV_MPRCL_MAX_INDEX 383
2756
-#define I40E_GLV_MPRCL_MPRCL_SHIFT 0
2757
-#define I40E_GLV_MPRCL_MPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_MPRCL_MPRCL_SHIFT)
2758
569
 #define I40E_GLV_MPTCH(_i) (0x0033CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
2759
-#define I40E_GLV_MPTCH_MAX_INDEX 383
2760
-#define I40E_GLV_MPTCH_MPTCH_SHIFT 0
2761
-#define I40E_GLV_MPTCH_MPTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_MPTCH_MPTCH_SHIFT)
2762
570
 #define I40E_GLV_MPTCL(_i) (0x0033cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
2763
-#define I40E_GLV_MPTCL_MAX_INDEX 383
2764
-#define I40E_GLV_MPTCL_MPTCL_SHIFT 0
2765
-#define I40E_GLV_MPTCL_MPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_MPTCL_MPTCL_SHIFT)
2766
571
 #define I40E_GLV_RDPC(_i) (0x00310000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
2767
-#define I40E_GLV_RDPC_MAX_INDEX 383
2768
-#define I40E_GLV_RDPC_RDPC_SHIFT 0
2769
-#define I40E_GLV_RDPC_RDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_RDPC_RDPC_SHIFT)
2770
572
 #define I40E_GLV_RUPP(_i) (0x0036E400 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
2771
-#define I40E_GLV_RUPP_MAX_INDEX 383
2772
-#define I40E_GLV_RUPP_RUPP_SHIFT 0
2773
-#define I40E_GLV_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_RUPP_RUPP_SHIFT)
2774
573
 #define I40E_GLV_TEPC(_i) (0x00344000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
2775
-#define I40E_GLV_TEPC_MAX_INDEX 383
2776
-#define I40E_GLV_TEPC_TEPC_SHIFT 0
2777
-#define I40E_GLV_TEPC_TEPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_TEPC_TEPC_SHIFT)
2778
574
 #define I40E_GLV_UPRCH(_i) (0x0036C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
2779
-#define I40E_GLV_UPRCH_MAX_INDEX 383
2780
-#define I40E_GLV_UPRCH_UPRCH_SHIFT 0
2781
-#define I40E_GLV_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_UPRCH_UPRCH_SHIFT)
2782
575
 #define I40E_GLV_UPRCL(_i) (0x0036c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
2783
-#define I40E_GLV_UPRCL_MAX_INDEX 383
2784
-#define I40E_GLV_UPRCL_UPRCL_SHIFT 0
2785
-#define I40E_GLV_UPRCL_UPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_UPRCL_UPRCL_SHIFT)
2786
576
 #define I40E_GLV_UPTCH(_i) (0x0033C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
2787
-#define I40E_GLV_UPTCH_MAX_INDEX 383
2788
-#define I40E_GLV_UPTCH_GLVUPTCH_SHIFT 0
2789
-#define I40E_GLV_UPTCH_GLVUPTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_UPTCH_GLVUPTCH_SHIFT)
2790
577
 #define I40E_GLV_UPTCL(_i) (0x0033c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */
2791
-#define I40E_GLV_UPTCL_MAX_INDEX 383
2792
-#define I40E_GLV_UPTCL_UPTCL_SHIFT 0
2793
-#define I40E_GLV_UPTCL_UPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_UPTCL_UPTCL_SHIFT)
2794
578
 #define I40E_GLVEBTC_RBCH(_i, _j) (0x00364004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
2795
-#define I40E_GLVEBTC_RBCH_MAX_INDEX 7
2796
-#define I40E_GLVEBTC_RBCH_TCBCH_SHIFT 0
2797
-#define I40E_GLVEBTC_RBCH_TCBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_RBCH_TCBCH_SHIFT)
2798
579
 #define I40E_GLVEBTC_RBCL(_i, _j) (0x00364000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
2799
-#define I40E_GLVEBTC_RBCL_MAX_INDEX 7
2800
-#define I40E_GLVEBTC_RBCL_TCBCL_SHIFT 0
2801
-#define I40E_GLVEBTC_RBCL_TCBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_RBCL_TCBCL_SHIFT)
2802
580
 #define I40E_GLVEBTC_RPCH(_i, _j) (0x00368004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
2803
-#define I40E_GLVEBTC_RPCH_MAX_INDEX 7
2804
-#define I40E_GLVEBTC_RPCH_TCPCH_SHIFT 0
2805
-#define I40E_GLVEBTC_RPCH_TCPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_RPCH_TCPCH_SHIFT)
2806
581
 #define I40E_GLVEBTC_RPCL(_i, _j) (0x00368000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
2807
-#define I40E_GLVEBTC_RPCL_MAX_INDEX 7
2808
-#define I40E_GLVEBTC_RPCL_TCPCL_SHIFT 0
2809
-#define I40E_GLVEBTC_RPCL_TCPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_RPCL_TCPCL_SHIFT)
2810
582
 #define I40E_GLVEBTC_TBCH(_i, _j) (0x00334004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
2811
-#define I40E_GLVEBTC_TBCH_MAX_INDEX 7
2812
-#define I40E_GLVEBTC_TBCH_TCBCH_SHIFT 0
2813
-#define I40E_GLVEBTC_TBCH_TCBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_TBCH_TCBCH_SHIFT)
2814
583
 #define I40E_GLVEBTC_TBCL(_i, _j) (0x00334000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
2815
-#define I40E_GLVEBTC_TBCL_MAX_INDEX 7
2816
-#define I40E_GLVEBTC_TBCL_TCBCL_SHIFT 0
2817
-#define I40E_GLVEBTC_TBCL_TCBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_TBCL_TCBCL_SHIFT)
2818
584
 #define I40E_GLVEBTC_TPCH(_i, _j) (0x00338004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
2819
-#define I40E_GLVEBTC_TPCH_MAX_INDEX 7
2820
-#define I40E_GLVEBTC_TPCH_TCPCH_SHIFT 0
2821
-#define I40E_GLVEBTC_TPCH_TCPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_TPCH_TCPCH_SHIFT)
2822
585
 #define I40E_GLVEBTC_TPCL(_i, _j) (0x00338000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */
2823
-#define I40E_GLVEBTC_TPCL_MAX_INDEX 7
2824
-#define I40E_GLVEBTC_TPCL_TCPCL_SHIFT 0
2825
-#define I40E_GLVEBTC_TPCL_TCPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_TPCL_TCPCL_SHIFT)
2826
-#define I40E_GLVEBVL_BPCH(_i) (0x00374804 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
2827
-#define I40E_GLVEBVL_BPCH_MAX_INDEX 127
2828
-#define I40E_GLVEBVL_BPCH_VLBPCH_SHIFT 0
2829
-#define I40E_GLVEBVL_BPCH_VLBPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_BPCH_VLBPCH_SHIFT)
2830
-#define I40E_GLVEBVL_BPCL(_i) (0x00374800 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
2831
-#define I40E_GLVEBVL_BPCL_MAX_INDEX 127
2832
-#define I40E_GLVEBVL_BPCL_VLBPCL_SHIFT 0
2833
-#define I40E_GLVEBVL_BPCL_VLBPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_BPCL_VLBPCL_SHIFT)
2834
-#define I40E_GLVEBVL_GORCH(_i) (0x00360004 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
2835
-#define I40E_GLVEBVL_GORCH_MAX_INDEX 127
2836
-#define I40E_GLVEBVL_GORCH_VLBCH_SHIFT 0
2837
-#define I40E_GLVEBVL_GORCH_VLBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_GORCH_VLBCH_SHIFT)
2838
-#define I40E_GLVEBVL_GORCL(_i) (0x00360000 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
2839
-#define I40E_GLVEBVL_GORCL_MAX_INDEX 127
2840
-#define I40E_GLVEBVL_GORCL_VLBCL_SHIFT 0
2841
-#define I40E_GLVEBVL_GORCL_VLBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_GORCL_VLBCL_SHIFT)
2842
-#define I40E_GLVEBVL_GOTCH(_i) (0x00330004 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
2843
-#define I40E_GLVEBVL_GOTCH_MAX_INDEX 127
2844
-#define I40E_GLVEBVL_GOTCH_VLBCH_SHIFT 0
2845
-#define I40E_GLVEBVL_GOTCH_VLBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_GOTCH_VLBCH_SHIFT)
2846
-#define I40E_GLVEBVL_GOTCL(_i) (0x00330000 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
2847
-#define I40E_GLVEBVL_GOTCL_MAX_INDEX 127
2848
-#define I40E_GLVEBVL_GOTCL_VLBCL_SHIFT 0
2849
-#define I40E_GLVEBVL_GOTCL_VLBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_GOTCL_VLBCL_SHIFT)
2850
-#define I40E_GLVEBVL_MPCH(_i) (0x00374404 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
2851
-#define I40E_GLVEBVL_MPCH_MAX_INDEX 127
2852
-#define I40E_GLVEBVL_MPCH_VLMPCH_SHIFT 0
2853
-#define I40E_GLVEBVL_MPCH_VLMPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_MPCH_VLMPCH_SHIFT)
2854
-#define I40E_GLVEBVL_MPCL(_i) (0x00374400 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
2855
-#define I40E_GLVEBVL_MPCL_MAX_INDEX 127
2856
-#define I40E_GLVEBVL_MPCL_VLMPCL_SHIFT 0
2857
-#define I40E_GLVEBVL_MPCL_VLMPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_MPCL_VLMPCL_SHIFT)
2858
-#define I40E_GLVEBVL_UPCH(_i) (0x00374004 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
2859
-#define I40E_GLVEBVL_UPCH_MAX_INDEX 127
2860
-#define I40E_GLVEBVL_UPCH_VLUPCH_SHIFT 0
2861
-#define I40E_GLVEBVL_UPCH_VLUPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_UPCH_VLUPCH_SHIFT)
2862
-#define I40E_GLVEBVL_UPCL(_i) (0x00374000 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */
2863
-#define I40E_GLVEBVL_UPCL_MAX_INDEX 127
2864
-#define I40E_GLVEBVL_UPCL_VLUPCL_SHIFT 0
2865
-#define I40E_GLVEBVL_UPCL_VLUPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_UPCL_VLUPCL_SHIFT)
2866
-#define I40E_GL_MTG_FLU_MSK_H 0x00269F4C /* Reset: CORER */
2867
-#define I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_SHIFT 0
2868
-#define I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_MASK I40E_MASK(0xFFFF, I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_SHIFT)
2869
-#define I40E_GL_SWR_DEF_ACT(_i) (0x00270200 + ((_i) * 4)) /* _i=0...35 */ /* Reset: CORER */
2870
-#define I40E_GL_SWR_DEF_ACT_MAX_INDEX 35
2871
-#define I40E_GL_SWR_DEF_ACT_DEF_ACTION_SHIFT 0
2872
-#define I40E_GL_SWR_DEF_ACT_DEF_ACTION_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_SWR_DEF_ACT_DEF_ACTION_SHIFT)
2873
-#define I40E_GL_SWR_DEF_ACT_EN(_i) (0x0026CFB8 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
2874
-#define I40E_GL_SWR_DEF_ACT_EN_MAX_INDEX 1
2875
-#define I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_SHIFT 0
2876
-#define I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_SHIFT)
2877
-#define I40E_PRTTSYN_ADJ 0x001E4280 /* Reset: GLOBR */
2878
-#define I40E_PRTTSYN_ADJ_TSYNADJ_SHIFT 0
2879
-#define I40E_PRTTSYN_ADJ_TSYNADJ_MASK I40E_MASK(0x7FFFFFFF, I40E_PRTTSYN_ADJ_TSYNADJ_SHIFT)
2880
-#define I40E_PRTTSYN_ADJ_SIGN_SHIFT 31
2881
-#define I40E_PRTTSYN_ADJ_SIGN_MASK I40E_MASK(0x1, I40E_PRTTSYN_ADJ_SIGN_SHIFT)
2882
-#define I40E_PRTTSYN_AUX_0(_i) (0x001E42A0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
2883
-#define I40E_PRTTSYN_AUX_0_MAX_INDEX 1
2884
-#define I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT 0
2885
-#define I40E_PRTTSYN_AUX_0_OUT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT)
2886
-#define I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT 1
2887
-#define I40E_PRTTSYN_AUX_0_OUTMOD_MASK I40E_MASK(0x3, I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT)
2888
-#define I40E_PRTTSYN_AUX_0_OUTLVL_SHIFT 3
2889
-#define I40E_PRTTSYN_AUX_0_OUTLVL_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_0_OUTLVL_SHIFT)
2890
-#define I40E_PRTTSYN_AUX_0_PULSEW_SHIFT 8
2891
-#define I40E_PRTTSYN_AUX_0_PULSEW_MASK I40E_MASK(0xF, I40E_PRTTSYN_AUX_0_PULSEW_SHIFT)
2892
-#define I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT 16
2893
-#define I40E_PRTTSYN_AUX_0_EVNTLVL_MASK I40E_MASK(0x3, I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT)
2894
-#define I40E_PRTTSYN_AUX_1(_i) (0x001E42E0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
2895
-#define I40E_PRTTSYN_AUX_1_MAX_INDEX 1
2896
-#define I40E_PRTTSYN_AUX_1_INSTNT_SHIFT 0
2897
-#define I40E_PRTTSYN_AUX_1_INSTNT_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_1_INSTNT_SHIFT)
2898
-#define I40E_PRTTSYN_AUX_1_SAMPLE_TIME_SHIFT 1
2899
-#define I40E_PRTTSYN_AUX_1_SAMPLE_TIME_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_1_SAMPLE_TIME_SHIFT)
2900
-#define I40E_PRTTSYN_CLKO(_i) (0x001E4240 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
2901
-#define I40E_PRTTSYN_CLKO_MAX_INDEX 1
2902
-#define I40E_PRTTSYN_CLKO_TSYNCLKO_SHIFT 0
2903
-#define I40E_PRTTSYN_CLKO_TSYNCLKO_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_CLKO_TSYNCLKO_SHIFT)
2904
586
 #define I40E_PRTTSYN_CTL0 0x001E4200 /* Reset: GLOBR */
2905
-#define I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_SHIFT 0
2906
-#define I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_SHIFT)
2907
587
 #define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT 1
2908
588
 #define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT)
2909
-#define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT 2
2910
-#define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT)
2911
-#define I40E_PRTTSYN_CTL0_TGT_INT_ENA_SHIFT 3
2912
-#define I40E_PRTTSYN_CTL0_TGT_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TGT_INT_ENA_SHIFT)
2913
589
 #define I40E_PRTTSYN_CTL0_PF_ID_SHIFT 8
2914
590
 #define I40E_PRTTSYN_CTL0_PF_ID_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL0_PF_ID_SHIFT)
2915
-#define I40E_PRTTSYN_CTL0_TSYNACT_SHIFT 12
2916
-#define I40E_PRTTSYN_CTL0_TSYNACT_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL0_TSYNACT_SHIFT)
2917
591
 #define I40E_PRTTSYN_CTL0_TSYNENA_SHIFT 31
2918
592
 #define I40E_PRTTSYN_CTL0_TSYNENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TSYNENA_SHIFT)
2919
593
 #define I40E_PRTTSYN_CTL1 0x00085020 /* Reset: CORER */
2920
594
 #define I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT 0
2921
595
 #define I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK I40E_MASK(0xFF, I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT)
2922
-#define I40E_PRTTSYN_CTL1_V1MESSTYPE1_SHIFT 8
2923
-#define I40E_PRTTSYN_CTL1_V1MESSTYPE1_MASK I40E_MASK(0xFF, I40E_PRTTSYN_CTL1_V1MESSTYPE1_SHIFT)
2924
596
 #define I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT 16
2925
597
 #define I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT)
2926
-#define I40E_PRTTSYN_CTL1_V2MESSTYPE1_SHIFT 20
2927
-#define I40E_PRTTSYN_CTL1_V2MESSTYPE1_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL1_V2MESSTYPE1_SHIFT)
2928
598
 #define I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT 24
2929
-#define I40E_PRTTSYN_CTL1_TSYNTYPE_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
2930
599
 #define I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT 26
2931
600
 #define I40E_PRTTSYN_CTL1_UDP_ENA_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT)
2932
601
 #define I40E_PRTTSYN_CTL1_TSYNENA_SHIFT 31
2933
602
 #define I40E_PRTTSYN_CTL1_TSYNENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL1_TSYNENA_SHIFT)
2934
-#define I40E_PRTTSYN_EVNT_H(_i) (0x001E40C0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
2935
-#define I40E_PRTTSYN_EVNT_H_MAX_INDEX 1
2936
-#define I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_SHIFT 0
2937
-#define I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_SHIFT)
2938
-#define I40E_PRTTSYN_EVNT_L(_i) (0x001E4080 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
2939
-#define I40E_PRTTSYN_EVNT_L_MAX_INDEX 1
2940
-#define I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_SHIFT 0
2941
-#define I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_SHIFT)
2942
603
 #define I40E_PRTTSYN_INC_H 0x001E4060 /* Reset: GLOBR */
2943
-#define I40E_PRTTSYN_INC_H_TSYNINC_H_SHIFT 0
2944
-#define I40E_PRTTSYN_INC_H_TSYNINC_H_MASK I40E_MASK(0x3F, I40E_PRTTSYN_INC_H_TSYNINC_H_SHIFT)
2945
604
 #define I40E_PRTTSYN_INC_L 0x001E4040 /* Reset: GLOBR */
2946
-#define I40E_PRTTSYN_INC_L_TSYNINC_L_SHIFT 0
2947
-#define I40E_PRTTSYN_INC_L_TSYNINC_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_INC_L_TSYNINC_L_SHIFT)
2948
605
 #define I40E_PRTTSYN_RXTIME_H(_i) (0x00085040 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */
2949
-#define I40E_PRTTSYN_RXTIME_H_MAX_INDEX 3
2950
-#define I40E_PRTTSYN_RXTIME_H_RXTIEM_H_SHIFT 0
2951
-#define I40E_PRTTSYN_RXTIME_H_RXTIEM_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_RXTIME_H_RXTIEM_H_SHIFT)
2952
606
 #define I40E_PRTTSYN_RXTIME_L(_i) (0x000850C0 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */
2953
-#define I40E_PRTTSYN_RXTIME_L_MAX_INDEX 3
2954
-#define I40E_PRTTSYN_RXTIME_L_RXTIEM_L_SHIFT 0
2955
-#define I40E_PRTTSYN_RXTIME_L_RXTIEM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_RXTIME_L_RXTIEM_L_SHIFT)
2956
607
 #define I40E_PRTTSYN_STAT_0 0x001E4220 /* Reset: GLOBR */
2957
-#define I40E_PRTTSYN_STAT_0_EVENT0_SHIFT 0
2958
-#define I40E_PRTTSYN_STAT_0_EVENT0_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_EVENT0_SHIFT)
2959
-#define I40E_PRTTSYN_STAT_0_EVENT1_SHIFT 1
2960
-#define I40E_PRTTSYN_STAT_0_EVENT1_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_EVENT1_SHIFT)
2961
-#define I40E_PRTTSYN_STAT_0_TGT0_SHIFT 2
2962
-#define I40E_PRTTSYN_STAT_0_TGT0_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TGT0_SHIFT)
2963
-#define I40E_PRTTSYN_STAT_0_TGT1_SHIFT 3
2964
-#define I40E_PRTTSYN_STAT_0_TGT1_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TGT1_SHIFT)
2965
608
 #define I40E_PRTTSYN_STAT_0_TXTIME_SHIFT 4
2966
609
 #define I40E_PRTTSYN_STAT_0_TXTIME_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TXTIME_SHIFT)
2967
610
 #define I40E_PRTTSYN_STAT_1 0x00085140 /* Reset: CORER */
2968
-#define I40E_PRTTSYN_STAT_1_RXT0_SHIFT 0
2969
-#define I40E_PRTTSYN_STAT_1_RXT0_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT0_SHIFT)
2970
-#define I40E_PRTTSYN_STAT_1_RXT1_SHIFT 1
2971
-#define I40E_PRTTSYN_STAT_1_RXT1_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT1_SHIFT)
2972
-#define I40E_PRTTSYN_STAT_1_RXT2_SHIFT 2
2973
-#define I40E_PRTTSYN_STAT_1_RXT2_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT2_SHIFT)
2974
-#define I40E_PRTTSYN_STAT_1_RXT3_SHIFT 3
2975
-#define I40E_PRTTSYN_STAT_1_RXT3_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT3_SHIFT)
2976
-#define I40E_PRTTSYN_TGT_H(_i) (0x001E4180 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
2977
-#define I40E_PRTTSYN_TGT_H_MAX_INDEX 1
2978
-#define I40E_PRTTSYN_TGT_H_TSYNTGTT_H_SHIFT 0
2979
-#define I40E_PRTTSYN_TGT_H_TSYNTGTT_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TGT_H_TSYNTGTT_H_SHIFT)
2980
-#define I40E_PRTTSYN_TGT_L(_i) (0x001E4140 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */
2981
-#define I40E_PRTTSYN_TGT_L_MAX_INDEX 1
2982
-#define I40E_PRTTSYN_TGT_L_TSYNTGTT_L_SHIFT 0
2983
-#define I40E_PRTTSYN_TGT_L_TSYNTGTT_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TGT_L_TSYNTGTT_L_SHIFT)
2984
611
 #define I40E_PRTTSYN_TIME_H 0x001E4120 /* Reset: GLOBR */
2985
-#define I40E_PRTTSYN_TIME_H_TSYNTIME_H_SHIFT 0
2986
-#define I40E_PRTTSYN_TIME_H_TSYNTIME_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TIME_H_TSYNTIME_H_SHIFT)
2987
612
 #define I40E_PRTTSYN_TIME_L 0x001E4100 /* Reset: GLOBR */
2988
-#define I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT 0
2989
-#define I40E_PRTTSYN_TIME_L_TSYNTIME_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT)
2990
613
 #define I40E_PRTTSYN_TXTIME_H 0x001E41E0 /* Reset: GLOBR */
2991
-#define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT 0
2992
-#define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT)
2993
614
 #define I40E_PRTTSYN_TXTIME_L 0x001E41C0 /* Reset: GLOBR */
2994
-#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT 0
2995
-#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT)
2996
615
 #define I40E_GL_MDET_RX 0x0012A510 /* Reset: CORER */
2997
616
 #define I40E_GL_MDET_RX_FUNCTION_SHIFT 0
2998
617
 #define I40E_GL_MDET_RX_FUNCTION_MASK I40E_MASK(0xFF, I40E_GL_MDET_RX_FUNCTION_SHIFT)
..
..
@@ -3025,2306 +644,55 @@
3025
644
 #define I40E_PF_VT_PFALLOC_LASTVF_SHIFT 8
3026
645
 #define I40E_PF_VT_PFALLOC_LASTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_LASTVF_SHIFT)
3027
646
 #define I40E_PF_VT_PFALLOC_VALID_SHIFT 31
3028
-#define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1, I40E_PF_VT_PFALLOC_VALID_SHIFT)
647
+#define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PF_VT_PFALLOC_VALID_SHIFT)
3029
648
 #define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
3030
-#define I40E_VP_MDET_RX_MAX_INDEX 127
3031
649
 #define I40E_VP_MDET_RX_VALID_SHIFT 0
3032
650
 #define I40E_VP_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_RX_VALID_SHIFT)
3033
651
 #define I40E_VP_MDET_TX(_VF) (0x000E6000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
3034
-#define I40E_VP_MDET_TX_MAX_INDEX 127
3035
652
 #define I40E_VP_MDET_TX_VALID_SHIFT 0
3036
653
 #define I40E_VP_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_TX_VALID_SHIFT)
3037
-#define I40E_GLPM_WUMC 0x0006C800 /* Reset: POR */
3038
-#define I40E_GLPM_WUMC_NOTCO_SHIFT 0
3039
-#define I40E_GLPM_WUMC_NOTCO_MASK I40E_MASK(0x1, I40E_GLPM_WUMC_NOTCO_SHIFT)
3040
-#define I40E_GLPM_WUMC_SRST_PIN_VAL_SHIFT 1
3041
-#define I40E_GLPM_WUMC_SRST_PIN_VAL_MASK I40E_MASK(0x1, I40E_GLPM_WUMC_SRST_PIN_VAL_SHIFT)
3042
-#define I40E_GLPM_WUMC_ROL_MODE_SHIFT 2
3043
-#define I40E_GLPM_WUMC_ROL_MODE_MASK I40E_MASK(0x1, I40E_GLPM_WUMC_ROL_MODE_SHIFT)
3044
-#define I40E_GLPM_WUMC_RESERVED_4_SHIFT 3
3045
-#define I40E_GLPM_WUMC_RESERVED_4_MASK I40E_MASK(0x1FFF, I40E_GLPM_WUMC_RESERVED_4_SHIFT)
3046
-#define I40E_GLPM_WUMC_MNG_WU_PF_SHIFT 16
3047
-#define I40E_GLPM_WUMC_MNG_WU_PF_MASK I40E_MASK(0xFFFF, I40E_GLPM_WUMC_MNG_WU_PF_SHIFT)
3048
654
 #define I40E_PFPM_APM 0x000B8080 /* Reset: POR */
3049
655
 #define I40E_PFPM_APM_APME_SHIFT 0
3050
656
 #define I40E_PFPM_APM_APME_MASK I40E_MASK(0x1, I40E_PFPM_APM_APME_SHIFT)
3051
-#define I40E_PFPM_FHFT_LENGTH(_i) (0x0006A000 + ((_i) * 128)) /* _i=0...7 */ /* Reset: POR */
3052
-#define I40E_PFPM_FHFT_LENGTH_MAX_INDEX 7
3053
-#define I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT 0
3054
-#define I40E_PFPM_FHFT_LENGTH_LENGTH_MASK I40E_MASK(0xFF, I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT)
3055
-#define I40E_PFPM_WUC 0x0006B200 /* Reset: POR */
3056
-#define I40E_PFPM_WUC_EN_APM_D0_SHIFT 5
3057
-#define I40E_PFPM_WUC_EN_APM_D0_MASK I40E_MASK(0x1, I40E_PFPM_WUC_EN_APM_D0_SHIFT)
3058
657
 #define I40E_PFPM_WUFC 0x0006B400 /* Reset: POR */
3059
-#define I40E_PFPM_WUFC_LNKC_SHIFT 0
3060
-#define I40E_PFPM_WUFC_LNKC_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_LNKC_SHIFT)
3061
658
 #define I40E_PFPM_WUFC_MAG_SHIFT 1
3062
659
 #define I40E_PFPM_WUFC_MAG_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_MAG_SHIFT)
3063
-#define I40E_PFPM_WUFC_MNG_SHIFT 3
3064
-#define I40E_PFPM_WUFC_MNG_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_MNG_SHIFT)
3065
-#define I40E_PFPM_WUFC_FLX0_ACT_SHIFT 4
3066
-#define I40E_PFPM_WUFC_FLX0_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX0_ACT_SHIFT)
3067
-#define I40E_PFPM_WUFC_FLX1_ACT_SHIFT 5
3068
-#define I40E_PFPM_WUFC_FLX1_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX1_ACT_SHIFT)
3069
-#define I40E_PFPM_WUFC_FLX2_ACT_SHIFT 6
3070
-#define I40E_PFPM_WUFC_FLX2_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX2_ACT_SHIFT)
3071
-#define I40E_PFPM_WUFC_FLX3_ACT_SHIFT 7
3072
-#define I40E_PFPM_WUFC_FLX3_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX3_ACT_SHIFT)
3073
-#define I40E_PFPM_WUFC_FLX4_ACT_SHIFT 8
3074
-#define I40E_PFPM_WUFC_FLX4_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX4_ACT_SHIFT)
3075
-#define I40E_PFPM_WUFC_FLX5_ACT_SHIFT 9
3076
-#define I40E_PFPM_WUFC_FLX5_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX5_ACT_SHIFT)
3077
-#define I40E_PFPM_WUFC_FLX6_ACT_SHIFT 10
3078
-#define I40E_PFPM_WUFC_FLX6_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX6_ACT_SHIFT)
3079
-#define I40E_PFPM_WUFC_FLX7_ACT_SHIFT 11
3080
-#define I40E_PFPM_WUFC_FLX7_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX7_ACT_SHIFT)
3081
-#define I40E_PFPM_WUFC_FLX0_SHIFT 16
3082
-#define I40E_PFPM_WUFC_FLX0_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX0_SHIFT)
3083
-#define I40E_PFPM_WUFC_FLX1_SHIFT 17
3084
-#define I40E_PFPM_WUFC_FLX1_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX1_SHIFT)
3085
-#define I40E_PFPM_WUFC_FLX2_SHIFT 18
3086
-#define I40E_PFPM_WUFC_FLX2_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX2_SHIFT)
3087
-#define I40E_PFPM_WUFC_FLX3_SHIFT 19
3088
-#define I40E_PFPM_WUFC_FLX3_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX3_SHIFT)
3089
-#define I40E_PFPM_WUFC_FLX4_SHIFT 20
3090
-#define I40E_PFPM_WUFC_FLX4_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX4_SHIFT)
3091
-#define I40E_PFPM_WUFC_FLX5_SHIFT 21
3092
-#define I40E_PFPM_WUFC_FLX5_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX5_SHIFT)
3093
-#define I40E_PFPM_WUFC_FLX6_SHIFT 22
3094
-#define I40E_PFPM_WUFC_FLX6_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX6_SHIFT)
3095
-#define I40E_PFPM_WUFC_FLX7_SHIFT 23
3096
-#define I40E_PFPM_WUFC_FLX7_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX7_SHIFT)
3097
-#define I40E_PFPM_WUFC_FW_RST_WK_SHIFT 31
3098
-#define I40E_PFPM_WUFC_FW_RST_WK_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FW_RST_WK_SHIFT)
3099
-#define I40E_PFPM_WUS 0x0006B600 /* Reset: POR */
3100
-#define I40E_PFPM_WUS_LNKC_SHIFT 0
3101
-#define I40E_PFPM_WUS_LNKC_MASK I40E_MASK(0x1, I40E_PFPM_WUS_LNKC_SHIFT)
3102
-#define I40E_PFPM_WUS_MAG_SHIFT 1
3103
-#define I40E_PFPM_WUS_MAG_MASK I40E_MASK(0x1, I40E_PFPM_WUS_MAG_SHIFT)
3104
-#define I40E_PFPM_WUS_PME_STATUS_SHIFT 2
3105
-#define I40E_PFPM_WUS_PME_STATUS_MASK I40E_MASK(0x1, I40E_PFPM_WUS_PME_STATUS_SHIFT)
3106
-#define I40E_PFPM_WUS_MNG_SHIFT 3
3107
-#define I40E_PFPM_WUS_MNG_MASK I40E_MASK(0x1, I40E_PFPM_WUS_MNG_SHIFT)
3108
-#define I40E_PFPM_WUS_FLX0_SHIFT 16
3109
-#define I40E_PFPM_WUS_FLX0_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX0_SHIFT)
3110
-#define I40E_PFPM_WUS_FLX1_SHIFT 17
3111
-#define I40E_PFPM_WUS_FLX1_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX1_SHIFT)
3112
-#define I40E_PFPM_WUS_FLX2_SHIFT 18
3113
-#define I40E_PFPM_WUS_FLX2_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX2_SHIFT)
3114
-#define I40E_PFPM_WUS_FLX3_SHIFT 19
3115
-#define I40E_PFPM_WUS_FLX3_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX3_SHIFT)
3116
-#define I40E_PFPM_WUS_FLX4_SHIFT 20
3117
-#define I40E_PFPM_WUS_FLX4_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX4_SHIFT)
3118
-#define I40E_PFPM_WUS_FLX5_SHIFT 21
3119
-#define I40E_PFPM_WUS_FLX5_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX5_SHIFT)
3120
-#define I40E_PFPM_WUS_FLX6_SHIFT 22
3121
-#define I40E_PFPM_WUS_FLX6_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX6_SHIFT)
3122
-#define I40E_PFPM_WUS_FLX7_SHIFT 23
3123
-#define I40E_PFPM_WUS_FLX7_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX7_SHIFT)
3124
-#define I40E_PFPM_WUS_FW_RST_WK_SHIFT 31
3125
-#define I40E_PFPM_WUS_FW_RST_WK_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FW_RST_WK_SHIFT)
3126
-#define I40E_PRTPM_FHFHR 0x0006C000 /* Reset: POR */
3127
-#define I40E_PRTPM_FHFHR_UNICAST_SHIFT 0
3128
-#define I40E_PRTPM_FHFHR_UNICAST_MASK I40E_MASK(0x1, I40E_PRTPM_FHFHR_UNICAST_SHIFT)
3129
-#define I40E_PRTPM_FHFHR_MULTICAST_SHIFT 1
3130
-#define I40E_PRTPM_FHFHR_MULTICAST_MASK I40E_MASK(0x1, I40E_PRTPM_FHFHR_MULTICAST_SHIFT)
3131
-#define I40E_PRTPM_SAH(_i) (0x001E44C0 + ((_i) * 32)) /* _i=0...3 */ /* Reset: PFR */
3132
-#define I40E_PRTPM_SAH_MAX_INDEX 3
3133
-#define I40E_PRTPM_SAH_PFPM_SAH_SHIFT 0
3134
-#define I40E_PRTPM_SAH_PFPM_SAH_MASK I40E_MASK(0xFFFF, I40E_PRTPM_SAH_PFPM_SAH_SHIFT)
3135
-#define I40E_PRTPM_SAH_PF_NUM_SHIFT 26
3136
-#define I40E_PRTPM_SAH_PF_NUM_MASK I40E_MASK(0xF, I40E_PRTPM_SAH_PF_NUM_SHIFT)
3137
-#define I40E_PRTPM_SAH_MC_MAG_EN_SHIFT 30
3138
-#define I40E_PRTPM_SAH_MC_MAG_EN_MASK I40E_MASK(0x1, I40E_PRTPM_SAH_MC_MAG_EN_SHIFT)
3139
-#define I40E_PRTPM_SAH_AV_SHIFT 31
3140
-#define I40E_PRTPM_SAH_AV_MASK I40E_MASK(0x1, I40E_PRTPM_SAH_AV_SHIFT)
3141
-#define I40E_PRTPM_SAL(_i) (0x001E4440 + ((_i) * 32)) /* _i=0...3 */ /* Reset: PFR */
3142
-#define I40E_PRTPM_SAL_MAX_INDEX 3
3143
-#define I40E_PRTPM_SAL_PFPM_SAL_SHIFT 0
3144
-#define I40E_PRTPM_SAL_PFPM_SAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_SAL_PFPM_SAL_SHIFT)
3145
660
 #define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */
3146
-#define I40E_VF_ARQBAH1_ARQBAH_SHIFT 0
3147
-#define I40E_VF_ARQBAH1_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH1_ARQBAH_SHIFT)
3148
661
 #define I40E_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */
3149
-#define I40E_VF_ARQBAL1_ARQBAL_SHIFT 0
3150
-#define I40E_VF_ARQBAL1_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAL1_ARQBAL_SHIFT)
3151
662
 #define I40E_VF_ARQH1 0x00007400 /* Reset: EMPR */
3152
-#define I40E_VF_ARQH1_ARQH_SHIFT 0
3153
-#define I40E_VF_ARQH1_ARQH_MASK I40E_MASK(0x3FF, I40E_VF_ARQH1_ARQH_SHIFT)
3154
663
 #define I40E_VF_ARQLEN1 0x00008000 /* Reset: EMPR */
3155
-#define I40E_VF_ARQLEN1_ARQLEN_SHIFT 0
3156
-#define I40E_VF_ARQLEN1_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN1_ARQLEN_SHIFT)
3157
-#define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28
3158
-#define I40E_VF_ARQLEN1_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQVFE_SHIFT)
3159
-#define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29
3160
-#define I40E_VF_ARQLEN1_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQOVFL_SHIFT)
3161
-#define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30
3162
-#define I40E_VF_ARQLEN1_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQCRIT_SHIFT)
3163
-#define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31
3164
-#define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQENABLE_SHIFT)
3165
664
 #define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */
3166
-#define I40E_VF_ARQT1_ARQT_SHIFT 0
3167
-#define I40E_VF_ARQT1_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT1_ARQT_SHIFT)
3168
665
 #define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */
3169
-#define I40E_VF_ATQBAH1_ATQBAH_SHIFT 0
3170
-#define I40E_VF_ATQBAH1_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH1_ATQBAH_SHIFT)
3171
666
 #define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */
3172
-#define I40E_VF_ATQBAL1_ATQBAL_SHIFT 0
3173
-#define I40E_VF_ATQBAL1_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL1_ATQBAL_SHIFT)
3174
667
 #define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */
3175
-#define I40E_VF_ATQH1_ATQH_SHIFT 0
3176
-#define I40E_VF_ATQH1_ATQH_MASK I40E_MASK(0x3FF, I40E_VF_ATQH1_ATQH_SHIFT)
3177
668
 #define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */
3178
-#define I40E_VF_ATQLEN1_ATQLEN_SHIFT 0
3179
-#define I40E_VF_ATQLEN1_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN1_ATQLEN_SHIFT)
3180
-#define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28
3181
-#define I40E_VF_ATQLEN1_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQVFE_SHIFT)
3182
-#define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29
3183
-#define I40E_VF_ATQLEN1_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQOVFL_SHIFT)
3184
-#define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30
3185
-#define I40E_VF_ATQLEN1_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQCRIT_SHIFT)
3186
-#define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31
3187
-#define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQENABLE_SHIFT)
3188
669
 #define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */
3189
-#define I40E_VF_ATQT1_ATQT_SHIFT 0
3190
-#define I40E_VF_ATQT1_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT1_ATQT_SHIFT)
3191
-#define I40E_VFGEN_RSTAT 0x00008800 /* Reset: VFR */
3192
-#define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0
3193
-#define I40E_VFGEN_RSTAT_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT_VFR_STATE_SHIFT)
3194
-#define I40E_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */
3195
-#define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0
3196
-#define I40E_VFINT_DYN_CTL01_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_SHIFT)
3197
-#define I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT 1
3198
-#define I40E_VFINT_DYN_CTL01_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT)
3199
-#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT 2
3200
-#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT)
3201
-#define I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3
3202
-#define I40E_VFINT_DYN_CTL01_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT)
3203
-#define I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT 5
3204
-#define I40E_VFINT_DYN_CTL01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT)
3205
-#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT 24
3206
-#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT)
3207
-#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT 25
3208
-#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT)
3209
-#define I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT 31
3210
-#define I40E_VFINT_DYN_CTL01_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT)
3211
-#define I40E_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */
3212
-#define I40E_VFINT_DYN_CTLN1_MAX_INDEX 15
3213
-#define I40E_VFINT_DYN_CTLN1_INTENA_SHIFT 0
3214
-#define I40E_VFINT_DYN_CTLN1_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_SHIFT)
3215
-#define I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT 1
3216
-#define I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT)
3217
-#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2
3218
-#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT)
3219
-#define I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3
3220
-#define I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT)
3221
-#define I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5
3222
-#define I40E_VFINT_DYN_CTLN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT)
3223
-#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24
3224
-#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT)
3225
-#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT 25
3226
-#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT)
3227
-#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT 31
3228
-#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT)
3229
-#define I40E_VFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */
3230
-#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT 25
3231
-#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT)
3232
-#define I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30
3233
-#define I40E_VFINT_ICR0_ENA1_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT)
3234
-#define I40E_VFINT_ICR0_ENA1_RSVD_SHIFT 31
3235
-#define I40E_VFINT_ICR0_ENA1_RSVD_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_RSVD_SHIFT)
3236
-#define I40E_VFINT_ICR01 0x00004800 /* Reset: CORER */
3237
-#define I40E_VFINT_ICR01_INTEVENT_SHIFT 0
3238
-#define I40E_VFINT_ICR01_INTEVENT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_INTEVENT_SHIFT)
3239
-#define I40E_VFINT_ICR01_QUEUE_0_SHIFT 1
3240
-#define I40E_VFINT_ICR01_QUEUE_0_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_0_SHIFT)
3241
-#define I40E_VFINT_ICR01_QUEUE_1_SHIFT 2
3242
-#define I40E_VFINT_ICR01_QUEUE_1_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_1_SHIFT)
3243
-#define I40E_VFINT_ICR01_QUEUE_2_SHIFT 3
3244
-#define I40E_VFINT_ICR01_QUEUE_2_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_2_SHIFT)
3245
-#define I40E_VFINT_ICR01_QUEUE_3_SHIFT 4
3246
-#define I40E_VFINT_ICR01_QUEUE_3_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_3_SHIFT)
3247
-#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT 25
3248
-#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT)
3249
-#define I40E_VFINT_ICR01_ADMINQ_SHIFT 30
3250
-#define I40E_VFINT_ICR01_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_ADMINQ_SHIFT)
3251
-#define I40E_VFINT_ICR01_SWINT_SHIFT 31
3252
-#define I40E_VFINT_ICR01_SWINT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_SWINT_SHIFT)
3253
-#define I40E_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */
3254
-#define I40E_VFINT_ITR01_MAX_INDEX 2
3255
-#define I40E_VFINT_ITR01_INTERVAL_SHIFT 0
3256
-#define I40E_VFINT_ITR01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR01_INTERVAL_SHIFT)
3257
-#define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */
3258
-#define I40E_VFINT_ITRN1_MAX_INDEX 2
3259
-#define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0
3260
-#define I40E_VFINT_ITRN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN1_INTERVAL_SHIFT)
3261
-#define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: CORER */
3262
-#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2
3263
-#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT)
3264
-#define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */
3265
-#define I40E_QRX_TAIL1_MAX_INDEX 15
3266
-#define I40E_QRX_TAIL1_TAIL_SHIFT 0
3267
-#define I40E_QRX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QRX_TAIL1_TAIL_SHIFT)
3268
-#define I40E_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */
3269
-#define I40E_QTX_TAIL1_MAX_INDEX 15
3270
-#define I40E_QTX_TAIL1_TAIL_SHIFT 0
3271
-#define I40E_QTX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QTX_TAIL1_TAIL_SHIFT)
3272
-#define I40E_VFMSIX_PBA 0x00002000 /* Reset: VFLR */
3273
-#define I40E_VFMSIX_PBA_PENBIT_SHIFT 0
3274
-#define I40E_VFMSIX_PBA_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA_PENBIT_SHIFT)
3275
-#define I40E_VFMSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
3276
-#define I40E_VFMSIX_TADD_MAX_INDEX 16
3277
-#define I40E_VFMSIX_TADD_MSIXTADD10_SHIFT 0
3278
-#define I40E_VFMSIX_TADD_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD_MSIXTADD10_SHIFT)
3279
-#define I40E_VFMSIX_TADD_MSIXTADD_SHIFT 2
3280
-#define I40E_VFMSIX_TADD_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD_MSIXTADD_SHIFT)
3281
-#define I40E_VFMSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
3282
-#define I40E_VFMSIX_TMSG_MAX_INDEX 16
3283
-#define I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT 0
3284
-#define I40E_VFMSIX_TMSG_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT)
3285
-#define I40E_VFMSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
3286
-#define I40E_VFMSIX_TUADD_MAX_INDEX 16
3287
-#define I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT 0
3288
-#define I40E_VFMSIX_TUADD_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT)
3289
-#define I40E_VFMSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
3290
-#define I40E_VFMSIX_TVCTRL_MAX_INDEX 16
3291
-#define I40E_VFMSIX_TVCTRL_MASK_SHIFT 0
3292
-#define I40E_VFMSIX_TVCTRL_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL_MASK_SHIFT)
3293
-#define I40E_VFCM_PE_ERRDATA 0x0000DC00 /* Reset: VFR */
3294
-#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0
3295
-#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT)
3296
-#define I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT 4
3297
-#define I40E_VFCM_PE_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT)
3298
-#define I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT 8
3299
-#define I40E_VFCM_PE_ERRDATA_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT)
3300
-#define I40E_VFCM_PE_ERRINFO 0x0000D800 /* Reset: VFR */
3301
-#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0
3302
-#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1, I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT)
3303
-#define I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT 4
3304
-#define I40E_VFCM_PE_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT)
3305
-#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8
3306
-#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT)
3307
-#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16
3308
-#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT)
3309
-#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24
3310
-#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT)
3311
-#define I40E_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
3312
-#define I40E_VFQF_HENA_MAX_INDEX 1
3313
-#define I40E_VFQF_HENA_PTYPE_ENA_SHIFT 0
3314
-#define I40E_VFQF_HENA_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_VFQF_HENA_PTYPE_ENA_SHIFT)
3315
-#define I40E_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */
3316
-#define I40E_VFQF_HKEY_MAX_INDEX 12
3317
-#define I40E_VFQF_HKEY_KEY_0_SHIFT 0
3318
-#define I40E_VFQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_0_SHIFT)
3319
-#define I40E_VFQF_HKEY_KEY_1_SHIFT 8
3320
-#define I40E_VFQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_1_SHIFT)
3321
-#define I40E_VFQF_HKEY_KEY_2_SHIFT 16
3322
-#define I40E_VFQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_2_SHIFT)
3323
-#define I40E_VFQF_HKEY_KEY_3_SHIFT 24
3324
-#define I40E_VFQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_3_SHIFT)
3325
-#define I40E_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3326
670
 #define I40E_VFQF_HLUT_MAX_INDEX 15
3327
-#define I40E_VFQF_HLUT_LUT0_SHIFT 0
3328
-#define I40E_VFQF_HLUT_LUT0_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT0_SHIFT)
3329
-#define I40E_VFQF_HLUT_LUT1_SHIFT 8
3330
-#define I40E_VFQF_HLUT_LUT1_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT1_SHIFT)
3331
-#define I40E_VFQF_HLUT_LUT2_SHIFT 16
3332
-#define I40E_VFQF_HLUT_LUT2_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT2_SHIFT)
3333
-#define I40E_VFQF_HLUT_LUT3_SHIFT 24
3334
-#define I40E_VFQF_HLUT_LUT3_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT3_SHIFT)
3335
-#define I40E_VFQF_HREGION(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
3336
-#define I40E_VFQF_HREGION_MAX_INDEX 7
3337
-#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0
3338
-#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT)
3339
-#define I40E_VFQF_HREGION_REGION_0_SHIFT 1
3340
-#define I40E_VFQF_HREGION_REGION_0_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_0_SHIFT)
3341
-#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4
3342
-#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT)
3343
-#define I40E_VFQF_HREGION_REGION_1_SHIFT 5
3344
-#define I40E_VFQF_HREGION_REGION_1_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_1_SHIFT)
3345
-#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8
3346
-#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT)
3347
-#define I40E_VFQF_HREGION_REGION_2_SHIFT 9
3348
-#define I40E_VFQF_HREGION_REGION_2_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_2_SHIFT)
3349
-#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12
3350
-#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT)
3351
-#define I40E_VFQF_HREGION_REGION_3_SHIFT 13
3352
-#define I40E_VFQF_HREGION_REGION_3_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_3_SHIFT)
3353
-#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16
3354
-#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT)
3355
-#define I40E_VFQF_HREGION_REGION_4_SHIFT 17
3356
-#define I40E_VFQF_HREGION_REGION_4_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_4_SHIFT)
3357
-#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20
3358
-#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT)
3359
-#define I40E_VFQF_HREGION_REGION_5_SHIFT 21
3360
-#define I40E_VFQF_HREGION_REGION_5_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_5_SHIFT)
3361
-#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24
3362
-#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT)
3363
-#define I40E_VFQF_HREGION_REGION_6_SHIFT 25
3364
-#define I40E_VFQF_HREGION_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_6_SHIFT)
3365
-#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28
3366
-#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT)
3367
-#define I40E_VFQF_HREGION_REGION_7_SHIFT 29
3368
-#define I40E_VFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_7_SHIFT)
3369
671
 
3370
-#define I40E_MNGSB_FDCRC 0x000B7050 /* Reset: POR */
3371
-#define I40E_MNGSB_FDCRC_CRC_RES_SHIFT 0
3372
-#define I40E_MNGSB_FDCRC_CRC_RES_MASK I40E_MASK(0xFF, I40E_MNGSB_FDCRC_CRC_RES_SHIFT)
3373
-#define I40E_MNGSB_FDCS 0x000B7040 /* Reset: POR */
3374
-#define I40E_MNGSB_FDCS_CRC_CONT_SHIFT 2
3375
-#define I40E_MNGSB_FDCS_CRC_CONT_MASK I40E_MASK(0x1, I40E_MNGSB_FDCS_CRC_CONT_SHIFT)
3376
-#define I40E_MNGSB_FDCS_CRC_SEED_EN_SHIFT 3
3377
-#define I40E_MNGSB_FDCS_CRC_SEED_EN_MASK I40E_MASK(0x1, I40E_MNGSB_FDCS_CRC_SEED_EN_SHIFT)
3378
-#define I40E_MNGSB_FDCS_CRC_WR_INH_SHIFT 4
3379
-#define I40E_MNGSB_FDCS_CRC_WR_INH_MASK I40E_MASK(0x1, I40E_MNGSB_FDCS_CRC_WR_INH_SHIFT)
3380
-#define I40E_MNGSB_FDCS_CRC_SEED_SHIFT 8
3381
-#define I40E_MNGSB_FDCS_CRC_SEED_MASK I40E_MASK(0xFF, I40E_MNGSB_FDCS_CRC_SEED_SHIFT)
3382
-#define I40E_MNGSB_FDS 0x000B7048 /* Reset: POR */
3383
-#define I40E_MNGSB_FDS_START_BC_SHIFT 0
3384
-#define I40E_MNGSB_FDS_START_BC_MASK I40E_MASK(0xFFF, I40E_MNGSB_FDS_START_BC_SHIFT)
3385
-#define I40E_MNGSB_FDS_LAST_BC_SHIFT 16
3386
-#define I40E_MNGSB_FDS_LAST_BC_MASK I40E_MASK(0xFFF, I40E_MNGSB_FDS_LAST_BC_SHIFT)
3387
672
 
3388
-#define I40E_GL_VF_CTRL_RX(_VF) (0x00083600 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
3389
-#define I40E_GL_VF_CTRL_RX_MAX_INDEX 127
3390
-#define I40E_GL_VF_CTRL_RX_AQ_RX_EN_SHIFT 0
3391
-#define I40E_GL_VF_CTRL_RX_AQ_RX_EN_MASK I40E_MASK(0x1, I40E_GL_VF_CTRL_RX_AQ_RX_EN_SHIFT)
3392
-#define I40E_GL_VF_CTRL_TX(_VF) (0x00083400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
3393
-#define I40E_GL_VF_CTRL_TX_MAX_INDEX 127
3394
-#define I40E_GL_VF_CTRL_TX_AQ_TX_EN_SHIFT 0
3395
-#define I40E_GL_VF_CTRL_TX_AQ_TX_EN_MASK I40E_MASK(0x1, I40E_GL_VF_CTRL_TX_AQ_TX_EN_SHIFT)
3396
673
 
3397
-#define I40E_GLCM_LAN_CACHESIZE 0x0010C4D8 /* Reset: CORER */
3398
-#define I40E_GLCM_LAN_CACHESIZE_WORD_SIZE_SHIFT 0
3399
-#define I40E_GLCM_LAN_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFFF, I40E_GLCM_LAN_CACHESIZE_WORD_SIZE_SHIFT)
3400
-#define I40E_GLCM_LAN_CACHESIZE_SETS_SHIFT 12
3401
-#define I40E_GLCM_LAN_CACHESIZE_SETS_MASK I40E_MASK(0xF, I40E_GLCM_LAN_CACHESIZE_SETS_SHIFT)
3402
-#define I40E_GLCM_LAN_CACHESIZE_WAYS_SHIFT 16
3403
-#define I40E_GLCM_LAN_CACHESIZE_WAYS_MASK I40E_MASK(0x3FF, I40E_GLCM_LAN_CACHESIZE_WAYS_SHIFT)
3404
-#define I40E_GLCM_PE_CACHESIZE 0x00138FE4 /* Reset: CORER */
3405
-#define I40E_GLCM_PE_CACHESIZE_WORD_SIZE_SHIFT 0
3406
-#define I40E_GLCM_PE_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFFF, I40E_GLCM_PE_CACHESIZE_WORD_SIZE_SHIFT)
3407
-#define I40E_GLCM_PE_CACHESIZE_SETS_SHIFT 12
3408
-#define I40E_GLCM_PE_CACHESIZE_SETS_MASK I40E_MASK(0xF, I40E_GLCM_PE_CACHESIZE_SETS_SHIFT)
3409
-#define I40E_GLCM_PE_CACHESIZE_WAYS_SHIFT 16
3410
-#define I40E_GLCM_PE_CACHESIZE_WAYS_MASK I40E_MASK(0x1FF, I40E_GLCM_PE_CACHESIZE_WAYS_SHIFT)
3411
-#define I40E_PFCM_PE_ERRDATA 0x00138D00 /* Reset: PFR */
3412
-#define I40E_PFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0
3413
-#define I40E_PFCM_PE_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_PFCM_PE_ERRDATA_ERROR_CODE_SHIFT)
3414
-#define I40E_PFCM_PE_ERRDATA_Q_TYPE_SHIFT 4
3415
-#define I40E_PFCM_PE_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_PFCM_PE_ERRDATA_Q_TYPE_SHIFT)
3416
-#define I40E_PFCM_PE_ERRDATA_Q_NUM_SHIFT 8
3417
-#define I40E_PFCM_PE_ERRDATA_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_PFCM_PE_ERRDATA_Q_NUM_SHIFT)
3418
-#define I40E_PFCM_PE_ERRINFO 0x00138C80 /* Reset: PFR */
3419
-#define I40E_PFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0
3420
-#define I40E_PFCM_PE_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1, I40E_PFCM_PE_ERRINFO_ERROR_VALID_SHIFT)
3421
-#define I40E_PFCM_PE_ERRINFO_ERROR_INST_SHIFT 4
3422
-#define I40E_PFCM_PE_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_PFCM_PE_ERRINFO_ERROR_INST_SHIFT)
3423
-#define I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8
3424
-#define I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT)
3425
-#define I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16
3426
-#define I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT)
3427
-#define I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24
3428
-#define I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT)
3429
674
 
3430
-#define I40E_PRTDCB_TFMSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
3431
-#define I40E_PRTDCB_TFMSTC_MAX_INDEX 7
3432
-#define I40E_PRTDCB_TFMSTC_MSTC_SHIFT 0
3433
-#define I40E_PRTDCB_TFMSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TFMSTC_MSTC_SHIFT)
3434
-#define I40E_GL_FWSTS_FWROWD_SHIFT 8
3435
-#define I40E_GL_FWSTS_FWROWD_MASK I40E_MASK(0x1, I40E_GL_FWSTS_FWROWD_SHIFT)
3436
-#define I40E_GLFOC_CACHESIZE 0x000AA0DC /* Reset: CORER */
3437
-#define I40E_GLFOC_CACHESIZE_WORD_SIZE_SHIFT 0
3438
-#define I40E_GLFOC_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFF, I40E_GLFOC_CACHESIZE_WORD_SIZE_SHIFT)
3439
-#define I40E_GLFOC_CACHESIZE_SETS_SHIFT 8
3440
-#define I40E_GLFOC_CACHESIZE_SETS_MASK I40E_MASK(0xFFF, I40E_GLFOC_CACHESIZE_SETS_SHIFT)
3441
-#define I40E_GLFOC_CACHESIZE_WAYS_SHIFT 20
3442
-#define I40E_GLFOC_CACHESIZE_WAYS_MASK I40E_MASK(0xF, I40E_GLFOC_CACHESIZE_WAYS_SHIFT)
3443
-#define I40E_GLHMC_APBVTINUSEBASE(_i) (0x000C4a00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3444
-#define I40E_GLHMC_APBVTINUSEBASE_MAX_INDEX 15
3445
-#define I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT 0
3446
-#define I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT)
3447
-#define I40E_GLHMC_CEQPART(_i) (0x001312C0 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3448
-#define I40E_GLHMC_CEQPART_MAX_INDEX 15
3449
-#define I40E_GLHMC_CEQPART_PMCEQBASE_SHIFT 0
3450
-#define I40E_GLHMC_CEQPART_PMCEQBASE_MASK I40E_MASK(0xFF, I40E_GLHMC_CEQPART_PMCEQBASE_SHIFT)
3451
-#define I40E_GLHMC_CEQPART_PMCEQSIZE_SHIFT 16
3452
-#define I40E_GLHMC_CEQPART_PMCEQSIZE_MASK I40E_MASK(0x1FF, I40E_GLHMC_CEQPART_PMCEQSIZE_SHIFT)
3453
-#define I40E_GLHMC_DBCQMAX 0x000C20F0 /* Reset: CORER */
3454
-#define I40E_GLHMC_DBCQMAX_GLHMC_DBCQMAX_SHIFT 0
3455
-#define I40E_GLHMC_DBCQMAX_GLHMC_DBCQMAX_MASK I40E_MASK(0x3FFFF, I40E_GLHMC_DBCQMAX_GLHMC_DBCQMAX_SHIFT)
3456
-#define I40E_GLHMC_DBCQPART(_i) (0x00131240 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3457
-#define I40E_GLHMC_DBCQPART_MAX_INDEX 15
3458
-#define I40E_GLHMC_DBCQPART_PMDBCQBASE_SHIFT 0
3459
-#define I40E_GLHMC_DBCQPART_PMDBCQBASE_MASK I40E_MASK(0x3FFF, I40E_GLHMC_DBCQPART_PMDBCQBASE_SHIFT)
3460
-#define I40E_GLHMC_DBCQPART_PMDBCQSIZE_SHIFT 16
3461
-#define I40E_GLHMC_DBCQPART_PMDBCQSIZE_MASK I40E_MASK(0x7FFF, I40E_GLHMC_DBCQPART_PMDBCQSIZE_SHIFT)
3462
-#define I40E_GLHMC_DBQPMAX 0x000C20EC /* Reset: CORER */
3463
-#define I40E_GLHMC_DBQPMAX_GLHMC_DBQPMAX_SHIFT 0
3464
-#define I40E_GLHMC_DBQPMAX_GLHMC_DBQPMAX_MASK I40E_MASK(0x7FFFF, I40E_GLHMC_DBQPMAX_GLHMC_DBQPMAX_SHIFT)
3465
-#define I40E_GLHMC_DBQPPART(_i) (0x00138D80 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3466
-#define I40E_GLHMC_DBQPPART_MAX_INDEX 15
3467
-#define I40E_GLHMC_DBQPPART_PMDBQPBASE_SHIFT 0
3468
-#define I40E_GLHMC_DBQPPART_PMDBQPBASE_MASK I40E_MASK(0x3FFF, I40E_GLHMC_DBQPPART_PMDBQPBASE_SHIFT)
3469
-#define I40E_GLHMC_DBQPPART_PMDBQPSIZE_SHIFT 16
3470
-#define I40E_GLHMC_DBQPPART_PMDBQPSIZE_MASK I40E_MASK(0x7FFF, I40E_GLHMC_DBQPPART_PMDBQPSIZE_SHIFT)
3471
-#define I40E_GLHMC_PEARPBASE(_i) (0x000C4800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3472
-#define I40E_GLHMC_PEARPBASE_MAX_INDEX 15
3473
-#define I40E_GLHMC_PEARPBASE_FPMPEARPBASE_SHIFT 0
3474
-#define I40E_GLHMC_PEARPBASE_FPMPEARPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEARPBASE_FPMPEARPBASE_SHIFT)
3475
-#define I40E_GLHMC_PEARPCNT(_i) (0x000C4900 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3476
-#define I40E_GLHMC_PEARPCNT_MAX_INDEX 15
3477
-#define I40E_GLHMC_PEARPCNT_FPMPEARPCNT_SHIFT 0
3478
-#define I40E_GLHMC_PEARPCNT_FPMPEARPCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEARPCNT_FPMPEARPCNT_SHIFT)
3479
-#define I40E_GLHMC_PEARPMAX 0x000C2038 /* Reset: CORER */
3480
-#define I40E_GLHMC_PEARPMAX_PMPEARPMAX_SHIFT 0
3481
-#define I40E_GLHMC_PEARPMAX_PMPEARPMAX_MASK I40E_MASK(0x1FFFF, I40E_GLHMC_PEARPMAX_PMPEARPMAX_SHIFT)
3482
-#define I40E_GLHMC_PEARPOBJSZ 0x000C2034 /* Reset: CORER */
3483
-#define I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_SHIFT 0
3484
-#define I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_MASK I40E_MASK(0x7, I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_SHIFT)
3485
-#define I40E_GLHMC_PECQBASE(_i) (0x000C4200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3486
-#define I40E_GLHMC_PECQBASE_MAX_INDEX 15
3487
-#define I40E_GLHMC_PECQBASE_FPMPECQBASE_SHIFT 0
3488
-#define I40E_GLHMC_PECQBASE_FPMPECQBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PECQBASE_FPMPECQBASE_SHIFT)
3489
-#define I40E_GLHMC_PECQCNT(_i) (0x000C4300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3490
-#define I40E_GLHMC_PECQCNT_MAX_INDEX 15
3491
-#define I40E_GLHMC_PECQCNT_FPMPECQCNT_SHIFT 0
3492
-#define I40E_GLHMC_PECQCNT_FPMPECQCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PECQCNT_FPMPECQCNT_SHIFT)
3493
-#define I40E_GLHMC_PECQOBJSZ 0x000C2020 /* Reset: CORER */
3494
-#define I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_SHIFT 0
3495
-#define I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_SHIFT)
3496
-#define I40E_GLHMC_PEHTCNT(_i) (0x000C4700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3497
-#define I40E_GLHMC_PEHTCNT_MAX_INDEX 15
3498
-#define I40E_GLHMC_PEHTCNT_FPMPEHTCNT_SHIFT 0
3499
-#define I40E_GLHMC_PEHTCNT_FPMPEHTCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEHTCNT_FPMPEHTCNT_SHIFT)
3500
-#define I40E_GLHMC_PEHTEBASE(_i) (0x000C4600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3501
-#define I40E_GLHMC_PEHTEBASE_MAX_INDEX 15
3502
-#define I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_SHIFT 0
3503
-#define I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_SHIFT)
3504
-#define I40E_GLHMC_PEHTEOBJSZ 0x000C202c /* Reset: CORER */
3505
-#define I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_SHIFT 0
3506
-#define I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_SHIFT)
3507
-#define I40E_GLHMC_PEHTMAX 0x000C2030 /* Reset: CORER */
3508
-#define I40E_GLHMC_PEHTMAX_PMPEHTMAX_SHIFT 0
3509
-#define I40E_GLHMC_PEHTMAX_PMPEHTMAX_MASK I40E_MASK(0x1FFFFF, I40E_GLHMC_PEHTMAX_PMPEHTMAX_SHIFT)
3510
-#define I40E_GLHMC_PEMRBASE(_i) (0x000C4c00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3511
-#define I40E_GLHMC_PEMRBASE_MAX_INDEX 15
3512
-#define I40E_GLHMC_PEMRBASE_FPMPEMRBASE_SHIFT 0
3513
-#define I40E_GLHMC_PEMRBASE_FPMPEMRBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEMRBASE_FPMPEMRBASE_SHIFT)
3514
-#define I40E_GLHMC_PEMRCNT(_i) (0x000C4d00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3515
-#define I40E_GLHMC_PEMRCNT_MAX_INDEX 15
3516
-#define I40E_GLHMC_PEMRCNT_FPMPEMRSZ_SHIFT 0
3517
-#define I40E_GLHMC_PEMRCNT_FPMPEMRSZ_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEMRCNT_FPMPEMRSZ_SHIFT)
3518
-#define I40E_GLHMC_PEMRMAX 0x000C2040 /* Reset: CORER */
3519
-#define I40E_GLHMC_PEMRMAX_PMPEMRMAX_SHIFT 0
3520
-#define I40E_GLHMC_PEMRMAX_PMPEMRMAX_MASK I40E_MASK(0x7FFFFF, I40E_GLHMC_PEMRMAX_PMPEMRMAX_SHIFT)
3521
-#define I40E_GLHMC_PEMROBJSZ 0x000C203c /* Reset: CORER */
3522
-#define I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_SHIFT 0
3523
-#define I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_SHIFT)
3524
-#define I40E_GLHMC_PEPBLBASE(_i) (0x000C5800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3525
-#define I40E_GLHMC_PEPBLBASE_MAX_INDEX 15
3526
-#define I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_SHIFT 0
3527
-#define I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_SHIFT)
3528
-#define I40E_GLHMC_PEPBLCNT(_i) (0x000C5900 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3529
-#define I40E_GLHMC_PEPBLCNT_MAX_INDEX 15
3530
-#define I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_SHIFT 0
3531
-#define I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_SHIFT)
3532
-#define I40E_GLHMC_PEPBLMAX 0x000C206c /* Reset: CORER */
3533
-#define I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_SHIFT 0
3534
-#define I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_SHIFT)
3535
-#define I40E_GLHMC_PEPFFIRSTSD 0x000C20E4 /* Reset: CORER */
3536
-#define I40E_GLHMC_PEPFFIRSTSD_GLHMC_PEPFFIRSTSD_SHIFT 0
3537
-#define I40E_GLHMC_PEPFFIRSTSD_GLHMC_PEPFFIRSTSD_MASK I40E_MASK(0xFFF, I40E_GLHMC_PEPFFIRSTSD_GLHMC_PEPFFIRSTSD_SHIFT)
3538
-#define I40E_GLHMC_PEQ1BASE(_i) (0x000C5200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3539
-#define I40E_GLHMC_PEQ1BASE_MAX_INDEX 15
3540
-#define I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_SHIFT 0
3541
-#define I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_SHIFT)
3542
-#define I40E_GLHMC_PEQ1CNT(_i) (0x000C5300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3543
-#define I40E_GLHMC_PEQ1CNT_MAX_INDEX 15
3544
-#define I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_SHIFT 0
3545
-#define I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_SHIFT)
3546
-#define I40E_GLHMC_PEQ1FLBASE(_i) (0x000C5400 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3547
-#define I40E_GLHMC_PEQ1FLBASE_MAX_INDEX 15
3548
-#define I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_SHIFT 0
3549
-#define I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_SHIFT)
3550
-#define I40E_GLHMC_PEQ1FLMAX 0x000C2058 /* Reset: CORER */
3551
-#define I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_SHIFT 0
3552
-#define I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_MASK I40E_MASK(0x3FFFFFF, I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_SHIFT)
3553
-#define I40E_GLHMC_PEQ1MAX 0x000C2054 /* Reset: CORER */
3554
-#define I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_SHIFT 0
3555
-#define I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_MASK I40E_MASK(0x3FFFFFF, I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_SHIFT)
3556
-#define I40E_GLHMC_PEQ1OBJSZ 0x000C2050 /* Reset: CORER */
3557
-#define I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_SHIFT 0
3558
-#define I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_SHIFT)
3559
-#define I40E_GLHMC_PEQPBASE(_i) (0x000C4000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3560
-#define I40E_GLHMC_PEQPBASE_MAX_INDEX 15
3561
-#define I40E_GLHMC_PEQPBASE_FPMPEQPBASE_SHIFT 0
3562
-#define I40E_GLHMC_PEQPBASE_FPMPEQPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEQPBASE_FPMPEQPBASE_SHIFT)
3563
-#define I40E_GLHMC_PEQPCNT(_i) (0x000C4100 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3564
-#define I40E_GLHMC_PEQPCNT_MAX_INDEX 15
3565
-#define I40E_GLHMC_PEQPCNT_FPMPEQPCNT_SHIFT 0
3566
-#define I40E_GLHMC_PEQPCNT_FPMPEQPCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEQPCNT_FPMPEQPCNT_SHIFT)
3567
-#define I40E_GLHMC_PEQPOBJSZ 0x000C201c /* Reset: CORER */
3568
-#define I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_SHIFT 0
3569
-#define I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_SHIFT)
3570
-#define I40E_GLHMC_PESRQBASE(_i) (0x000C4400 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3571
-#define I40E_GLHMC_PESRQBASE_MAX_INDEX 15
3572
-#define I40E_GLHMC_PESRQBASE_FPMPESRQBASE_SHIFT 0
3573
-#define I40E_GLHMC_PESRQBASE_FPMPESRQBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PESRQBASE_FPMPESRQBASE_SHIFT)
3574
-#define I40E_GLHMC_PESRQCNT(_i) (0x000C4500 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3575
-#define I40E_GLHMC_PESRQCNT_MAX_INDEX 15
3576
-#define I40E_GLHMC_PESRQCNT_FPMPESRQCNT_SHIFT 0
3577
-#define I40E_GLHMC_PESRQCNT_FPMPESRQCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PESRQCNT_FPMPESRQCNT_SHIFT)
3578
-#define I40E_GLHMC_PESRQMAX 0x000C2028 /* Reset: CORER */
3579
-#define I40E_GLHMC_PESRQMAX_PMPESRQMAX_SHIFT 0
3580
-#define I40E_GLHMC_PESRQMAX_PMPESRQMAX_MASK I40E_MASK(0xFFFF, I40E_GLHMC_PESRQMAX_PMPESRQMAX_SHIFT)
3581
-#define I40E_GLHMC_PESRQOBJSZ 0x000C2024 /* Reset: CORER */
3582
-#define I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_SHIFT 0
3583
-#define I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_SHIFT)
3584
-#define I40E_GLHMC_PETIMERBASE(_i) (0x000C5A00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3585
-#define I40E_GLHMC_PETIMERBASE_MAX_INDEX 15
3586
-#define I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_SHIFT 0
3587
-#define I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_SHIFT)
3588
-#define I40E_GLHMC_PETIMERCNT(_i) (0x000C5B00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3589
-#define I40E_GLHMC_PETIMERCNT_MAX_INDEX 15
3590
-#define I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_SHIFT 0
3591
-#define I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_SHIFT)
3592
-#define I40E_GLHMC_PETIMERMAX 0x000C2084 /* Reset: CORER */
3593
-#define I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_SHIFT 0
3594
-#define I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_SHIFT)
3595
-#define I40E_GLHMC_PETIMEROBJSZ 0x000C2080 /* Reset: CORER */
3596
-#define I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_SHIFT 0
3597
-#define I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_SHIFT)
3598
-#define I40E_GLHMC_PEXFBASE(_i) (0x000C4e00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3599
-#define I40E_GLHMC_PEXFBASE_MAX_INDEX 15
3600
-#define I40E_GLHMC_PEXFBASE_FPMPEXFBASE_SHIFT 0
3601
-#define I40E_GLHMC_PEXFBASE_FPMPEXFBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEXFBASE_FPMPEXFBASE_SHIFT)
3602
-#define I40E_GLHMC_PEXFCNT(_i) (0x000C4f00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3603
-#define I40E_GLHMC_PEXFCNT_MAX_INDEX 15
3604
-#define I40E_GLHMC_PEXFCNT_FPMPEXFCNT_SHIFT 0
3605
-#define I40E_GLHMC_PEXFCNT_FPMPEXFCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEXFCNT_FPMPEXFCNT_SHIFT)
3606
-#define I40E_GLHMC_PEXFFLBASE(_i) (0x000C5000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3607
-#define I40E_GLHMC_PEXFFLBASE_MAX_INDEX 15
3608
-#define I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_SHIFT 0
3609
-#define I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_SHIFT)
3610
-#define I40E_GLHMC_PEXFFLMAX 0x000C204c /* Reset: CORER */
3611
-#define I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_SHIFT 0
3612
-#define I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_MASK I40E_MASK(0x1FFFFFF, I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_SHIFT)
3613
-#define I40E_GLHMC_PEXFMAX 0x000C2048 /* Reset: CORER */
3614
-#define I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT 0
3615
-#define I40E_GLHMC_PEXFMAX_PMPEXFMAX_MASK I40E_MASK(0x3FFFFFF, I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT)
3616
-#define I40E_GLHMC_PEXFOBJSZ 0x000C2044 /* Reset: CORER */
3617
-#define I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_SHIFT 0
3618
-#define I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_SHIFT)
3619
-#define I40E_GLHMC_PFPESDPART(_i) (0x000C0880 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
3620
-#define I40E_GLHMC_PFPESDPART_MAX_INDEX 15
3621
-#define I40E_GLHMC_PFPESDPART_PMSDBASE_SHIFT 0
3622
-#define I40E_GLHMC_PFPESDPART_PMSDBASE_MASK I40E_MASK(0xFFF, I40E_GLHMC_PFPESDPART_PMSDBASE_SHIFT)
3623
-#define I40E_GLHMC_PFPESDPART_PMSDSIZE_SHIFT 16
3624
-#define I40E_GLHMC_PFPESDPART_PMSDSIZE_MASK I40E_MASK(0x1FFF, I40E_GLHMC_PFPESDPART_PMSDSIZE_SHIFT)
3625
-#define I40E_GLHMC_VFAPBVTINUSEBASE(_i) (0x000Cca00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3626
-#define I40E_GLHMC_VFAPBVTINUSEBASE_MAX_INDEX 31
3627
-#define I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT 0
3628
-#define I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT)
3629
-#define I40E_GLHMC_VFCEQPART(_i) (0x00132240 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3630
-#define I40E_GLHMC_VFCEQPART_MAX_INDEX 31
3631
-#define I40E_GLHMC_VFCEQPART_PMCEQBASE_SHIFT 0
3632
-#define I40E_GLHMC_VFCEQPART_PMCEQBASE_MASK I40E_MASK(0xFF, I40E_GLHMC_VFCEQPART_PMCEQBASE_SHIFT)
3633
-#define I40E_GLHMC_VFCEQPART_PMCEQSIZE_SHIFT 16
3634
-#define I40E_GLHMC_VFCEQPART_PMCEQSIZE_MASK I40E_MASK(0x1FF, I40E_GLHMC_VFCEQPART_PMCEQSIZE_SHIFT)
3635
-#define I40E_GLHMC_VFDBCQPART(_i) (0x00132140 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3636
-#define I40E_GLHMC_VFDBCQPART_MAX_INDEX 31
3637
-#define I40E_GLHMC_VFDBCQPART_PMDBCQBASE_SHIFT 0
3638
-#define I40E_GLHMC_VFDBCQPART_PMDBCQBASE_MASK I40E_MASK(0x3FFF, I40E_GLHMC_VFDBCQPART_PMDBCQBASE_SHIFT)
3639
-#define I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_SHIFT 16
3640
-#define I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_MASK I40E_MASK(0x7FFF, I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_SHIFT)
3641
-#define I40E_GLHMC_VFDBQPPART(_i) (0x00138E00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3642
-#define I40E_GLHMC_VFDBQPPART_MAX_INDEX 31
3643
-#define I40E_GLHMC_VFDBQPPART_PMDBQPBASE_SHIFT 0
3644
-#define I40E_GLHMC_VFDBQPPART_PMDBQPBASE_MASK I40E_MASK(0x3FFF, I40E_GLHMC_VFDBQPPART_PMDBQPBASE_SHIFT)
3645
-#define I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_SHIFT 16
3646
-#define I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_MASK I40E_MASK(0x7FFF, I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_SHIFT)
3647
-#define I40E_GLHMC_VFFSIAVBASE(_i) (0x000Cd600 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3648
-#define I40E_GLHMC_VFFSIAVBASE_MAX_INDEX 31
3649
-#define I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_SHIFT 0
3650
-#define I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_SHIFT)
3651
-#define I40E_GLHMC_VFFSIAVCNT(_i) (0x000Cd700 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3652
-#define I40E_GLHMC_VFFSIAVCNT_MAX_INDEX 31
3653
-#define I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_SHIFT 0
3654
-#define I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_SHIFT)
3655
-#define I40E_GLHMC_VFPDINV(_i) (0x000C8300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3656
-#define I40E_GLHMC_VFPDINV_MAX_INDEX 31
3657
-#define I40E_GLHMC_VFPDINV_PMSDIDX_SHIFT 0
3658
-#define I40E_GLHMC_VFPDINV_PMSDIDX_MASK I40E_MASK(0xFFF, I40E_GLHMC_VFPDINV_PMSDIDX_SHIFT)
3659
-#define I40E_GLHMC_VFPDINV_PMSDPARTSEL_SHIFT 15
3660
-#define I40E_GLHMC_VFPDINV_PMSDPARTSEL_MASK I40E_MASK(0x1, I40E_GLHMC_VFPDINV_PMSDPARTSEL_SHIFT)
3661
-#define I40E_GLHMC_VFPDINV_PMPDIDX_SHIFT 16
3662
-#define I40E_GLHMC_VFPDINV_PMPDIDX_MASK I40E_MASK(0x1FF, I40E_GLHMC_VFPDINV_PMPDIDX_SHIFT)
3663
-#define I40E_GLHMC_VFPEARPBASE(_i) (0x000Cc800 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3664
-#define I40E_GLHMC_VFPEARPBASE_MAX_INDEX 31
3665
-#define I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_SHIFT 0
3666
-#define I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_SHIFT)
3667
-#define I40E_GLHMC_VFPEARPCNT(_i) (0x000Cc900 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3668
-#define I40E_GLHMC_VFPEARPCNT_MAX_INDEX 31
3669
-#define I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_SHIFT 0
3670
-#define I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_SHIFT)
3671
-#define I40E_GLHMC_VFPECQBASE(_i) (0x000Cc200 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3672
-#define I40E_GLHMC_VFPECQBASE_MAX_INDEX 31
3673
-#define I40E_GLHMC_VFPECQBASE_FPMPECQBASE_SHIFT 0
3674
-#define I40E_GLHMC_VFPECQBASE_FPMPECQBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPECQBASE_FPMPECQBASE_SHIFT)
3675
-#define I40E_GLHMC_VFPECQCNT(_i) (0x000Cc300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3676
-#define I40E_GLHMC_VFPECQCNT_MAX_INDEX 31
3677
-#define I40E_GLHMC_VFPECQCNT_FPMPECQCNT_SHIFT 0
3678
-#define I40E_GLHMC_VFPECQCNT_FPMPECQCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPECQCNT_FPMPECQCNT_SHIFT)
3679
-#define I40E_GLHMC_VFPEHTCNT(_i) (0x000Cc700 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3680
-#define I40E_GLHMC_VFPEHTCNT_MAX_INDEX 31
3681
-#define I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_SHIFT 0
3682
-#define I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_SHIFT)
3683
-#define I40E_GLHMC_VFPEHTEBASE(_i) (0x000Cc600 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3684
-#define I40E_GLHMC_VFPEHTEBASE_MAX_INDEX 31
3685
-#define I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_SHIFT 0
3686
-#define I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_SHIFT)
3687
-#define I40E_GLHMC_VFPEMRBASE(_i) (0x000Ccc00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3688
-#define I40E_GLHMC_VFPEMRBASE_MAX_INDEX 31
3689
-#define I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_SHIFT 0
3690
-#define I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_SHIFT)
3691
-#define I40E_GLHMC_VFPEMRCNT(_i) (0x000Ccd00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3692
-#define I40E_GLHMC_VFPEMRCNT_MAX_INDEX 31
3693
-#define I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_SHIFT 0
3694
-#define I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_SHIFT)
3695
-#define I40E_GLHMC_VFPEPBLBASE(_i) (0x000Cd800 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3696
-#define I40E_GLHMC_VFPEPBLBASE_MAX_INDEX 31
3697
-#define I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_SHIFT 0
3698
-#define I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_SHIFT)
3699
-#define I40E_GLHMC_VFPEPBLCNT(_i) (0x000Cd900 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3700
-#define I40E_GLHMC_VFPEPBLCNT_MAX_INDEX 31
3701
-#define I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_SHIFT 0
3702
-#define I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_SHIFT)
3703
-#define I40E_GLHMC_VFPEQ1BASE(_i) (0x000Cd200 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3704
-#define I40E_GLHMC_VFPEQ1BASE_MAX_INDEX 31
3705
-#define I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_SHIFT 0
3706
-#define I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_SHIFT)
3707
-#define I40E_GLHMC_VFPEQ1CNT(_i) (0x000Cd300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3708
-#define I40E_GLHMC_VFPEQ1CNT_MAX_INDEX 31
3709
-#define I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_SHIFT 0
3710
-#define I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_SHIFT)
3711
-#define I40E_GLHMC_VFPEQ1FLBASE(_i) (0x000Cd400 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3712
-#define I40E_GLHMC_VFPEQ1FLBASE_MAX_INDEX 31
3713
-#define I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_SHIFT 0
3714
-#define I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_SHIFT)
3715
-#define I40E_GLHMC_VFPEQPBASE(_i) (0x000Cc000 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3716
-#define I40E_GLHMC_VFPEQPBASE_MAX_INDEX 31
3717
-#define I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_SHIFT 0
3718
-#define I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_SHIFT)
3719
-#define I40E_GLHMC_VFPEQPCNT(_i) (0x000Cc100 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3720
-#define I40E_GLHMC_VFPEQPCNT_MAX_INDEX 31
3721
-#define I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_SHIFT 0
3722
-#define I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_SHIFT)
3723
-#define I40E_GLHMC_VFPESRQBASE(_i) (0x000Cc400 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3724
-#define I40E_GLHMC_VFPESRQBASE_MAX_INDEX 31
3725
-#define I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_SHIFT 0
3726
-#define I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_SHIFT)
3727
-#define I40E_GLHMC_VFPESRQCNT(_i) (0x000Cc500 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3728
-#define I40E_GLHMC_VFPESRQCNT_MAX_INDEX 31
3729
-#define I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_SHIFT 0
3730
-#define I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_SHIFT)
3731
-#define I40E_GLHMC_VFPETIMERBASE(_i) (0x000CDA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3732
-#define I40E_GLHMC_VFPETIMERBASE_MAX_INDEX 31
3733
-#define I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_SHIFT 0
3734
-#define I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_SHIFT)
3735
-#define I40E_GLHMC_VFPETIMERCNT(_i) (0x000CDB00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3736
-#define I40E_GLHMC_VFPETIMERCNT_MAX_INDEX 31
3737
-#define I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_SHIFT 0
3738
-#define I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_SHIFT)
3739
-#define I40E_GLHMC_VFPEXFBASE(_i) (0x000Cce00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3740
-#define I40E_GLHMC_VFPEXFBASE_MAX_INDEX 31
3741
-#define I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_SHIFT 0
3742
-#define I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_SHIFT)
3743
-#define I40E_GLHMC_VFPEXFCNT(_i) (0x000Ccf00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3744
-#define I40E_GLHMC_VFPEXFCNT_MAX_INDEX 31
3745
-#define I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_SHIFT 0
3746
-#define I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_SHIFT)
3747
-#define I40E_GLHMC_VFPEXFFLBASE(_i) (0x000Cd000 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3748
-#define I40E_GLHMC_VFPEXFFLBASE_MAX_INDEX 31
3749
-#define I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_SHIFT 0
3750
-#define I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_SHIFT)
3751
-#define I40E_GLHMC_VFSDPART(_i) (0x000C8800 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
3752
-#define I40E_GLHMC_VFSDPART_MAX_INDEX 31
3753
-#define I40E_GLHMC_VFSDPART_PMSDBASE_SHIFT 0
3754
-#define I40E_GLHMC_VFSDPART_PMSDBASE_MASK I40E_MASK(0xFFF, I40E_GLHMC_VFSDPART_PMSDBASE_SHIFT)
3755
-#define I40E_GLHMC_VFSDPART_PMSDSIZE_SHIFT 16
3756
-#define I40E_GLHMC_VFSDPART_PMSDSIZE_MASK I40E_MASK(0x1FFF, I40E_GLHMC_VFSDPART_PMSDSIZE_SHIFT)
3757
-#define I40E_GLPBLOC_CACHESIZE 0x000A80BC /* Reset: CORER */
3758
-#define I40E_GLPBLOC_CACHESIZE_WORD_SIZE_SHIFT 0
3759
-#define I40E_GLPBLOC_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFF, I40E_GLPBLOC_CACHESIZE_WORD_SIZE_SHIFT)
3760
-#define I40E_GLPBLOC_CACHESIZE_SETS_SHIFT 8
3761
-#define I40E_GLPBLOC_CACHESIZE_SETS_MASK I40E_MASK(0xFFF, I40E_GLPBLOC_CACHESIZE_SETS_SHIFT)
3762
-#define I40E_GLPBLOC_CACHESIZE_WAYS_SHIFT 20
3763
-#define I40E_GLPBLOC_CACHESIZE_WAYS_MASK I40E_MASK(0xF, I40E_GLPBLOC_CACHESIZE_WAYS_SHIFT)
3764
-#define I40E_GLPDOC_CACHESIZE 0x000D0088 /* Reset: CORER */
3765
-#define I40E_GLPDOC_CACHESIZE_WORD_SIZE_SHIFT 0
3766
-#define I40E_GLPDOC_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFF, I40E_GLPDOC_CACHESIZE_WORD_SIZE_SHIFT)
3767
-#define I40E_GLPDOC_CACHESIZE_SETS_SHIFT 8
3768
-#define I40E_GLPDOC_CACHESIZE_SETS_MASK I40E_MASK(0xFFF, I40E_GLPDOC_CACHESIZE_SETS_SHIFT)
3769
-#define I40E_GLPDOC_CACHESIZE_WAYS_SHIFT 20
3770
-#define I40E_GLPDOC_CACHESIZE_WAYS_MASK I40E_MASK(0xF, I40E_GLPDOC_CACHESIZE_WAYS_SHIFT)
3771
-#define I40E_GLPEOC_CACHESIZE 0x000A60E8 /* Reset: CORER */
3772
-#define I40E_GLPEOC_CACHESIZE_WORD_SIZE_SHIFT 0
3773
-#define I40E_GLPEOC_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFF, I40E_GLPEOC_CACHESIZE_WORD_SIZE_SHIFT)
3774
-#define I40E_GLPEOC_CACHESIZE_SETS_SHIFT 8
3775
-#define I40E_GLPEOC_CACHESIZE_SETS_MASK I40E_MASK(0xFFF, I40E_GLPEOC_CACHESIZE_SETS_SHIFT)
3776
-#define I40E_GLPEOC_CACHESIZE_WAYS_SHIFT 20
3777
-#define I40E_GLPEOC_CACHESIZE_WAYS_MASK I40E_MASK(0xF, I40E_GLPEOC_CACHESIZE_WAYS_SHIFT)
3778
-#define I40E_PFHMC_PDINV_PMSDPARTSEL_SHIFT 15
3779
-#define I40E_PFHMC_PDINV_PMSDPARTSEL_MASK I40E_MASK(0x1, I40E_PFHMC_PDINV_PMSDPARTSEL_SHIFT)
3780
-#define I40E_PFHMC_SDCMD_PMSDPARTSEL_SHIFT 15
3781
-#define I40E_PFHMC_SDCMD_PMSDPARTSEL_MASK I40E_MASK(0x1, I40E_PFHMC_SDCMD_PMSDPARTSEL_SHIFT)
3782
-#define I40E_GL_PPRS_SPARE 0x000856E0 /* Reset: CORER */
3783
-#define I40E_GL_PPRS_SPARE_GL_PPRS_SPARE_SHIFT 0
3784
-#define I40E_GL_PPRS_SPARE_GL_PPRS_SPARE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_PPRS_SPARE_GL_PPRS_SPARE_SHIFT)
3785
-#define I40E_GL_TLAN_SPARE 0x000E64E0 /* Reset: CORER */
3786
-#define I40E_GL_TLAN_SPARE_GL_TLAN_SPARE_SHIFT 0
3787
-#define I40E_GL_TLAN_SPARE_GL_TLAN_SPARE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_TLAN_SPARE_GL_TLAN_SPARE_SHIFT)
3788
-#define I40E_GL_TUPM_SPARE 0x000a2230 /* Reset: CORER */
3789
-#define I40E_GL_TUPM_SPARE_GL_TUPM_SPARE_SHIFT 0
3790
-#define I40E_GL_TUPM_SPARE_GL_TUPM_SPARE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_TUPM_SPARE_GL_TUPM_SPARE_SHIFT)
3791
-#define I40E_GLGEN_CAR_DEBUG 0x000B81C0 /* Reset: POR */
3792
-#define I40E_GLGEN_CAR_DEBUG_CAR_UPPER_CORE_CLK_EN_SHIFT 0
3793
-#define I40E_GLGEN_CAR_DEBUG_CAR_UPPER_CORE_CLK_EN_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_UPPER_CORE_CLK_EN_SHIFT)
3794
-#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_HIU_CLK_EN_SHIFT 1
3795
-#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_HIU_CLK_EN_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_HIU_CLK_EN_SHIFT)
3796
-#define I40E_GLGEN_CAR_DEBUG_CAR_PE_CLK_EN_SHIFT 2
3797
-#define I40E_GLGEN_CAR_DEBUG_CAR_PE_CLK_EN_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PE_CLK_EN_SHIFT)
3798
-#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_PRIM_CLK_ACTIVE_SHIFT 3
3799
-#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_PRIM_CLK_ACTIVE_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_PRIM_CLK_ACTIVE_SHIFT)
3800
-#define I40E_GLGEN_CAR_DEBUG_CDC_PE_ACTIVE_SHIFT 4
3801
-#define I40E_GLGEN_CAR_DEBUG_CDC_PE_ACTIVE_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CDC_PE_ACTIVE_SHIFT)
3802
-#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_PRST_RESET_N_SHIFT 5
3803
-#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_PRST_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_PRST_RESET_N_SHIFT)
3804
-#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_SCLR_RESET_N_SHIFT 6
3805
-#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_SCLR_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_SCLR_RESET_N_SHIFT)
3806
-#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IB_RESET_N_SHIFT 7
3807
-#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IB_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IB_RESET_N_SHIFT)
3808
-#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IMIB_RESET_N_SHIFT 8
3809
-#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IMIB_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IMIB_RESET_N_SHIFT)
3810
-#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_EMP_RESET_N_SHIFT 9
3811
-#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_EMP_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_RAW_EMP_RESET_N_SHIFT)
3812
-#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_GLOBAL_RESET_N_SHIFT 10
3813
-#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_GLOBAL_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_RAW_GLOBAL_RESET_N_SHIFT)
3814
-#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_LAN_POWER_GOOD_SHIFT 11
3815
-#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_LAN_POWER_GOOD_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_RAW_LAN_POWER_GOOD_SHIFT)
3816
-#define I40E_GLGEN_CAR_DEBUG_CDC_IOSF_PRIMERY_RST_B_SHIFT 12
3817
-#define I40E_GLGEN_CAR_DEBUG_CDC_IOSF_PRIMERY_RST_B_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CDC_IOSF_PRIMERY_RST_B_SHIFT)
3818
-#define I40E_GLGEN_CAR_DEBUG_GBE_GLOBALRST_B_SHIFT 13
3819
-#define I40E_GLGEN_CAR_DEBUG_GBE_GLOBALRST_B_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_GBE_GLOBALRST_B_SHIFT)
3820
-#define I40E_GLGEN_CAR_DEBUG_FLEEP_AL_GLOBR_DONE_SHIFT 14
3821
-#define I40E_GLGEN_CAR_DEBUG_FLEEP_AL_GLOBR_DONE_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_FLEEP_AL_GLOBR_DONE_SHIFT)
3822
-#define I40E_GLGEN_MISC_SPARE 0x000880E0 /* Reset: POR */
3823
-#define I40E_GLGEN_MISC_SPARE_GLGEN_MISC_SPARE_SHIFT 0
3824
-#define I40E_GLGEN_MISC_SPARE_GLGEN_MISC_SPARE_MASK I40E_MASK(0xFFFFFFFF, I40E_GLGEN_MISC_SPARE_GLGEN_MISC_SPARE_SHIFT)
3825
-#define I40E_GL_UFUSE_SOC 0x000BE550 /* Reset: POR */
3826
-#define I40E_GL_UFUSE_SOC_PORT_MODE_SHIFT 0
3827
-#define I40E_GL_UFUSE_SOC_PORT_MODE_MASK I40E_MASK(0x3, I40E_GL_UFUSE_SOC_PORT_MODE_SHIFT)
3828
-#define I40E_GL_UFUSE_SOC_NIC_ID_SHIFT 2
3829
-#define I40E_GL_UFUSE_SOC_NIC_ID_MASK I40E_MASK(0x1, I40E_GL_UFUSE_SOC_NIC_ID_SHIFT)
3830
-#define I40E_GL_UFUSE_SOC_SPARE_FUSES_SHIFT 3
3831
-#define I40E_GL_UFUSE_SOC_SPARE_FUSES_MASK I40E_MASK(0x1FFF, I40E_GL_UFUSE_SOC_SPARE_FUSES_SHIFT)
3832
675
 #define I40E_PFINT_DYN_CTL0_WB_ON_ITR_SHIFT 30
3833
676
 #define I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_WB_ON_ITR_SHIFT)
3834
677
 #define I40E_PFINT_DYN_CTLN_WB_ON_ITR_SHIFT 30
3835
678
 #define I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_WB_ON_ITR_SHIFT)
3836
-#define I40E_VFINT_DYN_CTL0_WB_ON_ITR_SHIFT 30
3837
-#define I40E_VFINT_DYN_CTL0_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_WB_ON_ITR_SHIFT)
3838
-#define I40E_VFINT_DYN_CTLN_WB_ON_ITR_SHIFT 30
3839
-#define I40E_VFINT_DYN_CTLN_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_WB_ON_ITR_SHIFT)
3840
-#define I40E_VPLAN_QBASE(_VF) (0x00074800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
3841
-#define I40E_VPLAN_QBASE_MAX_INDEX 127
3842
-#define I40E_VPLAN_QBASE_VFFIRSTQ_SHIFT 0
3843
-#define I40E_VPLAN_QBASE_VFFIRSTQ_MASK I40E_MASK(0x7FF, I40E_VPLAN_QBASE_VFFIRSTQ_SHIFT)
3844
-#define I40E_VPLAN_QBASE_VFNUMQ_SHIFT 11
3845
-#define I40E_VPLAN_QBASE_VFNUMQ_MASK I40E_MASK(0xFF, I40E_VPLAN_QBASE_VFNUMQ_SHIFT)
3846
-#define I40E_VPLAN_QBASE_VFQTABLE_ENA_SHIFT 31
3847
-#define I40E_VPLAN_QBASE_VFQTABLE_ENA_MASK I40E_MASK(0x1, I40E_VPLAN_QBASE_VFQTABLE_ENA_SHIFT)
3848
-#define I40E_PRTMAC_LINK_DOWN_COUNTER 0x001E2440 /* Reset: GLOBR */
3849
-#define I40E_PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_SHIFT 0
3850
-#define I40E_PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_SHIFT)
3851
-#define I40E_GLNVM_AL_REQ 0x000B6164 /* Reset: POR */
3852
-#define I40E_GLNVM_AL_REQ_POR_SHIFT 0
3853
-#define I40E_GLNVM_AL_REQ_POR_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_POR_SHIFT)
3854
-#define I40E_GLNVM_AL_REQ_PCIE_IMIB_SHIFT 1
3855
-#define I40E_GLNVM_AL_REQ_PCIE_IMIB_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_PCIE_IMIB_SHIFT)
3856
-#define I40E_GLNVM_AL_REQ_GLOBR_SHIFT 2
3857
-#define I40E_GLNVM_AL_REQ_GLOBR_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_GLOBR_SHIFT)
3858
-#define I40E_GLNVM_AL_REQ_CORER_SHIFT 3
3859
-#define I40E_GLNVM_AL_REQ_CORER_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_CORER_SHIFT)
3860
-#define I40E_GLNVM_AL_REQ_PE_SHIFT 4
3861
-#define I40E_GLNVM_AL_REQ_PE_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_PE_SHIFT)
3862
-#define I40E_GLNVM_AL_REQ_PCIE_IMIB_ASSERT_SHIFT 5
3863
-#define I40E_GLNVM_AL_REQ_PCIE_IMIB_ASSERT_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_PCIE_IMIB_ASSERT_SHIFT)
3864
-#define I40E_GLNVM_ALTIMERS 0x000B6140 /* Reset: POR */
3865
-#define I40E_GLNVM_ALTIMERS_PCI_ALTIMER_SHIFT 0
3866
-#define I40E_GLNVM_ALTIMERS_PCI_ALTIMER_MASK I40E_MASK(0xFFF, I40E_GLNVM_ALTIMERS_PCI_ALTIMER_SHIFT)
3867
-#define I40E_GLNVM_ALTIMERS_GEN_ALTIMER_SHIFT 12
3868
-#define I40E_GLNVM_ALTIMERS_GEN_ALTIMER_MASK I40E_MASK(0xFFFFF, I40E_GLNVM_ALTIMERS_GEN_ALTIMER_SHIFT)
3869
679
 #define I40E_GLNVM_FLA 0x000B6108 /* Reset: POR */
3870
680
 #define I40E_GLNVM_FLA_LOCKED_SHIFT 6
3871
681
 #define I40E_GLNVM_FLA_LOCKED_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_LOCKED_SHIFT)
3872
682
 
3873
683
 #define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */
3874
-#define I40E_GLNVM_ULD_PCIER_DONE_SHIFT 0
3875
-#define I40E_GLNVM_ULD_PCIER_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_PCIER_DONE_SHIFT)
3876
-#define I40E_GLNVM_ULD_PCIER_DONE_1_SHIFT 1
3877
-#define I40E_GLNVM_ULD_PCIER_DONE_1_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_PCIER_DONE_1_SHIFT)
3878
-#define I40E_GLNVM_ULD_CORER_DONE_SHIFT 3
3879
-#define I40E_GLNVM_ULD_CORER_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CORER_DONE_SHIFT)
3880
-#define I40E_GLNVM_ULD_GLOBR_DONE_SHIFT 4
3881
-#define I40E_GLNVM_ULD_GLOBR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_GLOBR_DONE_SHIFT)
3882
-#define I40E_GLNVM_ULD_POR_DONE_SHIFT 5
3883
-#define I40E_GLNVM_ULD_POR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_POR_DONE_SHIFT)
3884
-#define I40E_GLNVM_ULD_POR_DONE_1_SHIFT 8
3885
-#define I40E_GLNVM_ULD_POR_DONE_1_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_POR_DONE_1_SHIFT)
3886
-#define I40E_GLNVM_ULD_PCIER_DONE_2_SHIFT 9
3887
-#define I40E_GLNVM_ULD_PCIER_DONE_2_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_PCIER_DONE_2_SHIFT)
3888
-#define I40E_GLNVM_ULD_PE_DONE_SHIFT 10
3889
-#define I40E_GLNVM_ULD_PE_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_PE_DONE_SHIFT)
3890
-#define I40E_GLNVM_ULT 0x000B6154 /* Reset: POR */
3891
-#define I40E_GLNVM_ULT_CONF_PCIR_AE_SHIFT 0
3892
-#define I40E_GLNVM_ULT_CONF_PCIR_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_PCIR_AE_SHIFT)
3893
-#define I40E_GLNVM_ULT_CONF_PCIRTL_AE_SHIFT 1
3894
-#define I40E_GLNVM_ULT_CONF_PCIRTL_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_PCIRTL_AE_SHIFT)
3895
-#define I40E_GLNVM_ULT_RESERVED_1_SHIFT 2
3896
-#define I40E_GLNVM_ULT_RESERVED_1_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_RESERVED_1_SHIFT)
3897
-#define I40E_GLNVM_ULT_CONF_CORE_AE_SHIFT 3
3898
-#define I40E_GLNVM_ULT_CONF_CORE_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_CORE_AE_SHIFT)
3899
-#define I40E_GLNVM_ULT_CONF_GLOBAL_AE_SHIFT 4
3900
-#define I40E_GLNVM_ULT_CONF_GLOBAL_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_GLOBAL_AE_SHIFT)
3901
-#define I40E_GLNVM_ULT_CONF_POR_AE_SHIFT 5
3902
-#define I40E_GLNVM_ULT_CONF_POR_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_POR_AE_SHIFT)
3903
-#define I40E_GLNVM_ULT_RESERVED_2_SHIFT 6
3904
-#define I40E_GLNVM_ULT_RESERVED_2_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_RESERVED_2_SHIFT)
3905
-#define I40E_GLNVM_ULT_RESERVED_3_SHIFT 7
3906
-#define I40E_GLNVM_ULT_RESERVED_3_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_RESERVED_3_SHIFT)
3907
-#define I40E_GLNVM_ULT_CONF_EMP_AE_SHIFT 8
3908
-#define I40E_GLNVM_ULT_CONF_EMP_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_EMP_AE_SHIFT)
3909
-#define I40E_GLNVM_ULT_CONF_PCIALT_AE_SHIFT 9
3910
-#define I40E_GLNVM_ULT_CONF_PCIALT_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_PCIALT_AE_SHIFT)
3911
-#define I40E_GLNVM_ULT_RESERVED_4_SHIFT 10
3912
-#define I40E_GLNVM_ULT_RESERVED_4_MASK I40E_MASK(0x3FFFFF, I40E_GLNVM_ULT_RESERVED_4_SHIFT)
3913
-#define I40E_MEM_INIT_DONE_STAT 0x000B615C /* Reset: POR */
3914
-#define I40E_MEM_INIT_DONE_STAT_CMLAN_MEM_INIT_DONE_SHIFT 0
3915
-#define I40E_MEM_INIT_DONE_STAT_CMLAN_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_CMLAN_MEM_INIT_DONE_SHIFT)
3916
-#define I40E_MEM_INIT_DONE_STAT_PMAT_MEM_INIT_DONE_SHIFT 1
3917
-#define I40E_MEM_INIT_DONE_STAT_PMAT_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_PMAT_MEM_INIT_DONE_SHIFT)
3918
-#define I40E_MEM_INIT_DONE_STAT_RCU_MEM_INIT_DONE_SHIFT 2
3919
-#define I40E_MEM_INIT_DONE_STAT_RCU_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RCU_MEM_INIT_DONE_SHIFT)
3920
-#define I40E_MEM_INIT_DONE_STAT_TDPU_MEM_INIT_DONE_SHIFT 3
3921
-#define I40E_MEM_INIT_DONE_STAT_TDPU_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TDPU_MEM_INIT_DONE_SHIFT)
3922
-#define I40E_MEM_INIT_DONE_STAT_TLAN_MEM_INIT_DONE_SHIFT 4
3923
-#define I40E_MEM_INIT_DONE_STAT_TLAN_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TLAN_MEM_INIT_DONE_SHIFT)
3924
-#define I40E_MEM_INIT_DONE_STAT_RLAN_MEM_INIT_DONE_SHIFT 5
3925
-#define I40E_MEM_INIT_DONE_STAT_RLAN_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RLAN_MEM_INIT_DONE_SHIFT)
3926
-#define I40E_MEM_INIT_DONE_STAT_RDPU_MEM_INIT_DONE_SHIFT 6
3927
-#define I40E_MEM_INIT_DONE_STAT_RDPU_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RDPU_MEM_INIT_DONE_SHIFT)
3928
-#define I40E_MEM_INIT_DONE_STAT_PPRS_MEM_INIT_DONE_SHIFT 7
3929
-#define I40E_MEM_INIT_DONE_STAT_PPRS_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_PPRS_MEM_INIT_DONE_SHIFT)
3930
-#define I40E_MEM_INIT_DONE_STAT_RPB_MEM_INIT_DONE_SHIFT 8
3931
-#define I40E_MEM_INIT_DONE_STAT_RPB_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RPB_MEM_INIT_DONE_SHIFT)
3932
-#define I40E_MEM_INIT_DONE_STAT_TPB_MEM_INIT_DONE_SHIFT 9
3933
-#define I40E_MEM_INIT_DONE_STAT_TPB_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TPB_MEM_INIT_DONE_SHIFT)
3934
-#define I40E_MEM_INIT_DONE_STAT_FOC_MEM_INIT_DONE_SHIFT 10
3935
-#define I40E_MEM_INIT_DONE_STAT_FOC_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_FOC_MEM_INIT_DONE_SHIFT)
3936
-#define I40E_MEM_INIT_DONE_STAT_TSCD_MEM_INIT_DONE_SHIFT 11
3937
-#define I40E_MEM_INIT_DONE_STAT_TSCD_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TSCD_MEM_INIT_DONE_SHIFT)
3938
-#define I40E_MEM_INIT_DONE_STAT_TCB_MEM_INIT_DONE_SHIFT 12
3939
-#define I40E_MEM_INIT_DONE_STAT_TCB_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TCB_MEM_INIT_DONE_SHIFT)
3940
-#define I40E_MEM_INIT_DONE_STAT_RCB_MEM_INIT_DONE_SHIFT 13
3941
-#define I40E_MEM_INIT_DONE_STAT_RCB_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RCB_MEM_INIT_DONE_SHIFT)
3942
-#define I40E_MEM_INIT_DONE_STAT_WUC_MEM_INIT_DONE_SHIFT 14
3943
-#define I40E_MEM_INIT_DONE_STAT_WUC_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_WUC_MEM_INIT_DONE_SHIFT)
3944
-#define I40E_MEM_INIT_DONE_STAT_STAT_MEM_INIT_DONE_SHIFT 15
3945
-#define I40E_MEM_INIT_DONE_STAT_STAT_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_STAT_MEM_INIT_DONE_SHIFT)
3946
-#define I40E_MEM_INIT_DONE_STAT_ITR_MEM_INIT_DONE_SHIFT 16
3947
-#define I40E_MEM_INIT_DONE_STAT_ITR_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_ITR_MEM_INIT_DONE_SHIFT)
3948
-#define I40E_MNGSB_DADD 0x000B7030 /* Reset: POR */
3949
-#define I40E_MNGSB_DADD_ADDR_SHIFT 0
3950
-#define I40E_MNGSB_DADD_ADDR_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_DADD_ADDR_SHIFT)
3951
-#define I40E_MNGSB_DCNT 0x000B7034 /* Reset: POR */
3952
-#define I40E_MNGSB_DCNT_BYTE_CNT_SHIFT 0
3953
-#define I40E_MNGSB_DCNT_BYTE_CNT_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_DCNT_BYTE_CNT_SHIFT)
3954
-#define I40E_MNGSB_MSGCTL 0x000B7020 /* Reset: POR */
3955
-#define I40E_MNGSB_MSGCTL_HDR_DWS_SHIFT 0
3956
-#define I40E_MNGSB_MSGCTL_HDR_DWS_MASK I40E_MASK(0x3, I40E_MNGSB_MSGCTL_HDR_DWS_SHIFT)
3957
-#define I40E_MNGSB_MSGCTL_EXP_RDW_SHIFT 8
3958
-#define I40E_MNGSB_MSGCTL_EXP_RDW_MASK I40E_MASK(0x1FF, I40E_MNGSB_MSGCTL_EXP_RDW_SHIFT)
3959
-#define I40E_MNGSB_MSGCTL_MSG_MODE_SHIFT 26
3960
-#define I40E_MNGSB_MSGCTL_MSG_MODE_MASK I40E_MASK(0x3, I40E_MNGSB_MSGCTL_MSG_MODE_SHIFT)
3961
-#define I40E_MNGSB_MSGCTL_TOKEN_MODE_SHIFT 28
3962
-#define I40E_MNGSB_MSGCTL_TOKEN_MODE_MASK I40E_MASK(0x3, I40E_MNGSB_MSGCTL_TOKEN_MODE_SHIFT)
3963
-#define I40E_MNGSB_MSGCTL_BARCLR_SHIFT 30
3964
-#define I40E_MNGSB_MSGCTL_BARCLR_MASK I40E_MASK(0x1, I40E_MNGSB_MSGCTL_BARCLR_SHIFT)
3965
-#define I40E_MNGSB_MSGCTL_CMDV_SHIFT 31
3966
-#define I40E_MNGSB_MSGCTL_CMDV_MASK I40E_MASK(0x1, I40E_MNGSB_MSGCTL_CMDV_SHIFT)
3967
-#define I40E_MNGSB_RDATA 0x000B7300 /* Reset: POR */
3968
-#define I40E_MNGSB_RDATA_DATA_SHIFT 0
3969
-#define I40E_MNGSB_RDATA_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_RDATA_DATA_SHIFT)
3970
-#define I40E_MNGSB_RHDR0 0x000B72FC /* Reset: POR */
3971
-#define I40E_MNGSB_RHDR0_DESTINATION_SHIFT 0
3972
-#define I40E_MNGSB_RHDR0_DESTINATION_MASK I40E_MASK(0xFF, I40E_MNGSB_RHDR0_DESTINATION_SHIFT)
3973
-#define I40E_MNGSB_RHDR0_SOURCE_SHIFT 8
3974
-#define I40E_MNGSB_RHDR0_SOURCE_MASK I40E_MASK(0xFF, I40E_MNGSB_RHDR0_SOURCE_SHIFT)
3975
-#define I40E_MNGSB_RHDR0_OPCODE_SHIFT 16
3976
-#define I40E_MNGSB_RHDR0_OPCODE_MASK I40E_MASK(0xFF, I40E_MNGSB_RHDR0_OPCODE_SHIFT)
3977
-#define I40E_MNGSB_RHDR0_TAG_SHIFT 24
3978
-#define I40E_MNGSB_RHDR0_TAG_MASK I40E_MASK(0x7, I40E_MNGSB_RHDR0_TAG_SHIFT)
3979
-#define I40E_MNGSB_RHDR0_RESPONSE_SHIFT 27
3980
-#define I40E_MNGSB_RHDR0_RESPONSE_MASK I40E_MASK(0x7, I40E_MNGSB_RHDR0_RESPONSE_SHIFT)
3981
-#define I40E_MNGSB_RHDR0_EH_SHIFT 31
3982
-#define I40E_MNGSB_RHDR0_EH_MASK I40E_MASK(0x1, I40E_MNGSB_RHDR0_EH_SHIFT)
3983
-#define I40E_MNGSB_RSPCTL 0x000B7024 /* Reset: POR */
3984
-#define I40E_MNGSB_RSPCTL_DMA_MSG_DWORDS_SHIFT 0
3985
-#define I40E_MNGSB_RSPCTL_DMA_MSG_DWORDS_MASK I40E_MASK(0x1FF, I40E_MNGSB_RSPCTL_DMA_MSG_DWORDS_SHIFT)
3986
-#define I40E_MNGSB_RSPCTL_RSP_MODE_SHIFT 26
3987
-#define I40E_MNGSB_RSPCTL_RSP_MODE_MASK I40E_MASK(0x3, I40E_MNGSB_RSPCTL_RSP_MODE_SHIFT)
3988
-#define I40E_MNGSB_RSPCTL_RSP_BAD_LEN_SHIFT 30
3989
-#define I40E_MNGSB_RSPCTL_RSP_BAD_LEN_MASK I40E_MASK(0x1, I40E_MNGSB_RSPCTL_RSP_BAD_LEN_SHIFT)
3990
-#define I40E_MNGSB_RSPCTL_RSP_ERR_SHIFT 31
3991
-#define I40E_MNGSB_RSPCTL_RSP_ERR_MASK I40E_MASK(0x1, I40E_MNGSB_RSPCTL_RSP_ERR_SHIFT)
3992
-#define I40E_MNGSB_WDATA 0x000B7100 /* Reset: POR */
3993
-#define I40E_MNGSB_WDATA_DATA_SHIFT 0
3994
-#define I40E_MNGSB_WDATA_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_WDATA_DATA_SHIFT)
3995
-#define I40E_MNGSB_WHDR0 0x000B70F4 /* Reset: POR */
3996
-#define I40E_MNGSB_WHDR0_RAW_DEST_SHIFT 0
3997
-#define I40E_MNGSB_WHDR0_RAW_DEST_MASK I40E_MASK(0xFF, I40E_MNGSB_WHDR0_RAW_DEST_SHIFT)
3998
-#define I40E_MNGSB_WHDR0_DEST_SEL_SHIFT 12
3999
-#define I40E_MNGSB_WHDR0_DEST_SEL_MASK I40E_MASK(0xF, I40E_MNGSB_WHDR0_DEST_SEL_SHIFT)
4000
-#define I40E_MNGSB_WHDR0_OPCODE_SEL_SHIFT 16
4001
-#define I40E_MNGSB_WHDR0_OPCODE_SEL_MASK I40E_MASK(0xFF, I40E_MNGSB_WHDR0_OPCODE_SEL_SHIFT)
4002
-#define I40E_MNGSB_WHDR0_TAG_SHIFT 24
4003
-#define I40E_MNGSB_WHDR0_TAG_MASK I40E_MASK(0x7F, I40E_MNGSB_WHDR0_TAG_SHIFT)
4004
-#define I40E_MNGSB_WHDR1 0x000B70F8 /* Reset: POR */
4005
-#define I40E_MNGSB_WHDR1_ADDR_SHIFT 0
4006
-#define I40E_MNGSB_WHDR1_ADDR_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_WHDR1_ADDR_SHIFT)
4007
-#define I40E_MNGSB_WHDR2 0x000B70FC /* Reset: POR */
4008
-#define I40E_MNGSB_WHDR2_LENGTH_SHIFT 0
4009
-#define I40E_MNGSB_WHDR2_LENGTH_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_WHDR2_LENGTH_SHIFT)
4010
684
 
4011
-#define I40E_GLPCI_CAPSUP_WAKUP_EN_SHIFT 21
4012
-#define I40E_GLPCI_CAPSUP_WAKUP_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_WAKUP_EN_SHIFT)
4013
685
 
4014
-#define I40E_GLPCI_CUR_CLNT_COMMON 0x0009CA18 /* Reset: PCIR */
4015
-#define I40E_GLPCI_CUR_CLNT_COMMON_DATA_LINES_SHIFT 0
4016
-#define I40E_GLPCI_CUR_CLNT_COMMON_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_CLNT_COMMON_DATA_LINES_SHIFT)
4017
-#define I40E_GLPCI_CUR_CLNT_COMMON_OSR_SHIFT 16
4018
-#define I40E_GLPCI_CUR_CLNT_COMMON_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_CLNT_COMMON_OSR_SHIFT)
4019
-#define I40E_GLPCI_CUR_CLNT_PIPEMON 0x0009CA20 /* Reset: PCIR */
4020
-#define I40E_GLPCI_CUR_CLNT_PIPEMON_DATA_LINES_SHIFT 0
4021
-#define I40E_GLPCI_CUR_CLNT_PIPEMON_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_CLNT_PIPEMON_DATA_LINES_SHIFT)
4022
-#define I40E_GLPCI_CUR_MNG_ALWD 0x0009c514 /* Reset: PCIR */
4023
-#define I40E_GLPCI_CUR_MNG_ALWD_DATA_LINES_SHIFT 0
4024
-#define I40E_GLPCI_CUR_MNG_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_ALWD_DATA_LINES_SHIFT)
4025
-#define I40E_GLPCI_CUR_MNG_ALWD_OSR_SHIFT 16
4026
-#define I40E_GLPCI_CUR_MNG_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_ALWD_OSR_SHIFT)
4027
-#define I40E_GLPCI_CUR_MNG_RSVD 0x0009c594 /* Reset: PCIR */
4028
-#define I40E_GLPCI_CUR_MNG_RSVD_DATA_LINES_SHIFT 0
4029
-#define I40E_GLPCI_CUR_MNG_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_RSVD_DATA_LINES_SHIFT)
4030
-#define I40E_GLPCI_CUR_MNG_RSVD_OSR_SHIFT 16
4031
-#define I40E_GLPCI_CUR_MNG_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_RSVD_OSR_SHIFT)
4032
-#define I40E_GLPCI_CUR_PMAT_ALWD 0x0009c510 /* Reset: PCIR */
4033
-#define I40E_GLPCI_CUR_PMAT_ALWD_DATA_LINES_SHIFT 0
4034
-#define I40E_GLPCI_CUR_PMAT_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_ALWD_DATA_LINES_SHIFT)
4035
-#define I40E_GLPCI_CUR_PMAT_ALWD_OSR_SHIFT 16
4036
-#define I40E_GLPCI_CUR_PMAT_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_ALWD_OSR_SHIFT)
4037
-#define I40E_GLPCI_CUR_PMAT_RSVD 0x0009c590 /* Reset: PCIR */
4038
-#define I40E_GLPCI_CUR_PMAT_RSVD_DATA_LINES_SHIFT 0
4039
-#define I40E_GLPCI_CUR_PMAT_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_RSVD_DATA_LINES_SHIFT)
4040
-#define I40E_GLPCI_CUR_PMAT_RSVD_OSR_SHIFT 16
4041
-#define I40E_GLPCI_CUR_PMAT_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_RSVD_OSR_SHIFT)
4042
-#define I40E_GLPCI_CUR_RLAN_ALWD 0x0009c500 /* Reset: PCIR */
4043
-#define I40E_GLPCI_CUR_RLAN_ALWD_DATA_LINES_SHIFT 0
4044
-#define I40E_GLPCI_CUR_RLAN_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_ALWD_DATA_LINES_SHIFT)
4045
-#define I40E_GLPCI_CUR_RLAN_ALWD_OSR_SHIFT 16
4046
-#define I40E_GLPCI_CUR_RLAN_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_ALWD_OSR_SHIFT)
4047
-#define I40E_GLPCI_CUR_RLAN_RSVD 0x0009c580 /* Reset: PCIR */
4048
-#define I40E_GLPCI_CUR_RLAN_RSVD_DATA_LINES_SHIFT 0
4049
-#define I40E_GLPCI_CUR_RLAN_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_RSVD_DATA_LINES_SHIFT)
4050
-#define I40E_GLPCI_CUR_RLAN_RSVD_OSR_SHIFT 16
4051
-#define I40E_GLPCI_CUR_RLAN_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_RSVD_OSR_SHIFT)
4052
-#define I40E_GLPCI_CUR_RXPE_ALWD 0x0009c508 /* Reset: PCIR */
4053
-#define I40E_GLPCI_CUR_RXPE_ALWD_DATA_LINES_SHIFT 0
4054
-#define I40E_GLPCI_CUR_RXPE_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_ALWD_DATA_LINES_SHIFT)
4055
-#define I40E_GLPCI_CUR_RXPE_ALWD_OSR_SHIFT 16
4056
-#define I40E_GLPCI_CUR_RXPE_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_ALWD_OSR_SHIFT)
4057
-#define I40E_GLPCI_CUR_RXPE_RSVD 0x0009c588 /* Reset: PCIR */
4058
-#define I40E_GLPCI_CUR_RXPE_RSVD_DATA_LINES_SHIFT 0
4059
-#define I40E_GLPCI_CUR_RXPE_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_RSVD_DATA_LINES_SHIFT)
4060
-#define I40E_GLPCI_CUR_RXPE_RSVD_OSR_SHIFT 16
4061
-#define I40E_GLPCI_CUR_RXPE_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_RSVD_OSR_SHIFT)
4062
-#define I40E_GLPCI_CUR_TDPU_ALWD 0x0009c518 /* Reset: PCIR */
4063
-#define I40E_GLPCI_CUR_TDPU_ALWD_DATA_LINES_SHIFT 0
4064
-#define I40E_GLPCI_CUR_TDPU_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_ALWD_DATA_LINES_SHIFT)
4065
-#define I40E_GLPCI_CUR_TDPU_ALWD_OSR_SHIFT 16
4066
-#define I40E_GLPCI_CUR_TDPU_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_ALWD_OSR_SHIFT)
4067
-#define I40E_GLPCI_CUR_TDPU_RSVD 0x0009c598 /* Reset: PCIR */
4068
-#define I40E_GLPCI_CUR_TDPU_RSVD_DATA_LINES_SHIFT 0
4069
-#define I40E_GLPCI_CUR_TDPU_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_RSVD_DATA_LINES_SHIFT)
4070
-#define I40E_GLPCI_CUR_TDPU_RSVD_OSR_SHIFT 16
4071
-#define I40E_GLPCI_CUR_TDPU_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_RSVD_OSR_SHIFT)
4072
-#define I40E_GLPCI_CUR_TLAN_ALWD 0x0009c504 /* Reset: PCIR */
4073
-#define I40E_GLPCI_CUR_TLAN_ALWD_DATA_LINES_SHIFT 0
4074
-#define I40E_GLPCI_CUR_TLAN_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_ALWD_DATA_LINES_SHIFT)
4075
-#define I40E_GLPCI_CUR_TLAN_ALWD_OSR_SHIFT 16
4076
-#define I40E_GLPCI_CUR_TLAN_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_ALWD_OSR_SHIFT)
4077
-#define I40E_GLPCI_CUR_TLAN_RSVD 0x0009c584 /* Reset: PCIR */
4078
-#define I40E_GLPCI_CUR_TLAN_RSVD_DATA_LINES_SHIFT 0
4079
-#define I40E_GLPCI_CUR_TLAN_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_RSVD_DATA_LINES_SHIFT)
4080
-#define I40E_GLPCI_CUR_TLAN_RSVD_OSR_SHIFT 16
4081
-#define I40E_GLPCI_CUR_TLAN_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_RSVD_OSR_SHIFT)
4082
-#define I40E_GLPCI_CUR_TXPE_ALWD 0x0009c50C /* Reset: PCIR */
4083
-#define I40E_GLPCI_CUR_TXPE_ALWD_DATA_LINES_SHIFT 0
4084
-#define I40E_GLPCI_CUR_TXPE_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_ALWD_DATA_LINES_SHIFT)
4085
-#define I40E_GLPCI_CUR_TXPE_ALWD_OSR_SHIFT 16
4086
-#define I40E_GLPCI_CUR_TXPE_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_ALWD_OSR_SHIFT)
4087
-#define I40E_GLPCI_CUR_TXPE_RSVD 0x0009c58c /* Reset: PCIR */
4088
-#define I40E_GLPCI_CUR_TXPE_RSVD_DATA_LINES_SHIFT 0
4089
-#define I40E_GLPCI_CUR_TXPE_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_RSVD_DATA_LINES_SHIFT)
4090
-#define I40E_GLPCI_CUR_TXPE_RSVD_OSR_SHIFT 16
4091
-#define I40E_GLPCI_CUR_TXPE_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_RSVD_OSR_SHIFT)
4092
-#define I40E_GLPCI_CUR_WATMK_CLNT_COMMON 0x0009CA28 /* Reset: PCIR */
4093
-#define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_DATA_LINES_SHIFT 0
4094
-#define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_WATMK_CLNT_COMMON_DATA_LINES_SHIFT)
4095
-#define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_OSR_SHIFT 16
4096
-#define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_WATMK_CLNT_COMMON_OSR_SHIFT)
4097
686
 
4098
-#define I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT 4
4099
-#define I40E_GLPCI_LBARCTRL_PE_DB_SIZE_MASK I40E_MASK(0x3, I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT)
4100
-#define I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_SHIFT 10
4101
-#define I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_SHIFT)
4102
-#define I40E_GLPCI_NPQ_CFG 0x0009CA00 /* Reset: PCIR */
4103
-#define I40E_GLPCI_NPQ_CFG_EXTEND_TO_SHIFT 0
4104
-#define I40E_GLPCI_NPQ_CFG_EXTEND_TO_MASK I40E_MASK(0x1, I40E_GLPCI_NPQ_CFG_EXTEND_TO_SHIFT)
4105
-#define I40E_GLPCI_NPQ_CFG_SMALL_TO_SHIFT 1
4106
-#define I40E_GLPCI_NPQ_CFG_SMALL_TO_MASK I40E_MASK(0x1, I40E_GLPCI_NPQ_CFG_SMALL_TO_SHIFT)
4107
-#define I40E_GLPCI_NPQ_CFG_WEIGHT_AVG_SHIFT 2
4108
-#define I40E_GLPCI_NPQ_CFG_WEIGHT_AVG_MASK I40E_MASK(0xF, I40E_GLPCI_NPQ_CFG_WEIGHT_AVG_SHIFT)
4109
-#define I40E_GLPCI_NPQ_CFG_NPQ_SPARE_SHIFT 6
4110
-#define I40E_GLPCI_NPQ_CFG_NPQ_SPARE_MASK I40E_MASK(0x3FF, I40E_GLPCI_NPQ_CFG_NPQ_SPARE_SHIFT)
4111
-#define I40E_GLPCI_NPQ_CFG_NPQ_ERR_STAT_SHIFT 16
4112
-#define I40E_GLPCI_NPQ_CFG_NPQ_ERR_STAT_MASK I40E_MASK(0xF, I40E_GLPCI_NPQ_CFG_NPQ_ERR_STAT_SHIFT)
4113
-#define I40E_GLPCI_WATMK_CLNT_PIPEMON 0x0009CA30 /* Reset: PCIR */
4114
-#define I40E_GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_SHIFT 0
4115
-#define I40E_GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_SHIFT)
4116
-#define I40E_GLPCI_WATMK_MNG_ALWD 0x0009CB14 /* Reset: PCIR */
4117
-#define I40E_GLPCI_WATMK_MNG_ALWD_DATA_LINES_SHIFT 0
4118
-#define I40E_GLPCI_WATMK_MNG_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_MNG_ALWD_DATA_LINES_SHIFT)
4119
-#define I40E_GLPCI_WATMK_MNG_ALWD_OSR_SHIFT 16
4120
-#define I40E_GLPCI_WATMK_MNG_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_MNG_ALWD_OSR_SHIFT)
4121
-#define I40E_GLPCI_WATMK_PMAT_ALWD 0x0009CB10 /* Reset: PCIR */
4122
-#define I40E_GLPCI_WATMK_PMAT_ALWD_DATA_LINES_SHIFT 0
4123
-#define I40E_GLPCI_WATMK_PMAT_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_PMAT_ALWD_DATA_LINES_SHIFT)
4124
-#define I40E_GLPCI_WATMK_PMAT_ALWD_OSR_SHIFT 16
4125
-#define I40E_GLPCI_WATMK_PMAT_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_PMAT_ALWD_OSR_SHIFT)
4126
-#define I40E_GLPCI_WATMK_RLAN_ALWD 0x0009CB00 /* Reset: PCIR */
4127
-#define I40E_GLPCI_WATMK_RLAN_ALWD_DATA_LINES_SHIFT 0
4128
-#define I40E_GLPCI_WATMK_RLAN_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RLAN_ALWD_DATA_LINES_SHIFT)
4129
-#define I40E_GLPCI_WATMK_RLAN_ALWD_OSR_SHIFT 16
4130
-#define I40E_GLPCI_WATMK_RLAN_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RLAN_ALWD_OSR_SHIFT)
4131
-#define I40E_GLPCI_WATMK_RXPE_ALWD 0x0009CB08 /* Reset: PCIR */
4132
-#define I40E_GLPCI_WATMK_RXPE_ALWD_DATA_LINES_SHIFT 0
4133
-#define I40E_GLPCI_WATMK_RXPE_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RXPE_ALWD_DATA_LINES_SHIFT)
4134
-#define I40E_GLPCI_WATMK_RXPE_ALWD_OSR_SHIFT 16
4135
-#define I40E_GLPCI_WATMK_RXPE_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RXPE_ALWD_OSR_SHIFT)
4136
-#define I40E_GLPCI_WATMK_TLAN_ALWD 0x0009CB04 /* Reset: PCIR */
4137
-#define I40E_GLPCI_WATMK_TLAN_ALWD_DATA_LINES_SHIFT 0
4138
-#define I40E_GLPCI_WATMK_TLAN_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TLAN_ALWD_DATA_LINES_SHIFT)
4139
-#define I40E_GLPCI_WATMK_TLAN_ALWD_OSR_SHIFT 16
4140
-#define I40E_GLPCI_WATMK_TLAN_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TLAN_ALWD_OSR_SHIFT)
4141
-#define I40E_GLPCI_WATMK_TPDU_ALWD 0x0009CB18 /* Reset: PCIR */
4142
-#define I40E_GLPCI_WATMK_TPDU_ALWD_DATA_LINES_SHIFT 0
4143
-#define I40E_GLPCI_WATMK_TPDU_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TPDU_ALWD_DATA_LINES_SHIFT)
4144
-#define I40E_GLPCI_WATMK_TPDU_ALWD_OSR_SHIFT 16
4145
-#define I40E_GLPCI_WATMK_TPDU_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TPDU_ALWD_OSR_SHIFT)
4146
-#define I40E_GLPCI_WATMK_TXPE_ALWD 0x0009CB0c /* Reset: PCIR */
4147
-#define I40E_GLPCI_WATMK_TXPE_ALWD_DATA_LINES_SHIFT 0
4148
-#define I40E_GLPCI_WATMK_TXPE_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TXPE_ALWD_DATA_LINES_SHIFT)
4149
-#define I40E_GLPCI_WATMK_TXPE_ALWD_OSR_SHIFT 16
4150
-#define I40E_GLPCI_WATMK_TXPE_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TXPE_ALWD_OSR_SHIFT)
4151
-#define I40E_GLPE_CPUSTATUS0 0x0000D040 /* Reset: PE_CORER */
4152
-#define I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_SHIFT 0
4153
-#define I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_SHIFT)
4154
-#define I40E_GLPE_CPUSTATUS1 0x0000D044 /* Reset: PE_CORER */
4155
-#define I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_SHIFT 0
4156
-#define I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_SHIFT)
4157
-#define I40E_GLPE_CPUSTATUS2 0x0000D048 /* Reset: PE_CORER */
4158
-#define I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_SHIFT 0
4159
-#define I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_SHIFT)
4160
-#define I40E_GLPE_CPUTRIG0 0x0000D060 /* Reset: PE_CORER */
4161
-#define I40E_GLPE_CPUTRIG0_PECPUTRIG0_SHIFT 0
4162
-#define I40E_GLPE_CPUTRIG0_PECPUTRIG0_MASK I40E_MASK(0xFFFF, I40E_GLPE_CPUTRIG0_PECPUTRIG0_SHIFT)
4163
-#define I40E_GLPE_CPUTRIG0_TEPREQUEST0_SHIFT 17
4164
-#define I40E_GLPE_CPUTRIG0_TEPREQUEST0_MASK I40E_MASK(0x1, I40E_GLPE_CPUTRIG0_TEPREQUEST0_SHIFT)
4165
-#define I40E_GLPE_CPUTRIG0_OOPREQUEST0_SHIFT 18
4166
-#define I40E_GLPE_CPUTRIG0_OOPREQUEST0_MASK I40E_MASK(0x1, I40E_GLPE_CPUTRIG0_OOPREQUEST0_SHIFT)
4167
-#define I40E_GLPE_DUAL40_RUPM 0x0000DA04 /* Reset: PE_CORER */
4168
-#define I40E_GLPE_DUAL40_RUPM_DUAL_40G_MODE_SHIFT 0
4169
-#define I40E_GLPE_DUAL40_RUPM_DUAL_40G_MODE_MASK I40E_MASK(0x1, I40E_GLPE_DUAL40_RUPM_DUAL_40G_MODE_SHIFT)
4170
-#define I40E_GLPE_PFAEQEDROPCNT(_i) (0x00131440 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
4171
-#define I40E_GLPE_PFAEQEDROPCNT_MAX_INDEX 15
4172
-#define I40E_GLPE_PFAEQEDROPCNT_AEQEDROPCNT_SHIFT 0
4173
-#define I40E_GLPE_PFAEQEDROPCNT_AEQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_PFAEQEDROPCNT_AEQEDROPCNT_SHIFT)
4174
-#define I40E_GLPE_PFCEQEDROPCNT(_i) (0x001313C0 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
4175
-#define I40E_GLPE_PFCEQEDROPCNT_MAX_INDEX 15
4176
-#define I40E_GLPE_PFCEQEDROPCNT_CEQEDROPCNT_SHIFT 0
4177
-#define I40E_GLPE_PFCEQEDROPCNT_CEQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_PFCEQEDROPCNT_CEQEDROPCNT_SHIFT)
4178
-#define I40E_GLPE_PFCQEDROPCNT(_i) (0x00131340 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
4179
-#define I40E_GLPE_PFCQEDROPCNT_MAX_INDEX 15
4180
-#define I40E_GLPE_PFCQEDROPCNT_CQEDROPCNT_SHIFT 0
4181
-#define I40E_GLPE_PFCQEDROPCNT_CQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_PFCQEDROPCNT_CQEDROPCNT_SHIFT)
4182
-#define I40E_GLPE_RUPM_CQPPOOL 0x0000DACC /* Reset: PE_CORER */
4183
-#define I40E_GLPE_RUPM_CQPPOOL_CQPSPADS_SHIFT 0
4184
-#define I40E_GLPE_RUPM_CQPPOOL_CQPSPADS_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_CQPPOOL_CQPSPADS_SHIFT)
4185
-#define I40E_GLPE_RUPM_FLRPOOL 0x0000DAC4 /* Reset: PE_CORER */
4186
-#define I40E_GLPE_RUPM_FLRPOOL_FLRSPADS_SHIFT 0
4187
-#define I40E_GLPE_RUPM_FLRPOOL_FLRSPADS_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_FLRPOOL_FLRSPADS_SHIFT)
4188
-#define I40E_GLPE_RUPM_GCTL 0x0000DA00 /* Reset: PE_CORER */
4189
-#define I40E_GLPE_RUPM_GCTL_ALLOFFTH_SHIFT 0
4190
-#define I40E_GLPE_RUPM_GCTL_ALLOFFTH_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_GCTL_ALLOFFTH_SHIFT)
4191
-#define I40E_GLPE_RUPM_GCTL_RUPM_P0_DIS_SHIFT 26
4192
-#define I40E_GLPE_RUPM_GCTL_RUPM_P0_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_P0_DIS_SHIFT)
4193
-#define I40E_GLPE_RUPM_GCTL_RUPM_P1_DIS_SHIFT 27
4194
-#define I40E_GLPE_RUPM_GCTL_RUPM_P1_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_P1_DIS_SHIFT)
4195
-#define I40E_GLPE_RUPM_GCTL_RUPM_P2_DIS_SHIFT 28
4196
-#define I40E_GLPE_RUPM_GCTL_RUPM_P2_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_P2_DIS_SHIFT)
4197
-#define I40E_GLPE_RUPM_GCTL_RUPM_P3_DIS_SHIFT 29
4198
-#define I40E_GLPE_RUPM_GCTL_RUPM_P3_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_P3_DIS_SHIFT)
4199
-#define I40E_GLPE_RUPM_GCTL_RUPM_DIS_SHIFT 30
4200
-#define I40E_GLPE_RUPM_GCTL_RUPM_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_DIS_SHIFT)
4201
-#define I40E_GLPE_RUPM_GCTL_SWLB_MODE_SHIFT 31
4202
-#define I40E_GLPE_RUPM_GCTL_SWLB_MODE_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_SWLB_MODE_SHIFT)
4203
-#define I40E_GLPE_RUPM_PTXPOOL 0x0000DAC8 /* Reset: PE_CORER */
4204
-#define I40E_GLPE_RUPM_PTXPOOL_PTXSPADS_SHIFT 0
4205
-#define I40E_GLPE_RUPM_PTXPOOL_PTXSPADS_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_PTXPOOL_PTXSPADS_SHIFT)
4206
-#define I40E_GLPE_RUPM_PUSHPOOL 0x0000DAC0 /* Reset: PE_CORER */
4207
-#define I40E_GLPE_RUPM_PUSHPOOL_PUSHSPADS_SHIFT 0
4208
-#define I40E_GLPE_RUPM_PUSHPOOL_PUSHSPADS_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_PUSHPOOL_PUSHSPADS_SHIFT)
4209
-#define I40E_GLPE_RUPM_TXHOST_EN 0x0000DA08 /* Reset: PE_CORER */
4210
-#define I40E_GLPE_RUPM_TXHOST_EN_TXHOST_EN_SHIFT 0
4211
-#define I40E_GLPE_RUPM_TXHOST_EN_TXHOST_EN_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_TXHOST_EN_TXHOST_EN_SHIFT)
4212
-#define I40E_GLPE_VFAEQEDROPCNT(_i) (0x00132540 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
4213
-#define I40E_GLPE_VFAEQEDROPCNT_MAX_INDEX 31
4214
-#define I40E_GLPE_VFAEQEDROPCNT_AEQEDROPCNT_SHIFT 0
4215
-#define I40E_GLPE_VFAEQEDROPCNT_AEQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFAEQEDROPCNT_AEQEDROPCNT_SHIFT)
4216
-#define I40E_GLPE_VFCEQEDROPCNT(_i) (0x00132440 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
4217
-#define I40E_GLPE_VFCEQEDROPCNT_MAX_INDEX 31
4218
-#define I40E_GLPE_VFCEQEDROPCNT_CEQEDROPCNT_SHIFT 0
4219
-#define I40E_GLPE_VFCEQEDROPCNT_CEQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFCEQEDROPCNT_CEQEDROPCNT_SHIFT)
4220
-#define I40E_GLPE_VFCQEDROPCNT(_i) (0x00132340 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
4221
-#define I40E_GLPE_VFCQEDROPCNT_MAX_INDEX 31
4222
-#define I40E_GLPE_VFCQEDROPCNT_CQEDROPCNT_SHIFT 0
4223
-#define I40E_GLPE_VFCQEDROPCNT_CQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFCQEDROPCNT_CQEDROPCNT_SHIFT)
4224
-#define I40E_GLPE_VFFLMOBJCTRL(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */
4225
-#define I40E_GLPE_VFFLMOBJCTRL_MAX_INDEX 31
4226
-#define I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT 0
4227
-#define I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_MASK I40E_MASK(0x7, I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT)
4228
-#define I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT 8
4229
-#define I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_MASK I40E_MASK(0x7, I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT)
4230
-#define I40E_GLPE_VFFLMQ1ALLOCERR(_i) (0x0000C700 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */
4231
-#define I40E_GLPE_VFFLMQ1ALLOCERR_MAX_INDEX 31
4232
-#define I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_SHIFT 0
4233
-#define I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_SHIFT)
4234
-#define I40E_GLPE_VFFLMXMITALLOCERR(_i) (0x0000C600 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */
4235
-#define I40E_GLPE_VFFLMXMITALLOCERR_MAX_INDEX 31
4236
-#define I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_SHIFT 0
4237
-#define I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_SHIFT)
4238
-#define I40E_GLPE_VFUDACTRL(_i) (0x0000C000 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */
4239
-#define I40E_GLPE_VFUDACTRL_MAX_INDEX 31
4240
-#define I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_SHIFT 0
4241
-#define I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_SHIFT)
4242
-#define I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_SHIFT 1
4243
-#define I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_SHIFT)
4244
-#define I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_SHIFT 2
4245
-#define I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_SHIFT)
4246
-#define I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_SHIFT 3
4247
-#define I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_SHIFT)
4248
-#define I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_SHIFT 4
4249
-#define I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_SHIFT)
4250
-#define I40E_GLPE_VFUDAUCFBQPN(_i) (0x0000C100 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */
4251
-#define I40E_GLPE_VFUDAUCFBQPN_MAX_INDEX 31
4252
-#define I40E_GLPE_VFUDAUCFBQPN_QPN_SHIFT 0
4253
-#define I40E_GLPE_VFUDAUCFBQPN_QPN_MASK I40E_MASK(0x3FFFF, I40E_GLPE_VFUDAUCFBQPN_QPN_SHIFT)
4254
-#define I40E_GLPE_VFUDAUCFBQPN_VALID_SHIFT 31
4255
-#define I40E_GLPE_VFUDAUCFBQPN_VALID_MASK I40E_MASK(0x1, I40E_GLPE_VFUDAUCFBQPN_VALID_SHIFT)
4256
-#define I40E_PFPE_AEQALLOC 0x00131180 /* Reset: PFR */
4257
-#define I40E_PFPE_AEQALLOC_AECOUNT_SHIFT 0
4258
-#define I40E_PFPE_AEQALLOC_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPE_AEQALLOC_AECOUNT_SHIFT)
4259
-#define I40E_PFPE_CCQPHIGH 0x00008200 /* Reset: PFR */
4260
-#define I40E_PFPE_CCQPHIGH_PECCQPHIGH_SHIFT 0
4261
-#define I40E_PFPE_CCQPHIGH_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPE_CCQPHIGH_PECCQPHIGH_SHIFT)
4262
-#define I40E_PFPE_CCQPLOW 0x00008180 /* Reset: PFR */
4263
-#define I40E_PFPE_CCQPLOW_PECCQPLOW_SHIFT 0
4264
-#define I40E_PFPE_CCQPLOW_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPE_CCQPLOW_PECCQPLOW_SHIFT)
4265
-#define I40E_PFPE_CCQPSTATUS 0x00008100 /* Reset: PFR */
4266
-#define I40E_PFPE_CCQPSTATUS_CCQP_DONE_SHIFT 0
4267
-#define I40E_PFPE_CCQPSTATUS_CCQP_DONE_MASK I40E_MASK(0x1, I40E_PFPE_CCQPSTATUS_CCQP_DONE_SHIFT)
4268
-#define I40E_PFPE_CCQPSTATUS_HMC_PROFILE_SHIFT 4
4269
-#define I40E_PFPE_CCQPSTATUS_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_PFPE_CCQPSTATUS_HMC_PROFILE_SHIFT)
4270
-#define I40E_PFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT 16
4271
-#define I40E_PFPE_CCQPSTATUS_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_PFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT)
4272
-#define I40E_PFPE_CCQPSTATUS_CCQP_ERR_SHIFT 31
4273
-#define I40E_PFPE_CCQPSTATUS_CCQP_ERR_MASK I40E_MASK(0x1, I40E_PFPE_CCQPSTATUS_CCQP_ERR_SHIFT)
4274
-#define I40E_PFPE_CQACK 0x00131100 /* Reset: PFR */
4275
-#define I40E_PFPE_CQACK_PECQID_SHIFT 0
4276
-#define I40E_PFPE_CQACK_PECQID_MASK I40E_MASK(0x1FFFF, I40E_PFPE_CQACK_PECQID_SHIFT)
4277
-#define I40E_PFPE_CQARM 0x00131080 /* Reset: PFR */
4278
-#define I40E_PFPE_CQARM_PECQID_SHIFT 0
4279
-#define I40E_PFPE_CQARM_PECQID_MASK I40E_MASK(0x1FFFF, I40E_PFPE_CQARM_PECQID_SHIFT)
4280
-#define I40E_PFPE_CQPDB 0x00008000 /* Reset: PFR */
4281
-#define I40E_PFPE_CQPDB_WQHEAD_SHIFT 0
4282
-#define I40E_PFPE_CQPDB_WQHEAD_MASK I40E_MASK(0x7FF, I40E_PFPE_CQPDB_WQHEAD_SHIFT)
4283
-#define I40E_PFPE_CQPERRCODES 0x00008880 /* Reset: PFR */
4284
-#define I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT 0
4285
-#define I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT)
4286
-#define I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT 16
4287
-#define I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFF, I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT)
4288
-#define I40E_PFPE_CQPTAIL 0x00008080 /* Reset: PFR */
4289
-#define I40E_PFPE_CQPTAIL_WQTAIL_SHIFT 0
4290
-#define I40E_PFPE_CQPTAIL_WQTAIL_MASK I40E_MASK(0x7FF, I40E_PFPE_CQPTAIL_WQTAIL_SHIFT)
4291
-#define I40E_PFPE_CQPTAIL_CQP_OP_ERR_SHIFT 31
4292
-#define I40E_PFPE_CQPTAIL_CQP_OP_ERR_MASK I40E_MASK(0x1, I40E_PFPE_CQPTAIL_CQP_OP_ERR_SHIFT)
4293
-#define I40E_PFPE_FLMQ1ALLOCERR 0x00008980 /* Reset: PFR */
4294
-#define I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_SHIFT 0
4295
-#define I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_MASK I40E_MASK(0xFFFF, I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_SHIFT)
4296
-#define I40E_PFPE_FLMXMITALLOCERR 0x00008900 /* Reset: PFR */
4297
-#define I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_SHIFT 0
4298
-#define I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_MASK I40E_MASK(0xFFFF, I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_SHIFT)
4299
-#define I40E_PFPE_IPCONFIG0 0x00008280 /* Reset: PFR */
4300
-#define I40E_PFPE_IPCONFIG0_PEIPID_SHIFT 0
4301
-#define I40E_PFPE_IPCONFIG0_PEIPID_MASK I40E_MASK(0xFFFF, I40E_PFPE_IPCONFIG0_PEIPID_SHIFT)
4302
-#define I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT 16
4303
-#define I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_MASK I40E_MASK(0x1, I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT)
4304
-#define I40E_PFPE_MRTEIDXMASK 0x00008600 /* Reset: PFR */
4305
-#define I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT 0
4306
-#define I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT)
4307
-#define I40E_PFPE_RCVUNEXPECTEDERROR 0x00008680 /* Reset: PFR */
4308
-#define I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT 0
4309
-#define I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT)
4310
-#define I40E_PFPE_TCPNOWTIMER 0x00008580 /* Reset: PFR */
4311
-#define I40E_PFPE_TCPNOWTIMER_TCP_NOW_SHIFT 0
4312
-#define I40E_PFPE_TCPNOWTIMER_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPE_TCPNOWTIMER_TCP_NOW_SHIFT)
4313
-#define I40E_PFPE_UDACTRL 0x00008700 /* Reset: PFR */
4314
-#define I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_SHIFT 0
4315
-#define I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_SHIFT)
4316
-#define I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_SHIFT 1
4317
-#define I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_SHIFT)
4318
-#define I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_SHIFT 2
4319
-#define I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_SHIFT)
4320
-#define I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_SHIFT 3
4321
-#define I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_SHIFT)
4322
-#define I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_SHIFT 4
4323
-#define I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_SHIFT)
4324
-#define I40E_PFPE_UDAUCFBQPN 0x00008780 /* Reset: PFR */
4325
-#define I40E_PFPE_UDAUCFBQPN_QPN_SHIFT 0
4326
-#define I40E_PFPE_UDAUCFBQPN_QPN_MASK I40E_MASK(0x3FFFF, I40E_PFPE_UDAUCFBQPN_QPN_SHIFT)
4327
-#define I40E_PFPE_UDAUCFBQPN_VALID_SHIFT 31
4328
-#define I40E_PFPE_UDAUCFBQPN_VALID_MASK I40E_MASK(0x1, I40E_PFPE_UDAUCFBQPN_VALID_SHIFT)
4329
-#define I40E_PFPE_WQEALLOC 0x00138C00 /* Reset: PFR */
4330
-#define I40E_PFPE_WQEALLOC_PEQPID_SHIFT 0
4331
-#define I40E_PFPE_WQEALLOC_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_PFPE_WQEALLOC_PEQPID_SHIFT)
4332
-#define I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT 20
4333
-#define I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT)
4334
-#define I40E_PRTDCB_RLPMC 0x0001F140 /* Reset: PE_CORER */
4335
-#define I40E_PRTDCB_RLPMC_TC2PFC_SHIFT 0
4336
-#define I40E_PRTDCB_RLPMC_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTDCB_RLPMC_TC2PFC_SHIFT)
4337
-#define I40E_PRTDCB_TCMSTC_RLPM(_i) (0x0001F040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: PE_CORER */
4338
-#define I40E_PRTDCB_TCMSTC_RLPM_MAX_INDEX 7
4339
-#define I40E_PRTDCB_TCMSTC_RLPM_MSTC_SHIFT 0
4340
-#define I40E_PRTDCB_TCMSTC_RLPM_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCMSTC_RLPM_MSTC_SHIFT)
4341
-#define I40E_PRTDCB_TCPMC_RLPM 0x0001F1A0 /* Reset: PE_CORER */
4342
-#define I40E_PRTDCB_TCPMC_RLPM_CPM_SHIFT 0
4343
-#define I40E_PRTDCB_TCPMC_RLPM_CPM_MASK I40E_MASK(0x1FFF, I40E_PRTDCB_TCPMC_RLPM_CPM_SHIFT)
4344
-#define I40E_PRTDCB_TCPMC_RLPM_LLTC_SHIFT 13
4345
-#define I40E_PRTDCB_TCPMC_RLPM_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TCPMC_RLPM_LLTC_SHIFT)
4346
-#define I40E_PRTDCB_TCPMC_RLPM_TCPM_MODE_SHIFT 30
4347
-#define I40E_PRTDCB_TCPMC_RLPM_TCPM_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_TCPMC_RLPM_TCPM_MODE_SHIFT)
4348
-#define I40E_PRTE_RUPM_TCCNTR03 0x0000DAE0 /* Reset: PE_CORER */
4349
-#define I40E_PRTE_RUPM_TCCNTR03_TC0COUNT_SHIFT 0
4350
-#define I40E_PRTE_RUPM_TCCNTR03_TC0COUNT_MASK I40E_MASK(0xFF, I40E_PRTE_RUPM_TCCNTR03_TC0COUNT_SHIFT)
4351
-#define I40E_PRTE_RUPM_TCCNTR03_TC1COUNT_SHIFT 8
4352
-#define I40E_PRTE_RUPM_TCCNTR03_TC1COUNT_MASK I40E_MASK(0xFF, I40E_PRTE_RUPM_TCCNTR03_TC1COUNT_SHIFT)
4353
-#define I40E_PRTE_RUPM_TCCNTR03_TC2COUNT_SHIFT 16
4354
-#define I40E_PRTE_RUPM_TCCNTR03_TC2COUNT_MASK I40E_MASK(0xFF, I40E_PRTE_RUPM_TCCNTR03_TC2COUNT_SHIFT)
4355
-#define I40E_PRTE_RUPM_TCCNTR03_TC3COUNT_SHIFT 24
4356
-#define I40E_PRTE_RUPM_TCCNTR03_TC3COUNT_MASK I40E_MASK(0xFF, I40E_PRTE_RUPM_TCCNTR03_TC3COUNT_SHIFT)
4357
-#define I40E_PRTPE_RUPM_CNTR 0x0000DB20 /* Reset: PE_CORER */
4358
-#define I40E_PRTPE_RUPM_CNTR_COUNT_SHIFT 0
4359
-#define I40E_PRTPE_RUPM_CNTR_COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_CNTR_COUNT_SHIFT)
4360
-#define I40E_PRTPE_RUPM_CTL 0x0000DA40 /* Reset: PE_CORER */
4361
-#define I40E_PRTPE_RUPM_CTL_LLTC_SHIFT 13
4362
-#define I40E_PRTPE_RUPM_CTL_LLTC_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_CTL_LLTC_SHIFT)
4363
-#define I40E_PRTPE_RUPM_CTL_RUPM_MODE_SHIFT 30
4364
-#define I40E_PRTPE_RUPM_CTL_RUPM_MODE_MASK I40E_MASK(0x1, I40E_PRTPE_RUPM_CTL_RUPM_MODE_SHIFT)
4365
-#define I40E_PRTPE_RUPM_PFCCTL 0x0000DA60 /* Reset: PE_CORER */
4366
-#define I40E_PRTPE_RUPM_PFCCTL_TC2PFC_SHIFT 0
4367
-#define I40E_PRTPE_RUPM_PFCCTL_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PFCCTL_TC2PFC_SHIFT)
4368
-#define I40E_PRTPE_RUPM_PFCPC 0x0000DA80 /* Reset: PE_CORER */
4369
-#define I40E_PRTPE_RUPM_PFCPC_PORTOFFTH_SHIFT 0
4370
-#define I40E_PRTPE_RUPM_PFCPC_PORTOFFTH_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PFCPC_PORTOFFTH_SHIFT)
4371
-#define I40E_PRTPE_RUPM_PFCTCC 0x0000DAA0 /* Reset: PE_CORER */
4372
-#define I40E_PRTPE_RUPM_PFCTCC_TCOFFTH_SHIFT 0
4373
-#define I40E_PRTPE_RUPM_PFCTCC_TCOFFTH_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PFCTCC_TCOFFTH_SHIFT)
4374
-#define I40E_PRTPE_RUPM_PFCTCC_LL_PRI_TH_SHIFT 16
4375
-#define I40E_PRTPE_RUPM_PFCTCC_LL_PRI_TH_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PFCTCC_LL_PRI_TH_SHIFT)
4376
-#define I40E_PRTPE_RUPM_PFCTCC_LL_PRI_EN_SHIFT 31
4377
-#define I40E_PRTPE_RUPM_PFCTCC_LL_PRI_EN_MASK I40E_MASK(0x1, I40E_PRTPE_RUPM_PFCTCC_LL_PRI_EN_SHIFT)
4378
-#define I40E_PRTPE_RUPM_PTCTCCNTR47 0x0000DB60 /* Reset: PE_CORER */
4379
-#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC4COUNT_SHIFT 0
4380
-#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC4COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTCTCCNTR47_TC4COUNT_SHIFT)
4381
-#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC5COUNT_SHIFT 8
4382
-#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC5COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTCTCCNTR47_TC5COUNT_SHIFT)
4383
-#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC6COUNT_SHIFT 16
4384
-#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC6COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTCTCCNTR47_TC6COUNT_SHIFT)
4385
-#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC7COUNT_SHIFT 24
4386
-#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC7COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTCTCCNTR47_TC7COUNT_SHIFT)
4387
-#define I40E_PRTPE_RUPM_PTXTCCNTR03 0x0000DB40 /* Reset: PE_CORER */
4388
-#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC0COUNT_SHIFT 0
4389
-#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC0COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTXTCCNTR03_TC0COUNT_SHIFT)
4390
-#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC1COUNT_SHIFT 8
4391
-#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC1COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTXTCCNTR03_TC1COUNT_SHIFT)
4392
-#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC2COUNT_SHIFT 16
4393
-#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC2COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTXTCCNTR03_TC2COUNT_SHIFT)
4394
-#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC3COUNT_SHIFT 24
4395
-#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC3COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTXTCCNTR03_TC3COUNT_SHIFT)
4396
-#define I40E_PRTPE_RUPM_TCCNTR47 0x0000DB00 /* Reset: PE_CORER */
4397
-#define I40E_PRTPE_RUPM_TCCNTR47_TC4COUNT_SHIFT 0
4398
-#define I40E_PRTPE_RUPM_TCCNTR47_TC4COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_TCCNTR47_TC4COUNT_SHIFT)
4399
-#define I40E_PRTPE_RUPM_TCCNTR47_TC5COUNT_SHIFT 8
4400
-#define I40E_PRTPE_RUPM_TCCNTR47_TC5COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_TCCNTR47_TC5COUNT_SHIFT)
4401
-#define I40E_PRTPE_RUPM_TCCNTR47_TC6COUNT_SHIFT 16
4402
-#define I40E_PRTPE_RUPM_TCCNTR47_TC6COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_TCCNTR47_TC6COUNT_SHIFT)
4403
-#define I40E_PRTPE_RUPM_TCCNTR47_TC7COUNT_SHIFT 24
4404
-#define I40E_PRTPE_RUPM_TCCNTR47_TC7COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_TCCNTR47_TC7COUNT_SHIFT)
4405
-#define I40E_PRTPE_RUPM_THRES 0x0000DA20 /* Reset: PE_CORER */
4406
-#define I40E_PRTPE_RUPM_THRES_MINSPADSPERTC_SHIFT 0
4407
-#define I40E_PRTPE_RUPM_THRES_MINSPADSPERTC_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_THRES_MINSPADSPERTC_SHIFT)
4408
-#define I40E_PRTPE_RUPM_THRES_MAXSPADS_SHIFT 8
4409
-#define I40E_PRTPE_RUPM_THRES_MAXSPADS_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_THRES_MAXSPADS_SHIFT)
4410
-#define I40E_PRTPE_RUPM_THRES_MAXSPADSPERTC_SHIFT 16
4411
-#define I40E_PRTPE_RUPM_THRES_MAXSPADSPERTC_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_THRES_MAXSPADSPERTC_SHIFT)
4412
-#define I40E_VFPE_AEQALLOC(_VF) (0x00130C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
4413
-#define I40E_VFPE_AEQALLOC_MAX_INDEX 127
4414
-#define I40E_VFPE_AEQALLOC_AECOUNT_SHIFT 0
4415
-#define I40E_VFPE_AEQALLOC_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_AEQALLOC_AECOUNT_SHIFT)
4416
-#define I40E_VFPE_CCQPHIGH(_VF) (0x00001000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
4417
-#define I40E_VFPE_CCQPHIGH_MAX_INDEX 127
4418
-#define I40E_VFPE_CCQPHIGH_PECCQPHIGH_SHIFT 0
4419
-#define I40E_VFPE_CCQPHIGH_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPHIGH_PECCQPHIGH_SHIFT)
4420
-#define I40E_VFPE_CCQPLOW(_VF) (0x00000C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
4421
-#define I40E_VFPE_CCQPLOW_MAX_INDEX 127
4422
-#define I40E_VFPE_CCQPLOW_PECCQPLOW_SHIFT 0
4423
-#define I40E_VFPE_CCQPLOW_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPLOW_PECCQPLOW_SHIFT)
4424
-#define I40E_VFPE_CCQPSTATUS(_VF) (0x00000800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
4425
-#define I40E_VFPE_CCQPSTATUS_MAX_INDEX 127
4426
-#define I40E_VFPE_CCQPSTATUS_CCQP_DONE_SHIFT 0
4427
-#define I40E_VFPE_CCQPSTATUS_CCQP_DONE_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS_CCQP_DONE_SHIFT)
4428
-#define I40E_VFPE_CCQPSTATUS_HMC_PROFILE_SHIFT 4
4429
-#define I40E_VFPE_CCQPSTATUS_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_VFPE_CCQPSTATUS_HMC_PROFILE_SHIFT)
4430
-#define I40E_VFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT 16
4431
-#define I40E_VFPE_CCQPSTATUS_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_VFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT)
4432
-#define I40E_VFPE_CCQPSTATUS_CCQP_ERR_SHIFT 31
4433
-#define I40E_VFPE_CCQPSTATUS_CCQP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS_CCQP_ERR_SHIFT)
4434
-#define I40E_VFPE_CQACK(_VF) (0x00130800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
4435
-#define I40E_VFPE_CQACK_MAX_INDEX 127
4436
-#define I40E_VFPE_CQACK_PECQID_SHIFT 0
4437
-#define I40E_VFPE_CQACK_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQACK_PECQID_SHIFT)
4438
-#define I40E_VFPE_CQARM(_VF) (0x00130400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
4439
-#define I40E_VFPE_CQARM_MAX_INDEX 127
4440
-#define I40E_VFPE_CQARM_PECQID_SHIFT 0
4441
-#define I40E_VFPE_CQARM_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQARM_PECQID_SHIFT)
4442
-#define I40E_VFPE_CQPDB(_VF) (0x00000000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
4443
-#define I40E_VFPE_CQPDB_MAX_INDEX 127
4444
-#define I40E_VFPE_CQPDB_WQHEAD_SHIFT 0
4445
-#define I40E_VFPE_CQPDB_WQHEAD_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPDB_WQHEAD_SHIFT)
4446
-#define I40E_VFPE_CQPERRCODES(_VF) (0x00001800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
4447
-#define I40E_VFPE_CQPERRCODES_MAX_INDEX 127
4448
-#define I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT 0
4449
-#define I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT)
4450
-#define I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT 16
4451
-#define I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT)
4452
-#define I40E_VFPE_CQPTAIL(_VF) (0x00000400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
4453
-#define I40E_VFPE_CQPTAIL_MAX_INDEX 127
4454
-#define I40E_VFPE_CQPTAIL_WQTAIL_SHIFT 0
4455
-#define I40E_VFPE_CQPTAIL_WQTAIL_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPTAIL_WQTAIL_SHIFT)
4456
-#define I40E_VFPE_CQPTAIL_CQP_OP_ERR_SHIFT 31
4457
-#define I40E_VFPE_CQPTAIL_CQP_OP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CQPTAIL_CQP_OP_ERR_SHIFT)
4458
-#define I40E_VFPE_IPCONFIG0(_VF) (0x00001400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
4459
-#define I40E_VFPE_IPCONFIG0_MAX_INDEX 127
4460
-#define I40E_VFPE_IPCONFIG0_PEIPID_SHIFT 0
4461
-#define I40E_VFPE_IPCONFIG0_PEIPID_MASK I40E_MASK(0xFFFF, I40E_VFPE_IPCONFIG0_PEIPID_SHIFT)
4462
-#define I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT 16
4463
-#define I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_MASK I40E_MASK(0x1, I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT)
4464
-#define I40E_VFPE_MRTEIDXMASK(_VF) (0x00003000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
4465
-#define I40E_VFPE_MRTEIDXMASK_MAX_INDEX 127
4466
-#define I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT 0
4467
-#define I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT)
4468
-#define I40E_VFPE_RCVUNEXPECTEDERROR(_VF) (0x00003400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
4469
-#define I40E_VFPE_RCVUNEXPECTEDERROR_MAX_INDEX 127
4470
-#define I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT 0
4471
-#define I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT)
4472
-#define I40E_VFPE_TCPNOWTIMER(_VF) (0x00002C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
4473
-#define I40E_VFPE_TCPNOWTIMER_MAX_INDEX 127
4474
-#define I40E_VFPE_TCPNOWTIMER_TCP_NOW_SHIFT 0
4475
-#define I40E_VFPE_TCPNOWTIMER_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_TCPNOWTIMER_TCP_NOW_SHIFT)
4476
-#define I40E_VFPE_WQEALLOC(_VF) (0x00138000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
4477
-#define I40E_VFPE_WQEALLOC_MAX_INDEX 127
4478
-#define I40E_VFPE_WQEALLOC_PEQPID_SHIFT 0
4479
-#define I40E_VFPE_WQEALLOC_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_VFPE_WQEALLOC_PEQPID_SHIFT)
4480
-#define I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT 20
4481
-#define I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT)
4482
-#define I40E_GLPES_PFIP4RXDISCARD(_i) (0x00010600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
4483
-#define I40E_GLPES_PFIP4RXDISCARD_MAX_INDEX 15
4484
-#define I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_SHIFT 0
4485
-#define I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_SHIFT)
4486
-#define I40E_GLPES_PFIP4RXFRAGSHI(_i) (0x00010804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4487
-#define I40E_GLPES_PFIP4RXFRAGSHI_MAX_INDEX 15
4488
-#define I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT 0
4489
-#define I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT)
4490
-#define I40E_GLPES_PFIP4RXFRAGSLO(_i) (0x00010800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4491
-#define I40E_GLPES_PFIP4RXFRAGSLO_MAX_INDEX 15
4492
-#define I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT 0
4493
-#define I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT)
4494
-#define I40E_GLPES_PFIP4RXMCOCTSHI(_i) (0x00010A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4495
-#define I40E_GLPES_PFIP4RXMCOCTSHI_MAX_INDEX 15
4496
-#define I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT 0
4497
-#define I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT)
4498
-#define I40E_GLPES_PFIP4RXMCOCTSLO(_i) (0x00010A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4499
-#define I40E_GLPES_PFIP4RXMCOCTSLO_MAX_INDEX 15
4500
-#define I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT 0
4501
-#define I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT)
4502
-#define I40E_GLPES_PFIP4RXMCPKTSHI(_i) (0x00010C04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4503
-#define I40E_GLPES_PFIP4RXMCPKTSHI_MAX_INDEX 15
4504
-#define I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT 0
4505
-#define I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT)
4506
-#define I40E_GLPES_PFIP4RXMCPKTSLO(_i) (0x00010C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4507
-#define I40E_GLPES_PFIP4RXMCPKTSLO_MAX_INDEX 15
4508
-#define I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT 0
4509
-#define I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT)
4510
-#define I40E_GLPES_PFIP4RXOCTSHI(_i) (0x00010204 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4511
-#define I40E_GLPES_PFIP4RXOCTSHI_MAX_INDEX 15
4512
-#define I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT 0
4513
-#define I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT)
4514
-#define I40E_GLPES_PFIP4RXOCTSLO(_i) (0x00010200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4515
-#define I40E_GLPES_PFIP4RXOCTSLO_MAX_INDEX 15
4516
-#define I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT 0
4517
-#define I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT)
4518
-#define I40E_GLPES_PFIP4RXPKTSHI(_i) (0x00010404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4519
-#define I40E_GLPES_PFIP4RXPKTSHI_MAX_INDEX 15
4520
-#define I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT 0
4521
-#define I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT)
4522
-#define I40E_GLPES_PFIP4RXPKTSLO(_i) (0x00010400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4523
-#define I40E_GLPES_PFIP4RXPKTSLO_MAX_INDEX 15
4524
-#define I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT 0
4525
-#define I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT)
4526
-#define I40E_GLPES_PFIP4RXTRUNC(_i) (0x00010700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
4527
-#define I40E_GLPES_PFIP4RXTRUNC_MAX_INDEX 15
4528
-#define I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_SHIFT 0
4529
-#define I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_SHIFT)
4530
-#define I40E_GLPES_PFIP4TXFRAGSHI(_i) (0x00011E04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4531
-#define I40E_GLPES_PFIP4TXFRAGSHI_MAX_INDEX 15
4532
-#define I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT 0
4533
-#define I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT)
4534
-#define I40E_GLPES_PFIP4TXFRAGSLO(_i) (0x00011E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4535
-#define I40E_GLPES_PFIP4TXFRAGSLO_MAX_INDEX 15
4536
-#define I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT 0
4537
-#define I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT)
4538
-#define I40E_GLPES_PFIP4TXMCOCTSHI(_i) (0x00012004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4539
-#define I40E_GLPES_PFIP4TXMCOCTSHI_MAX_INDEX 15
4540
-#define I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT 0
4541
-#define I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT)
4542
-#define I40E_GLPES_PFIP4TXMCOCTSLO(_i) (0x00012000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4543
-#define I40E_GLPES_PFIP4TXMCOCTSLO_MAX_INDEX 15
4544
-#define I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT 0
4545
-#define I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT)
4546
-#define I40E_GLPES_PFIP4TXMCPKTSHI(_i) (0x00012204 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4547
-#define I40E_GLPES_PFIP4TXMCPKTSHI_MAX_INDEX 15
4548
-#define I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT 0
4549
-#define I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT)
4550
-#define I40E_GLPES_PFIP4TXMCPKTSLO(_i) (0x00012200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4551
-#define I40E_GLPES_PFIP4TXMCPKTSLO_MAX_INDEX 15
4552
-#define I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT 0
4553
-#define I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT)
4554
-#define I40E_GLPES_PFIP4TXNOROUTE(_i) (0x00012E00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
4555
-#define I40E_GLPES_PFIP4TXNOROUTE_MAX_INDEX 15
4556
-#define I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT 0
4557
-#define I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT)
4558
-#define I40E_GLPES_PFIP4TXOCTSHI(_i) (0x00011A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4559
-#define I40E_GLPES_PFIP4TXOCTSHI_MAX_INDEX 15
4560
-#define I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT 0
4561
-#define I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT)
4562
-#define I40E_GLPES_PFIP4TXOCTSLO(_i) (0x00011A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4563
-#define I40E_GLPES_PFIP4TXOCTSLO_MAX_INDEX 15
4564
-#define I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT 0
4565
-#define I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT)
4566
-#define I40E_GLPES_PFIP4TXPKTSHI(_i) (0x00011C04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4567
-#define I40E_GLPES_PFIP4TXPKTSHI_MAX_INDEX 15
4568
-#define I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT 0
4569
-#define I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT)
4570
-#define I40E_GLPES_PFIP4TXPKTSLO(_i) (0x00011C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4571
-#define I40E_GLPES_PFIP4TXPKTSLO_MAX_INDEX 15
4572
-#define I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT 0
4573
-#define I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT)
4574
-#define I40E_GLPES_PFIP6RXDISCARD(_i) (0x00011200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
4575
-#define I40E_GLPES_PFIP6RXDISCARD_MAX_INDEX 15
4576
-#define I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_SHIFT 0
4577
-#define I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_SHIFT)
4578
-#define I40E_GLPES_PFIP6RXFRAGSHI(_i) (0x00011404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4579
-#define I40E_GLPES_PFIP6RXFRAGSHI_MAX_INDEX 15
4580
-#define I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT 0
4581
-#define I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT)
4582
-#define I40E_GLPES_PFIP6RXFRAGSLO(_i) (0x00011400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4583
-#define I40E_GLPES_PFIP6RXFRAGSLO_MAX_INDEX 15
4584
-#define I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT 0
4585
-#define I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT)
4586
-#define I40E_GLPES_PFIP6RXMCOCTSHI(_i) (0x00011604 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4587
-#define I40E_GLPES_PFIP6RXMCOCTSHI_MAX_INDEX 15
4588
-#define I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT 0
4589
-#define I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT)
4590
-#define I40E_GLPES_PFIP6RXMCOCTSLO(_i) (0x00011600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4591
-#define I40E_GLPES_PFIP6RXMCOCTSLO_MAX_INDEX 15
4592
-#define I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT 0
4593
-#define I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT)
4594
-#define I40E_GLPES_PFIP6RXMCPKTSHI(_i) (0x00011804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4595
-#define I40E_GLPES_PFIP6RXMCPKTSHI_MAX_INDEX 15
4596
-#define I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT 0
4597
-#define I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT)
4598
-#define I40E_GLPES_PFIP6RXMCPKTSLO(_i) (0x00011800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4599
-#define I40E_GLPES_PFIP6RXMCPKTSLO_MAX_INDEX 15
4600
-#define I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT 0
4601
-#define I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT)
4602
-#define I40E_GLPES_PFIP6RXOCTSHI(_i) (0x00010E04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4603
-#define I40E_GLPES_PFIP6RXOCTSHI_MAX_INDEX 15
4604
-#define I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT 0
4605
-#define I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT)
4606
-#define I40E_GLPES_PFIP6RXOCTSLO(_i) (0x00010E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4607
-#define I40E_GLPES_PFIP6RXOCTSLO_MAX_INDEX 15
4608
-#define I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT 0
4609
-#define I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT)
4610
-#define I40E_GLPES_PFIP6RXPKTSHI(_i) (0x00011004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4611
-#define I40E_GLPES_PFIP6RXPKTSHI_MAX_INDEX 15
4612
-#define I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT 0
4613
-#define I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT)
4614
-#define I40E_GLPES_PFIP6RXPKTSLO(_i) (0x00011000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4615
-#define I40E_GLPES_PFIP6RXPKTSLO_MAX_INDEX 15
4616
-#define I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT 0
4617
-#define I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT)
4618
-#define I40E_GLPES_PFIP6RXTRUNC(_i) (0x00011300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
4619
-#define I40E_GLPES_PFIP6RXTRUNC_MAX_INDEX 15
4620
-#define I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_SHIFT 0
4621
-#define I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_SHIFT)
4622
-#define I40E_GLPES_PFIP6TXFRAGSHI(_i) (0x00012804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4623
-#define I40E_GLPES_PFIP6TXFRAGSHI_MAX_INDEX 15
4624
-#define I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT 0
4625
-#define I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT)
4626
-#define I40E_GLPES_PFIP6TXFRAGSLO(_i) (0x00012800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4627
-#define I40E_GLPES_PFIP6TXFRAGSLO_MAX_INDEX 15
4628
-#define I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT 0
4629
-#define I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT)
4630
-#define I40E_GLPES_PFIP6TXMCOCTSHI(_i) (0x00012A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4631
-#define I40E_GLPES_PFIP6TXMCOCTSHI_MAX_INDEX 15
4632
-#define I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT 0
4633
-#define I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT)
4634
-#define I40E_GLPES_PFIP6TXMCOCTSLO(_i) (0x00012A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4635
-#define I40E_GLPES_PFIP6TXMCOCTSLO_MAX_INDEX 15
4636
-#define I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT 0
4637
-#define I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT)
4638
-#define I40E_GLPES_PFIP6TXMCPKTSHI(_i) (0x00012C04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4639
-#define I40E_GLPES_PFIP6TXMCPKTSHI_MAX_INDEX 15
4640
-#define I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT 0
4641
-#define I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT)
4642
-#define I40E_GLPES_PFIP6TXMCPKTSLO(_i) (0x00012C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4643
-#define I40E_GLPES_PFIP6TXMCPKTSLO_MAX_INDEX 15
4644
-#define I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT 0
4645
-#define I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT)
4646
-#define I40E_GLPES_PFIP6TXNOROUTE(_i) (0x00012F00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
4647
-#define I40E_GLPES_PFIP6TXNOROUTE_MAX_INDEX 15
4648
-#define I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT 0
4649
-#define I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT)
4650
-#define I40E_GLPES_PFIP6TXOCTSHI(_i) (0x00012404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4651
-#define I40E_GLPES_PFIP6TXOCTSHI_MAX_INDEX 15
4652
-#define I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT 0
4653
-#define I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT)
4654
-#define I40E_GLPES_PFIP6TXOCTSLO(_i) (0x00012400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4655
-#define I40E_GLPES_PFIP6TXOCTSLO_MAX_INDEX 15
4656
-#define I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT 0
4657
-#define I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT)
4658
-#define I40E_GLPES_PFIP6TXPKTSHI(_i) (0x00012604 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4659
-#define I40E_GLPES_PFIP6TXPKTSHI_MAX_INDEX 15
4660
-#define I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT 0
4661
-#define I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT)
4662
-#define I40E_GLPES_PFIP6TXPKTSLO(_i) (0x00012600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4663
-#define I40E_GLPES_PFIP6TXPKTSLO_MAX_INDEX 15
4664
-#define I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT 0
4665
-#define I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT)
4666
-#define I40E_GLPES_PFRDMARXRDSHI(_i) (0x00013E04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4667
-#define I40E_GLPES_PFRDMARXRDSHI_MAX_INDEX 15
4668
-#define I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_SHIFT 0
4669
-#define I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_SHIFT)
4670
-#define I40E_GLPES_PFRDMARXRDSLO(_i) (0x00013E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4671
-#define I40E_GLPES_PFRDMARXRDSLO_MAX_INDEX 15
4672
-#define I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_SHIFT 0
4673
-#define I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_SHIFT)
4674
-#define I40E_GLPES_PFRDMARXSNDSHI(_i) (0x00014004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4675
-#define I40E_GLPES_PFRDMARXSNDSHI_MAX_INDEX 15
4676
-#define I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT 0
4677
-#define I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT)
4678
-#define I40E_GLPES_PFRDMARXSNDSLO(_i) (0x00014000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4679
-#define I40E_GLPES_PFRDMARXSNDSLO_MAX_INDEX 15
4680
-#define I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT 0
4681
-#define I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT)
4682
-#define I40E_GLPES_PFRDMARXWRSHI(_i) (0x00013C04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4683
-#define I40E_GLPES_PFRDMARXWRSHI_MAX_INDEX 15
4684
-#define I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_SHIFT 0
4685
-#define I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_SHIFT)
4686
-#define I40E_GLPES_PFRDMARXWRSLO(_i) (0x00013C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4687
-#define I40E_GLPES_PFRDMARXWRSLO_MAX_INDEX 15
4688
-#define I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_SHIFT 0
4689
-#define I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_SHIFT)
4690
-#define I40E_GLPES_PFRDMATXRDSHI(_i) (0x00014404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4691
-#define I40E_GLPES_PFRDMATXRDSHI_MAX_INDEX 15
4692
-#define I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_SHIFT 0
4693
-#define I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_SHIFT)
4694
-#define I40E_GLPES_PFRDMATXRDSLO(_i) (0x00014400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4695
-#define I40E_GLPES_PFRDMATXRDSLO_MAX_INDEX 15
4696
-#define I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_SHIFT 0
4697
-#define I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_SHIFT)
4698
-#define I40E_GLPES_PFRDMATXSNDSHI(_i) (0x00014604 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4699
-#define I40E_GLPES_PFRDMATXSNDSHI_MAX_INDEX 15
4700
-#define I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT 0
4701
-#define I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT)
4702
-#define I40E_GLPES_PFRDMATXSNDSLO(_i) (0x00014600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4703
-#define I40E_GLPES_PFRDMATXSNDSLO_MAX_INDEX 15
4704
-#define I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT 0
4705
-#define I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT)
4706
-#define I40E_GLPES_PFRDMATXWRSHI(_i) (0x00014204 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4707
-#define I40E_GLPES_PFRDMATXWRSHI_MAX_INDEX 15
4708
-#define I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_SHIFT 0
4709
-#define I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_SHIFT)
4710
-#define I40E_GLPES_PFRDMATXWRSLO(_i) (0x00014200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4711
-#define I40E_GLPES_PFRDMATXWRSLO_MAX_INDEX 15
4712
-#define I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_SHIFT 0
4713
-#define I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_SHIFT)
4714
-#define I40E_GLPES_PFRDMAVBNDHI(_i) (0x00014804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4715
-#define I40E_GLPES_PFRDMAVBNDHI_MAX_INDEX 15
4716
-#define I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_SHIFT 0
4717
-#define I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_SHIFT)
4718
-#define I40E_GLPES_PFRDMAVBNDLO(_i) (0x00014800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4719
-#define I40E_GLPES_PFRDMAVBNDLO_MAX_INDEX 15
4720
-#define I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_SHIFT 0
4721
-#define I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_SHIFT)
4722
-#define I40E_GLPES_PFRDMAVINVHI(_i) (0x00014A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4723
-#define I40E_GLPES_PFRDMAVINVHI_MAX_INDEX 15
4724
-#define I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_SHIFT 0
4725
-#define I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_SHIFT)
4726
-#define I40E_GLPES_PFRDMAVINVLO(_i) (0x00014A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4727
-#define I40E_GLPES_PFRDMAVINVLO_MAX_INDEX 15
4728
-#define I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_SHIFT 0
4729
-#define I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_SHIFT)
4730
-#define I40E_GLPES_PFRXVLANERR(_i) (0x00010000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
4731
-#define I40E_GLPES_PFRXVLANERR_MAX_INDEX 15
4732
-#define I40E_GLPES_PFRXVLANERR_RXVLANERR_SHIFT 0
4733
-#define I40E_GLPES_PFRXVLANERR_RXVLANERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFRXVLANERR_RXVLANERR_SHIFT)
4734
-#define I40E_GLPES_PFTCPRTXSEG(_i) (0x00013600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
4735
-#define I40E_GLPES_PFTCPRTXSEG_MAX_INDEX 15
4736
-#define I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_SHIFT 0
4737
-#define I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_SHIFT)
4738
-#define I40E_GLPES_PFTCPRXOPTERR(_i) (0x00013200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
4739
-#define I40E_GLPES_PFTCPRXOPTERR_MAX_INDEX 15
4740
-#define I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_SHIFT 0
4741
-#define I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_SHIFT)
4742
-#define I40E_GLPES_PFTCPRXPROTOERR(_i) (0x00013300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
4743
-#define I40E_GLPES_PFTCPRXPROTOERR_MAX_INDEX 15
4744
-#define I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT 0
4745
-#define I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT)
4746
-#define I40E_GLPES_PFTCPRXSEGSHI(_i) (0x00013004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4747
-#define I40E_GLPES_PFTCPRXSEGSHI_MAX_INDEX 15
4748
-#define I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT 0
4749
-#define I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT)
4750
-#define I40E_GLPES_PFTCPRXSEGSLO(_i) (0x00013000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4751
-#define I40E_GLPES_PFTCPRXSEGSLO_MAX_INDEX 15
4752
-#define I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT 0
4753
-#define I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT)
4754
-#define I40E_GLPES_PFTCPTXSEGHI(_i) (0x00013404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4755
-#define I40E_GLPES_PFTCPTXSEGHI_MAX_INDEX 15
4756
-#define I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_SHIFT 0
4757
-#define I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_SHIFT)
4758
-#define I40E_GLPES_PFTCPTXSEGLO(_i) (0x00013400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4759
-#define I40E_GLPES_PFTCPTXSEGLO_MAX_INDEX 15
4760
-#define I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_SHIFT 0
4761
-#define I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_SHIFT)
4762
-#define I40E_GLPES_PFUDPRXPKTSHI(_i) (0x00013804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4763
-#define I40E_GLPES_PFUDPRXPKTSHI_MAX_INDEX 15
4764
-#define I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT 0
4765
-#define I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT)
4766
-#define I40E_GLPES_PFUDPRXPKTSLO(_i) (0x00013800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4767
-#define I40E_GLPES_PFUDPRXPKTSLO_MAX_INDEX 15
4768
-#define I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT 0
4769
-#define I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT)
4770
-#define I40E_GLPES_PFUDPTXPKTSHI(_i) (0x00013A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4771
-#define I40E_GLPES_PFUDPTXPKTSHI_MAX_INDEX 15
4772
-#define I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT 0
4773
-#define I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT)
4774
-#define I40E_GLPES_PFUDPTXPKTSLO(_i) (0x00013A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
4775
-#define I40E_GLPES_PFUDPTXPKTSLO_MAX_INDEX 15
4776
-#define I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT 0
4777
-#define I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT)
4778
-#define I40E_GLPES_RDMARXMULTFPDUSHI 0x0001E014 /* Reset: PE_CORER */
4779
-#define I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_SHIFT 0
4780
-#define I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_SHIFT)
4781
-#define I40E_GLPES_RDMARXMULTFPDUSLO 0x0001E010 /* Reset: PE_CORER */
4782
-#define I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_SHIFT 0
4783
-#define I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_SHIFT)
4784
-#define I40E_GLPES_RDMARXOOODDPHI 0x0001E01C /* Reset: PE_CORER */
4785
-#define I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_SHIFT 0
4786
-#define I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_SHIFT)
4787
-#define I40E_GLPES_RDMARXOOODDPLO 0x0001E018 /* Reset: PE_CORER */
4788
-#define I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_SHIFT 0
4789
-#define I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_SHIFT)
4790
-#define I40E_GLPES_RDMARXOOONOMARK 0x0001E004 /* Reset: PE_CORER */
4791
-#define I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_SHIFT 0
4792
-#define I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_SHIFT)
4793
-#define I40E_GLPES_RDMARXUNALIGN 0x0001E000 /* Reset: PE_CORER */
4794
-#define I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_SHIFT 0
4795
-#define I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_SHIFT)
4796
-#define I40E_GLPES_TCPRXFOURHOLEHI 0x0001E044 /* Reset: PE_CORER */
4797
-#define I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_SHIFT 0
4798
-#define I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_SHIFT)
4799
-#define I40E_GLPES_TCPRXFOURHOLELO 0x0001E040 /* Reset: PE_CORER */
4800
-#define I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_SHIFT 0
4801
-#define I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_SHIFT)
4802
-#define I40E_GLPES_TCPRXONEHOLEHI 0x0001E02C /* Reset: PE_CORER */
4803
-#define I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_SHIFT 0
4804
-#define I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_SHIFT)
4805
-#define I40E_GLPES_TCPRXONEHOLELO 0x0001E028 /* Reset: PE_CORER */
4806
-#define I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_SHIFT 0
4807
-#define I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_SHIFT)
4808
-#define I40E_GLPES_TCPRXPUREACKHI 0x0001E024 /* Reset: PE_CORER */
4809
-#define I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_SHIFT 0
4810
-#define I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_SHIFT)
4811
-#define I40E_GLPES_TCPRXPUREACKSLO 0x0001E020 /* Reset: PE_CORER */
4812
-#define I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_SHIFT 0
4813
-#define I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_SHIFT)
4814
-#define I40E_GLPES_TCPRXTHREEHOLEHI 0x0001E03C /* Reset: PE_CORER */
4815
-#define I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_SHIFT 0
4816
-#define I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_SHIFT)
4817
-#define I40E_GLPES_TCPRXTHREEHOLELO 0x0001E038 /* Reset: PE_CORER */
4818
-#define I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_SHIFT 0
4819
-#define I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_SHIFT)
4820
-#define I40E_GLPES_TCPRXTWOHOLEHI 0x0001E034 /* Reset: PE_CORER */
4821
-#define I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_SHIFT 0
4822
-#define I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_SHIFT)
4823
-#define I40E_GLPES_TCPRXTWOHOLELO 0x0001E030 /* Reset: PE_CORER */
4824
-#define I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_SHIFT 0
4825
-#define I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_SHIFT)
4826
-#define I40E_GLPES_TCPTXRETRANSFASTHI 0x0001E04C /* Reset: PE_CORER */
4827
-#define I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_SHIFT 0
4828
-#define I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_SHIFT)
4829
-#define I40E_GLPES_TCPTXRETRANSFASTLO 0x0001E048 /* Reset: PE_CORER */
4830
-#define I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_SHIFT 0
4831
-#define I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_SHIFT)
4832
-#define I40E_GLPES_TCPTXTOUTSFASTHI 0x0001E054 /* Reset: PE_CORER */
4833
-#define I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_SHIFT 0
4834
-#define I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_SHIFT)
4835
-#define I40E_GLPES_TCPTXTOUTSFASTLO 0x0001E050 /* Reset: PE_CORER */
4836
-#define I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_SHIFT 0
4837
-#define I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_SHIFT)
4838
-#define I40E_GLPES_TCPTXTOUTSHI 0x0001E05C /* Reset: PE_CORER */
4839
-#define I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_SHIFT 0
4840
-#define I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_SHIFT)
4841
-#define I40E_GLPES_TCPTXTOUTSLO 0x0001E058 /* Reset: PE_CORER */
4842
-#define I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_SHIFT 0
4843
-#define I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_SHIFT)
4844
-#define I40E_GLPES_VFIP4RXDISCARD(_i) (0x00018600 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */
4845
-#define I40E_GLPES_VFIP4RXDISCARD_MAX_INDEX 31
4846
-#define I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_SHIFT 0
4847
-#define I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_SHIFT)
4848
-#define I40E_GLPES_VFIP4RXFRAGSHI(_i) (0x00018804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4849
-#define I40E_GLPES_VFIP4RXFRAGSHI_MAX_INDEX 31
4850
-#define I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT 0
4851
-#define I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT)
4852
-#define I40E_GLPES_VFIP4RXFRAGSLO(_i) (0x00018800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4853
-#define I40E_GLPES_VFIP4RXFRAGSLO_MAX_INDEX 31
4854
-#define I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT 0
4855
-#define I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT)
4856
-#define I40E_GLPES_VFIP4RXMCOCTSHI(_i) (0x00018A04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4857
-#define I40E_GLPES_VFIP4RXMCOCTSHI_MAX_INDEX 31
4858
-#define I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT 0
4859
-#define I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT)
4860
-#define I40E_GLPES_VFIP4RXMCOCTSLO(_i) (0x00018A00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4861
-#define I40E_GLPES_VFIP4RXMCOCTSLO_MAX_INDEX 31
4862
-#define I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT 0
4863
-#define I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT)
4864
-#define I40E_GLPES_VFIP4RXMCPKTSHI(_i) (0x00018C04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4865
-#define I40E_GLPES_VFIP4RXMCPKTSHI_MAX_INDEX 31
4866
-#define I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT 0
4867
-#define I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT)
4868
-#define I40E_GLPES_VFIP4RXMCPKTSLO(_i) (0x00018C00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4869
-#define I40E_GLPES_VFIP4RXMCPKTSLO_MAX_INDEX 31
4870
-#define I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT 0
4871
-#define I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT)
4872
-#define I40E_GLPES_VFIP4RXOCTSHI(_i) (0x00018204 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4873
-#define I40E_GLPES_VFIP4RXOCTSHI_MAX_INDEX 31
4874
-#define I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT 0
4875
-#define I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT)
4876
-#define I40E_GLPES_VFIP4RXOCTSLO(_i) (0x00018200 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4877
-#define I40E_GLPES_VFIP4RXOCTSLO_MAX_INDEX 31
4878
-#define I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT 0
4879
-#define I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT)
4880
-#define I40E_GLPES_VFIP4RXPKTSHI(_i) (0x00018404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4881
-#define I40E_GLPES_VFIP4RXPKTSHI_MAX_INDEX 31
4882
-#define I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT 0
4883
-#define I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT)
4884
-#define I40E_GLPES_VFIP4RXPKTSLO(_i) (0x00018400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4885
-#define I40E_GLPES_VFIP4RXPKTSLO_MAX_INDEX 31
4886
-#define I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT 0
4887
-#define I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT)
4888
-#define I40E_GLPES_VFIP4RXTRUNC(_i) (0x00018700 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */
4889
-#define I40E_GLPES_VFIP4RXTRUNC_MAX_INDEX 31
4890
-#define I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_SHIFT 0
4891
-#define I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_SHIFT)
4892
-#define I40E_GLPES_VFIP4TXFRAGSHI(_i) (0x00019E04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4893
-#define I40E_GLPES_VFIP4TXFRAGSHI_MAX_INDEX 31
4894
-#define I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT 0
4895
-#define I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT)
4896
-#define I40E_GLPES_VFIP4TXFRAGSLO(_i) (0x00019E00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4897
-#define I40E_GLPES_VFIP4TXFRAGSLO_MAX_INDEX 31
4898
-#define I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT 0
4899
-#define I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT)
4900
-#define I40E_GLPES_VFIP4TXMCOCTSHI(_i) (0x0001A004 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4901
-#define I40E_GLPES_VFIP4TXMCOCTSHI_MAX_INDEX 31
4902
-#define I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT 0
4903
-#define I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT)
4904
-#define I40E_GLPES_VFIP4TXMCOCTSLO(_i) (0x0001A000 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4905
-#define I40E_GLPES_VFIP4TXMCOCTSLO_MAX_INDEX 31
4906
-#define I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT 0
4907
-#define I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT)
4908
-#define I40E_GLPES_VFIP4TXMCPKTSHI(_i) (0x0001A204 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4909
-#define I40E_GLPES_VFIP4TXMCPKTSHI_MAX_INDEX 31
4910
-#define I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT 0
4911
-#define I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT)
4912
-#define I40E_GLPES_VFIP4TXMCPKTSLO(_i) (0x0001A200 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4913
-#define I40E_GLPES_VFIP4TXMCPKTSLO_MAX_INDEX 31
4914
-#define I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT 0
4915
-#define I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT)
4916
-#define I40E_GLPES_VFIP4TXNOROUTE(_i) (0x0001AE00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */
4917
-#define I40E_GLPES_VFIP4TXNOROUTE_MAX_INDEX 31
4918
-#define I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT 0
4919
-#define I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT)
4920
-#define I40E_GLPES_VFIP4TXOCTSHI(_i) (0x00019A04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4921
-#define I40E_GLPES_VFIP4TXOCTSHI_MAX_INDEX 31
4922
-#define I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT 0
4923
-#define I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT)
4924
-#define I40E_GLPES_VFIP4TXOCTSLO(_i) (0x00019A00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4925
-#define I40E_GLPES_VFIP4TXOCTSLO_MAX_INDEX 31
4926
-#define I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT 0
4927
-#define I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT)
4928
-#define I40E_GLPES_VFIP4TXPKTSHI(_i) (0x00019C04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4929
-#define I40E_GLPES_VFIP4TXPKTSHI_MAX_INDEX 31
4930
-#define I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT 0
4931
-#define I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT)
4932
-#define I40E_GLPES_VFIP4TXPKTSLO(_i) (0x00019C00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4933
-#define I40E_GLPES_VFIP4TXPKTSLO_MAX_INDEX 31
4934
-#define I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT 0
4935
-#define I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT)
4936
-#define I40E_GLPES_VFIP6RXDISCARD(_i) (0x00019200 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */
4937
-#define I40E_GLPES_VFIP6RXDISCARD_MAX_INDEX 31
4938
-#define I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_SHIFT 0
4939
-#define I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_SHIFT)
4940
-#define I40E_GLPES_VFIP6RXFRAGSHI(_i) (0x00019404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4941
-#define I40E_GLPES_VFIP6RXFRAGSHI_MAX_INDEX 31
4942
-#define I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT 0
4943
-#define I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT)
4944
-#define I40E_GLPES_VFIP6RXFRAGSLO(_i) (0x00019400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4945
-#define I40E_GLPES_VFIP6RXFRAGSLO_MAX_INDEX 31
4946
-#define I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT 0
4947
-#define I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT)
4948
-#define I40E_GLPES_VFIP6RXMCOCTSHI(_i) (0x00019604 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4949
-#define I40E_GLPES_VFIP6RXMCOCTSHI_MAX_INDEX 31
4950
-#define I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT 0
4951
-#define I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT)
4952
-#define I40E_GLPES_VFIP6RXMCOCTSLO(_i) (0x00019600 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4953
-#define I40E_GLPES_VFIP6RXMCOCTSLO_MAX_INDEX 31
4954
-#define I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT 0
4955
-#define I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT)
4956
-#define I40E_GLPES_VFIP6RXMCPKTSHI(_i) (0x00019804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4957
-#define I40E_GLPES_VFIP6RXMCPKTSHI_MAX_INDEX 31
4958
-#define I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT 0
4959
-#define I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT)
4960
-#define I40E_GLPES_VFIP6RXMCPKTSLO(_i) (0x00019800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4961
-#define I40E_GLPES_VFIP6RXMCPKTSLO_MAX_INDEX 31
4962
-#define I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT 0
4963
-#define I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT)
4964
-#define I40E_GLPES_VFIP6RXOCTSHI(_i) (0x00018E04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4965
-#define I40E_GLPES_VFIP6RXOCTSHI_MAX_INDEX 31
4966
-#define I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT 0
4967
-#define I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT)
4968
-#define I40E_GLPES_VFIP6RXOCTSLO(_i) (0x00018E00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4969
-#define I40E_GLPES_VFIP6RXOCTSLO_MAX_INDEX 31
4970
-#define I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT 0
4971
-#define I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT)
4972
-#define I40E_GLPES_VFIP6RXPKTSHI(_i) (0x00019004 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4973
-#define I40E_GLPES_VFIP6RXPKTSHI_MAX_INDEX 31
4974
-#define I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT 0
4975
-#define I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT)
4976
-#define I40E_GLPES_VFIP6RXPKTSLO(_i) (0x00019000 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4977
-#define I40E_GLPES_VFIP6RXPKTSLO_MAX_INDEX 31
4978
-#define I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT 0
4979
-#define I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT)
4980
-#define I40E_GLPES_VFIP6RXTRUNC(_i) (0x00019300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */
4981
-#define I40E_GLPES_VFIP6RXTRUNC_MAX_INDEX 31
4982
-#define I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_SHIFT 0
4983
-#define I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_SHIFT)
4984
-#define I40E_GLPES_VFIP6TXFRAGSHI(_i) (0x0001A804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4985
-#define I40E_GLPES_VFIP6TXFRAGSHI_MAX_INDEX 31
4986
-#define I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT 0
4987
-#define I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT)
4988
-#define I40E_GLPES_VFIP6TXFRAGSLO(_i) (0x0001A800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4989
-#define I40E_GLPES_VFIP6TXFRAGSLO_MAX_INDEX 31
4990
-#define I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT 0
4991
-#define I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT)
4992
-#define I40E_GLPES_VFIP6TXMCOCTSHI(_i) (0x0001AA04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4993
-#define I40E_GLPES_VFIP6TXMCOCTSHI_MAX_INDEX 31
4994
-#define I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT 0
4995
-#define I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT)
4996
-#define I40E_GLPES_VFIP6TXMCOCTSLO(_i) (0x0001AA00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
4997
-#define I40E_GLPES_VFIP6TXMCOCTSLO_MAX_INDEX 31
4998
-#define I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT 0
4999
-#define I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT)
5000
-#define I40E_GLPES_VFIP6TXMCPKTSHI(_i) (0x0001AC04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5001
-#define I40E_GLPES_VFIP6TXMCPKTSHI_MAX_INDEX 31
5002
-#define I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT 0
5003
-#define I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT)
5004
-#define I40E_GLPES_VFIP6TXMCPKTSLO(_i) (0x0001AC00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5005
-#define I40E_GLPES_VFIP6TXMCPKTSLO_MAX_INDEX 31
5006
-#define I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT 0
5007
-#define I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT)
5008
-#define I40E_GLPES_VFIP6TXNOROUTE(_i) (0x0001AF00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */
5009
-#define I40E_GLPES_VFIP6TXNOROUTE_MAX_INDEX 31
5010
-#define I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT 0
5011
-#define I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT)
5012
-#define I40E_GLPES_VFIP6TXOCTSHI(_i) (0x0001A404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5013
-#define I40E_GLPES_VFIP6TXOCTSHI_MAX_INDEX 31
5014
-#define I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT 0
5015
-#define I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT)
5016
-#define I40E_GLPES_VFIP6TXOCTSLO(_i) (0x0001A400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5017
-#define I40E_GLPES_VFIP6TXOCTSLO_MAX_INDEX 31
5018
-#define I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT 0
5019
-#define I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT)
5020
-#define I40E_GLPES_VFIP6TXPKTSHI(_i) (0x0001A604 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5021
-#define I40E_GLPES_VFIP6TXPKTSHI_MAX_INDEX 31
5022
-#define I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT 0
5023
-#define I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT)
5024
-#define I40E_GLPES_VFIP6TXPKTSLO(_i) (0x0001A600 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5025
-#define I40E_GLPES_VFIP6TXPKTSLO_MAX_INDEX 31
5026
-#define I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT 0
5027
-#define I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT)
5028
-#define I40E_GLPES_VFRDMARXRDSHI(_i) (0x0001BE04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5029
-#define I40E_GLPES_VFRDMARXRDSHI_MAX_INDEX 31
5030
-#define I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_SHIFT 0
5031
-#define I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_SHIFT)
5032
-#define I40E_GLPES_VFRDMARXRDSLO(_i) (0x0001BE00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5033
-#define I40E_GLPES_VFRDMARXRDSLO_MAX_INDEX 31
5034
-#define I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_SHIFT 0
5035
-#define I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_SHIFT)
5036
-#define I40E_GLPES_VFRDMARXSNDSHI(_i) (0x0001C004 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5037
-#define I40E_GLPES_VFRDMARXSNDSHI_MAX_INDEX 31
5038
-#define I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT 0
5039
-#define I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT)
5040
-#define I40E_GLPES_VFRDMARXSNDSLO(_i) (0x0001C000 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5041
-#define I40E_GLPES_VFRDMARXSNDSLO_MAX_INDEX 31
5042
-#define I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT 0
5043
-#define I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT)
5044
-#define I40E_GLPES_VFRDMARXWRSHI(_i) (0x0001BC04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5045
-#define I40E_GLPES_VFRDMARXWRSHI_MAX_INDEX 31
5046
-#define I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_SHIFT 0
5047
-#define I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_SHIFT)
5048
-#define I40E_GLPES_VFRDMARXWRSLO(_i) (0x0001BC00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5049
-#define I40E_GLPES_VFRDMARXWRSLO_MAX_INDEX 31
5050
-#define I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_SHIFT 0
5051
-#define I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_SHIFT)
5052
-#define I40E_GLPES_VFRDMATXRDSHI(_i) (0x0001C404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5053
-#define I40E_GLPES_VFRDMATXRDSHI_MAX_INDEX 31
5054
-#define I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_SHIFT 0
5055
-#define I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_SHIFT)
5056
-#define I40E_GLPES_VFRDMATXRDSLO(_i) (0x0001C400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5057
-#define I40E_GLPES_VFRDMATXRDSLO_MAX_INDEX 31
5058
-#define I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_SHIFT 0
5059
-#define I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_SHIFT)
5060
-#define I40E_GLPES_VFRDMATXSNDSHI(_i) (0x0001C604 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5061
-#define I40E_GLPES_VFRDMATXSNDSHI_MAX_INDEX 31
5062
-#define I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT 0
5063
-#define I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT)
5064
-#define I40E_GLPES_VFRDMATXSNDSLO(_i) (0x0001C600 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5065
-#define I40E_GLPES_VFRDMATXSNDSLO_MAX_INDEX 31
5066
-#define I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT 0
5067
-#define I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT)
5068
-#define I40E_GLPES_VFRDMATXWRSHI(_i) (0x0001C204 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5069
-#define I40E_GLPES_VFRDMATXWRSHI_MAX_INDEX 31
5070
-#define I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_SHIFT 0
5071
-#define I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_SHIFT)
5072
-#define I40E_GLPES_VFRDMATXWRSLO(_i) (0x0001C200 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5073
-#define I40E_GLPES_VFRDMATXWRSLO_MAX_INDEX 31
5074
-#define I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_SHIFT 0
5075
-#define I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_SHIFT)
5076
-#define I40E_GLPES_VFRDMAVBNDHI(_i) (0x0001C804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5077
-#define I40E_GLPES_VFRDMAVBNDHI_MAX_INDEX 31
5078
-#define I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_SHIFT 0
5079
-#define I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_SHIFT)
5080
-#define I40E_GLPES_VFRDMAVBNDLO(_i) (0x0001C800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5081
-#define I40E_GLPES_VFRDMAVBNDLO_MAX_INDEX 31
5082
-#define I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_SHIFT 0
5083
-#define I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_SHIFT)
5084
-#define I40E_GLPES_VFRDMAVINVHI(_i) (0x0001CA04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5085
-#define I40E_GLPES_VFRDMAVINVHI_MAX_INDEX 31
5086
-#define I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_SHIFT 0
5087
-#define I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_SHIFT)
5088
-#define I40E_GLPES_VFRDMAVINVLO(_i) (0x0001CA00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5089
-#define I40E_GLPES_VFRDMAVINVLO_MAX_INDEX 31
5090
-#define I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_SHIFT 0
5091
-#define I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_SHIFT)
5092
-#define I40E_GLPES_VFRXVLANERR(_i) (0x00018000 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */
5093
-#define I40E_GLPES_VFRXVLANERR_MAX_INDEX 31
5094
-#define I40E_GLPES_VFRXVLANERR_RXVLANERR_SHIFT 0
5095
-#define I40E_GLPES_VFRXVLANERR_RXVLANERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFRXVLANERR_RXVLANERR_SHIFT)
5096
-#define I40E_GLPES_VFTCPRTXSEG(_i) (0x0001B600 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */
5097
-#define I40E_GLPES_VFTCPRTXSEG_MAX_INDEX 31
5098
-#define I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_SHIFT 0
5099
-#define I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_SHIFT)
5100
-#define I40E_GLPES_VFTCPRXOPTERR(_i) (0x0001B200 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */
5101
-#define I40E_GLPES_VFTCPRXOPTERR_MAX_INDEX 31
5102
-#define I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_SHIFT 0
5103
-#define I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_SHIFT)
5104
-#define I40E_GLPES_VFTCPRXPROTOERR(_i) (0x0001B300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */
5105
-#define I40E_GLPES_VFTCPRXPROTOERR_MAX_INDEX 31
5106
-#define I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT 0
5107
-#define I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT)
5108
-#define I40E_GLPES_VFTCPRXSEGSHI(_i) (0x0001B004 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5109
-#define I40E_GLPES_VFTCPRXSEGSHI_MAX_INDEX 31
5110
-#define I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT 0
5111
-#define I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT)
5112
-#define I40E_GLPES_VFTCPRXSEGSLO(_i) (0x0001B000 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5113
-#define I40E_GLPES_VFTCPRXSEGSLO_MAX_INDEX 31
5114
-#define I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT 0
5115
-#define I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT)
5116
-#define I40E_GLPES_VFTCPTXSEGHI(_i) (0x0001B404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5117
-#define I40E_GLPES_VFTCPTXSEGHI_MAX_INDEX 31
5118
-#define I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_SHIFT 0
5119
-#define I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_SHIFT)
5120
-#define I40E_GLPES_VFTCPTXSEGLO(_i) (0x0001B400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5121
-#define I40E_GLPES_VFTCPTXSEGLO_MAX_INDEX 31
5122
-#define I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_SHIFT 0
5123
-#define I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_SHIFT)
5124
-#define I40E_GLPES_VFUDPRXPKTSHI(_i) (0x0001B804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5125
-#define I40E_GLPES_VFUDPRXPKTSHI_MAX_INDEX 31
5126
-#define I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT 0
5127
-#define I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT)
5128
-#define I40E_GLPES_VFUDPRXPKTSLO(_i) (0x0001B800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5129
-#define I40E_GLPES_VFUDPRXPKTSLO_MAX_INDEX 31
5130
-#define I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT 0
5131
-#define I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT)
5132
-#define I40E_GLPES_VFUDPTXPKTSHI(_i) (0x0001BA04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5133
-#define I40E_GLPES_VFUDPTXPKTSHI_MAX_INDEX 31
5134
-#define I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT 0
5135
-#define I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT)
5136
-#define I40E_GLPES_VFUDPTXPKTSLO(_i) (0x0001BA00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */
5137
-#define I40E_GLPES_VFUDPTXPKTSLO_MAX_INDEX 31
5138
-#define I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT 0
5139
-#define I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT)
5140
-#define I40E_GLGEN_PME_TO 0x000B81BC /* Reset: POR */
5141
-#define I40E_GLGEN_PME_TO_PME_TO_FOR_PE_SHIFT 0
5142
-#define I40E_GLGEN_PME_TO_PME_TO_FOR_PE_MASK I40E_MASK(0x1, I40E_GLGEN_PME_TO_PME_TO_FOR_PE_SHIFT)
5143
-#define I40E_GLQF_APBVT(_i) (0x00260000 + ((_i) * 4)) /* _i=0...2047 */ /* Reset: CORER */
5144
-#define I40E_GLQF_APBVT_MAX_INDEX 2047
5145
-#define I40E_GLQF_APBVT_APBVT_SHIFT 0
5146
-#define I40E_GLQF_APBVT_APBVT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLQF_APBVT_APBVT_SHIFT)
5147
-#define I40E_GLQF_FD_PCTYPES(_i) (0x00268000 + ((_i) * 4)) /* _i=0...63 */ /* Reset: POR */
5148
-#define I40E_GLQF_FD_PCTYPES_MAX_INDEX 63
5149
-#define I40E_GLQF_FD_PCTYPES_FD_PCTYPE_SHIFT 0
5150
-#define I40E_GLQF_FD_PCTYPES_FD_PCTYPE_MASK I40E_MASK(0x3F, I40E_GLQF_FD_PCTYPES_FD_PCTYPE_SHIFT)
5151
-#define I40E_GLQF_FD_MSK(_i, _j) (0x00267200 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */
5152
-#define I40E_GLQF_FD_MSK_MAX_INDEX 1
5153
-#define I40E_GLQF_FD_MSK_MASK_SHIFT 0
5154
-#define I40E_GLQF_FD_MSK_MASK_MASK I40E_MASK(0xFFFF, I40E_GLQF_FD_MSK_MASK_SHIFT)
5155
-#define I40E_GLQF_FD_MSK_OFFSET_SHIFT 16
5156
-#define I40E_GLQF_FD_MSK_OFFSET_MASK I40E_MASK(0x3F, I40E_GLQF_FD_MSK_OFFSET_SHIFT)
5157
687
 #define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */
5158
-#define I40E_GLQF_HASH_INSET_MAX_INDEX 1
5159
-#define I40E_GLQF_HASH_INSET_INSET_SHIFT 0
5160
-#define I40E_GLQF_HASH_INSET_INSET_MASK I40E_MASK(0xFFFFFFFF, I40E_GLQF_HASH_INSET_INSET_SHIFT)
5161
-#define I40E_GLQF_HASH_MSK(_i, _j) (0x00267A00 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */
5162
-#define I40E_GLQF_HASH_MSK_MAX_INDEX 1
5163
-#define I40E_GLQF_HASH_MSK_MASK_SHIFT 0
5164
-#define I40E_GLQF_HASH_MSK_MASK_MASK I40E_MASK(0xFFFF, I40E_GLQF_HASH_MSK_MASK_SHIFT)
5165
-#define I40E_GLQF_HASH_MSK_OFFSET_SHIFT 16
5166
-#define I40E_GLQF_HASH_MSK_OFFSET_MASK I40E_MASK(0x3F, I40E_GLQF_HASH_MSK_OFFSET_SHIFT)
5167
688
 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4)) /* _i=0...63 */ /* Reset: CORER */
5168
-#define I40E_GLQF_ORT_MAX_INDEX 63
5169
689
 #define I40E_GLQF_ORT_PIT_INDX_SHIFT 0
5170
690
 #define I40E_GLQF_ORT_PIT_INDX_MASK I40E_MASK(0x1F, I40E_GLQF_ORT_PIT_INDX_SHIFT)
5171
691
 #define I40E_GLQF_ORT_FIELD_CNT_SHIFT 5
5172
692
 #define I40E_GLQF_ORT_FIELD_CNT_MASK I40E_MASK(0x3, I40E_GLQF_ORT_FIELD_CNT_SHIFT)
5173
693
 #define I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT 7
5174
694
 #define I40E_GLQF_ORT_FLX_PAYLOAD_MASK I40E_MASK(0x1, I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT)
5175
-#define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4)) /* _i=0...23 */ /* Reset: CORER */
5176
-#define I40E_GLQF_PIT_MAX_INDEX 23
5177
-#define I40E_GLQF_PIT_SOURCE_OFF_SHIFT 0
5178
-#define I40E_GLQF_PIT_SOURCE_OFF_MASK I40E_MASK(0x1F, I40E_GLQF_PIT_SOURCE_OFF_SHIFT)
5179
-#define I40E_GLQF_PIT_FSIZE_SHIFT 5
5180
-#define I40E_GLQF_PIT_FSIZE_MASK I40E_MASK(0x1F, I40E_GLQF_PIT_FSIZE_SHIFT)
5181
-#define I40E_GLQF_PIT_DEST_OFF_SHIFT 10
5182
-#define I40E_GLQF_PIT_DEST_OFF_MASK I40E_MASK(0x3F, I40E_GLQF_PIT_DEST_OFF_SHIFT)
5183
695
 #define I40E_GLQF_FDEVICTENA(_i) (0x00270384 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
5184
-#define I40E_GLQF_FDEVICTENA_MAX_INDEX 1
5185
-#define I40E_GLQF_FDEVICTENA_GLQF_FDEVICTENA_SHIFT 0
5186
-#define I40E_GLQF_FDEVICTENA_GLQF_FDEVICTENA_MASK I40E_MASK(0xFFFFFFFF, I40E_GLQF_FDEVICTENA_GLQF_FDEVICTENA_SHIFT)
5187
-#define I40E_GLQF_FDEVICTFLAG 0x00270280 /* Reset: CORER */
5188
-#define I40E_GLQF_FDEVICTFLAG_TX_FLAGS_SHIFT 0
5189
-#define I40E_GLQF_FDEVICTFLAG_TX_FLAGS_MASK I40E_MASK(0xFF, I40E_GLQF_FDEVICTFLAG_TX_FLAGS_SHIFT)
5190
-#define I40E_GLQF_FDEVICTFLAG_RX_FLAGS_SHIFT 8
5191
-#define I40E_GLQF_FDEVICTFLAG_RX_FLAGS_MASK I40E_MASK(0xFF, I40E_GLQF_FDEVICTFLAG_RX_FLAGS_SHIFT)
5192
-#define I40E_PFQF_CTL_2 0x00270300 /* Reset: CORER */
5193
-#define I40E_PFQF_CTL_2_PEHSIZE_SHIFT 0
5194
-#define I40E_PFQF_CTL_2_PEHSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_2_PEHSIZE_SHIFT)
5195
-#define I40E_PFQF_CTL_2_PEDSIZE_SHIFT 5
5196
-#define I40E_PFQF_CTL_2_PEDSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_2_PEDSIZE_SHIFT)
5197
696
 /* Redefined for X722 family */
5198
-#define I40E_X722_PFQF_HLUT(_i) (0x00240000 + ((_i) * 128)) /* _i=0...127 */ /* Reset: CORER */
5199
-#define I40E_X722_PFQF_HLUT_MAX_INDEX 127
5200
-#define I40E_X722_PFQF_HLUT_LUT0_SHIFT 0
5201
-#define I40E_X722_PFQF_HLUT_LUT0_MASK I40E_MASK(0x7F, I40E_X722_PFQF_HLUT_LUT0_SHIFT)
5202
-#define I40E_X722_PFQF_HLUT_LUT1_SHIFT 8
5203
-#define I40E_X722_PFQF_HLUT_LUT1_MASK I40E_MASK(0x7F, I40E_X722_PFQF_HLUT_LUT1_SHIFT)
5204
-#define I40E_X722_PFQF_HLUT_LUT2_SHIFT 16
5205
-#define I40E_X722_PFQF_HLUT_LUT2_MASK I40E_MASK(0x7F, I40E_X722_PFQF_HLUT_LUT2_SHIFT)
5206
-#define I40E_X722_PFQF_HLUT_LUT3_SHIFT 24
5207
-#define I40E_X722_PFQF_HLUT_LUT3_MASK I40E_MASK(0x7F, I40E_X722_PFQF_HLUT_LUT3_SHIFT)
5208
-#define I40E_PFQF_HREGION(_i) (0x00245400 + ((_i) * 128)) /* _i=0...7 */ /* Reset: CORER */
5209
-#define I40E_PFQF_HREGION_MAX_INDEX 7
5210
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0
5211
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_0_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT)
5212
-#define I40E_PFQF_HREGION_REGION_0_SHIFT 1
5213
-#define I40E_PFQF_HREGION_REGION_0_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_0_SHIFT)
5214
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4
5215
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_1_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT)
5216
-#define I40E_PFQF_HREGION_REGION_1_SHIFT 5
5217
-#define I40E_PFQF_HREGION_REGION_1_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_1_SHIFT)
5218
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8
5219
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_2_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT)
5220
-#define I40E_PFQF_HREGION_REGION_2_SHIFT 9
5221
-#define I40E_PFQF_HREGION_REGION_2_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_2_SHIFT)
5222
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12
5223
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_3_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT)
5224
-#define I40E_PFQF_HREGION_REGION_3_SHIFT 13
5225
-#define I40E_PFQF_HREGION_REGION_3_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_3_SHIFT)
5226
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16
5227
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_4_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT)
5228
-#define I40E_PFQF_HREGION_REGION_4_SHIFT 17
5229
-#define I40E_PFQF_HREGION_REGION_4_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_4_SHIFT)
5230
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20
5231
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_5_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT)
5232
-#define I40E_PFQF_HREGION_REGION_5_SHIFT 21
5233
-#define I40E_PFQF_HREGION_REGION_5_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_5_SHIFT)
5234
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24
5235
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT)
5236
-#define I40E_PFQF_HREGION_REGION_6_SHIFT 25
5237
-#define I40E_PFQF_HREGION_REGION_6_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_6_SHIFT)
5238
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28
5239
-#define I40E_PFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT)
5240
-#define I40E_PFQF_HREGION_REGION_7_SHIFT 29
5241
-#define I40E_PFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_7_SHIFT)
5242
-#define I40E_VSIQF_CTL_RSS_LUT_TYPE_SHIFT 8
5243
-#define I40E_VSIQF_CTL_RSS_LUT_TYPE_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_RSS_LUT_TYPE_SHIFT)
5244
-#define I40E_VSIQF_HKEY(_i, _VSI) (0x002A0000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...12, _VSI=0...383 */ /* Reset: CORER */
5245
-#define I40E_VSIQF_HKEY_MAX_INDEX 12
5246
-#define I40E_VSIQF_HKEY_KEY_0_SHIFT 0
5247
-#define I40E_VSIQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_VSIQF_HKEY_KEY_0_SHIFT)
5248
-#define I40E_VSIQF_HKEY_KEY_1_SHIFT 8
5249
-#define I40E_VSIQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_VSIQF_HKEY_KEY_1_SHIFT)
5250
-#define I40E_VSIQF_HKEY_KEY_2_SHIFT 16
5251
-#define I40E_VSIQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_VSIQF_HKEY_KEY_2_SHIFT)
5252
-#define I40E_VSIQF_HKEY_KEY_3_SHIFT 24
5253
-#define I40E_VSIQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_VSIQF_HKEY_KEY_3_SHIFT)
5254
-#define I40E_VSIQF_HLUT(_i, _VSI) (0x00220000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...15, _VSI=0...383 */ /* Reset: CORER */
5255
-#define I40E_VSIQF_HLUT_MAX_INDEX 15
5256
-#define I40E_VSIQF_HLUT_LUT0_SHIFT 0
5257
-#define I40E_VSIQF_HLUT_LUT0_MASK I40E_MASK(0xF, I40E_VSIQF_HLUT_LUT0_SHIFT)
5258
-#define I40E_VSIQF_HLUT_LUT1_SHIFT 8
5259
-#define I40E_VSIQF_HLUT_LUT1_MASK I40E_MASK(0xF, I40E_VSIQF_HLUT_LUT1_SHIFT)
5260
-#define I40E_VSIQF_HLUT_LUT2_SHIFT 16
5261
-#define I40E_VSIQF_HLUT_LUT2_MASK I40E_MASK(0xF, I40E_VSIQF_HLUT_LUT2_SHIFT)
5262
-#define I40E_VSIQF_HLUT_LUT3_SHIFT 24
5263
-#define I40E_VSIQF_HLUT_LUT3_MASK I40E_MASK(0xF, I40E_VSIQF_HLUT_LUT3_SHIFT)
5264
697
 #define I40E_GLGEN_STAT_CLEAR 0x00390004 /* Reset: CORER */
5265
-#define I40E_GLGEN_STAT_CLEAR_GLGEN_STAT_CLEAR_SHIFT 0
5266
-#define I40E_GLGEN_STAT_CLEAR_GLGEN_STAT_CLEAR_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_CLEAR_GLGEN_STAT_CLEAR_SHIFT)
5267
-#define I40E_GLGEN_STAT_HALT 0x00390000 /* Reset: CORER */
5268
-#define I40E_GLGEN_STAT_HALT_HALT_CELLS_SHIFT 0
5269
-#define I40E_GLGEN_STAT_HALT_HALT_CELLS_MASK I40E_MASK(0x3FFFFFFF, I40E_GLGEN_STAT_HALT_HALT_CELLS_SHIFT)
5270
-#define I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT 30
5271
-#define I40E_VFINT_DYN_CTL01_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT)
5272
-#define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30
5273
-#define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT)
5274
-#define I40E_VFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */
5275
-#define I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT 0
5276
-#define I40E_VFPE_AEQALLOC1_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT)
5277
-#define I40E_VFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */
5278
-#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT 0
5279
-#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT)
5280
-#define I40E_VFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */
5281
-#define I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT 0
5282
-#define I40E_VFPE_CCQPLOW1_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT)
5283
-#define I40E_VFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */
5284
-#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT 0
5285
-#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT)
5286
-#define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT 4
5287
-#define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT)
5288
-#define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT 16
5289
-#define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT)
5290
-#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT 31
5291
-#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT)
5292
-#define I40E_VFPE_CQACK1 0x0000B000 /* Reset: VFR */
5293
-#define I40E_VFPE_CQACK1_PECQID_SHIFT 0
5294
-#define I40E_VFPE_CQACK1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQACK1_PECQID_SHIFT)
5295
-#define I40E_VFPE_CQARM1 0x0000B400 /* Reset: VFR */
5296
-#define I40E_VFPE_CQARM1_PECQID_SHIFT 0
5297
-#define I40E_VFPE_CQARM1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQARM1_PECQID_SHIFT)
5298
-#define I40E_VFPE_CQPDB1 0x0000BC00 /* Reset: VFR */
5299
-#define I40E_VFPE_CQPDB1_WQHEAD_SHIFT 0
5300
-#define I40E_VFPE_CQPDB1_WQHEAD_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPDB1_WQHEAD_SHIFT)
5301
-#define I40E_VFPE_CQPERRCODES1 0x00009C00 /* Reset: VFR */
5302
-#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT 0
5303
-#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT)
5304
-#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT 16
5305
-#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT)
5306
-#define I40E_VFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */
5307
-#define I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT 0
5308
-#define I40E_VFPE_CQPTAIL1_WQTAIL_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT)
5309
-#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT 31
5310
-#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT)
5311
-#define I40E_VFPE_IPCONFIG01 0x00008C00 /* Reset: VFR */
5312
-#define I40E_VFPE_IPCONFIG01_PEIPID_SHIFT 0
5313
-#define I40E_VFPE_IPCONFIG01_PEIPID_MASK I40E_MASK(0xFFFF, I40E_VFPE_IPCONFIG01_PEIPID_SHIFT)
5314
-#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT 16
5315
-#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_MASK I40E_MASK(0x1, I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT)
5316
-#define I40E_VFPE_MRTEIDXMASK1 0x00009000 /* Reset: VFR */
5317
-#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT 0
5318
-#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT)
5319
-#define I40E_VFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset: VFR */
5320
-#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT 0
5321
-#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT)
5322
-#define I40E_VFPE_TCPNOWTIMER1 0x0000A800 /* Reset: VFR */
5323
-#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT 0
5324
-#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT)
5325
-#define I40E_VFPE_WQEALLOC1 0x0000C000 /* Reset: VFR */
5326
-#define I40E_VFPE_WQEALLOC1_PEQPID_SHIFT 0
5327
-#define I40E_VFPE_WQEALLOC1_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_VFPE_WQEALLOC1_PEQPID_SHIFT)
5328
-#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT 20
5329
-#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT)
5330
698
 #endif /* _I40E_REGISTER_H_ */