forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f 
 kernel/drivers/net/ethernet/intel/e1000e/ich8lan.c
....@@ -271,7 +271,7 @@
271271 		u16 count = 20;
272272 
273273 		do {
274
-			usleep_range(5000, 10000);
274
+			usleep_range(5000, 6000);
275275 		} while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
276276 
277277 		msleep(30);
....@@ -300,7 +300,9 @@
300300 	 * so forcibly disable it.
301301 	 */
302302 	hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
303
-	e1000_disable_ulp_lpt_lp(hw, true);
303
+	ret_val = e1000_disable_ulp_lpt_lp(hw, true);
304
+	if (ret_val)
305
+		e_warn("Failed to disable ULP\n");
304306 
305307 	ret_val = hw->phy.ops.acquire(hw);
306308 	if (ret_val) {
....@@ -316,6 +318,9 @@
316318 	case e1000_pch_lpt:
317319 	case e1000_pch_spt:
318320 	case e1000_pch_cnp:
321
+	case e1000_pch_tgp:
322
+	case e1000_pch_adp:
323
+	case e1000_pch_mtp:
319324 		if (e1000_phy_is_accessible_pchlan(hw))
320325 			break;
321326 
....@@ -332,12 +337,12 @@
332337 		 */
333338 		msleep(50);
334339 
335
-		/* fall-through */
340
+		fallthrough;
336341 	case e1000_pch2lan:
337342 		if (e1000_phy_is_accessible_pchlan(hw))
338343 			break;
339344 
340
-		/* fall-through */
345
+		fallthrough;
341346 	case e1000_pchlan:
342347 		if ((hw->mac.type == e1000_pchlan) &&
343348 		    (fwsm & E1000_ICH_FWSM_FW_VALID))
....@@ -405,7 +410,7 @@
405410 	/* Ungate automatic PHY configuration on non-managed 82579 */
406411 	if ((hw->mac.type == e1000_pch2lan) &&
407412 	    !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
408
-		usleep_range(10000, 20000);
413
+		usleep_range(10000, 11000);
409414 		e1000_gate_hw_phy_config_ich8lan(hw, false);
410415 	}
411416 
....@@ -453,11 +458,14 @@
453458 				return ret_val;
454459 			if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
455460 				break;
456
-			/* fall-through */
461
+			fallthrough;
457462 		case e1000_pch2lan:
458463 		case e1000_pch_lpt:
459464 		case e1000_pch_spt:
460465 		case e1000_pch_cnp:
466
+		case e1000_pch_tgp:
467
+		case e1000_pch_adp:
468
+		case e1000_pch_mtp:
461469 			/* In case the PHY needs to be in mdio slow mode,
462470 			 * set slow mode and try to get the PHY id again.
463471 			 */
....@@ -531,7 +539,7 @@
531539 	phy->id = 0;
532540 	while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
533541 	       (i++ < 100)) {
534
-		usleep_range(1000, 2000);
542
+		usleep_range(1000, 1100);
535543 		ret_val = e1000e_get_phy_id(hw);
536544 		if (ret_val)
537545 			return ret_val;
....@@ -696,10 +704,13 @@
696704 	case e1000_pch2lan:
697705 		mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
698706 		mac->ops.rar_set = e1000_rar_set_pch2lan;
699
-		/* fall-through */
707
+		fallthrough;
700708 	case e1000_pch_lpt:
701709 	case e1000_pch_spt:
702710 	case e1000_pch_cnp:
711
+	case e1000_pch_tgp:
712
+	case e1000_pch_adp:
713
+	case e1000_pch_mtp:
703714 	case e1000_pchlan:
704715 		/* check management mode */
705716 		mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
....@@ -735,7 +746,7 @@
735746 /**
736747  *  __e1000_access_emi_reg_locked - Read/write EMI register
737748  *  @hw: pointer to the HW structure
738
- *  @addr: EMI address to program
749
+ *  @address: EMI address to program
739750  *  @data: pointer to value to read/write from/to the EMI address
740751  *  @read: boolean flag to indicate read or write
741752  *
....@@ -995,8 +1006,8 @@
9951006 {
9961007 	u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
9971008 	    link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
998
-	u16 max_ltr_enc_d = 0;	/* maximum LTR decoded by platform */
999
-	u16 lat_enc_d = 0;	/* latency decoded */
1009
+	u32 max_ltr_enc_d = 0;	/* maximum LTR decoded by platform */
1010
+	u32 lat_enc_d = 0;	/* latency decoded */
10001011 	u16 lat_enc = 0;	/* latency encoded */
10011012 
10021013 	if (link) {
....@@ -1241,6 +1252,9 @@
12411252 		return 0;
12421253 
12431254 	if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1255
+		struct e1000_adapter *adapter = hw->adapter;
1256
+		bool firmware_bug = false;
1257
+
12441258 		if (force) {
12451259 			/* Request ME un-configure ULP mode in the PHY */
12461260 			mac_reg = er32(H2ME);
....@@ -1249,16 +1263,24 @@
12491263 			ew32(H2ME, mac_reg);
12501264 		}
12511265 
1252
-		/* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1266
+		/* Poll up to 2.5 seconds for ME to clear ULP_CFG_DONE.
1267
+		 * If this takes more than 1 second, show a warning indicating a
1268
+		 * firmware bug
1269
+		 */
12531270 		while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1254
-			if (i++ == 30) {
1271
+			if (i++ == 250) {
12551272 				ret_val = -E1000_ERR_PHY;
12561273 				goto out;
12571274 			}
1275
+			if (i > 100 && !firmware_bug)
1276
+				firmware_bug = true;
12581277 
1259
-			usleep_range(10000, 20000);
1278
+			usleep_range(10000, 11000);
12601279 		}
1261
-		e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1280
+		if (firmware_bug)
1281
+			e_warn("ULP_CONFIG_DONE took %dmsec.  This is a firmware bug\n", i * 10);
1282
+		else
1283
+			e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
12621284 
12631285 		if (force) {
12641286 			mac_reg = er32(H2ME);
....@@ -1561,7 +1583,7 @@
15611583 		ret_val = e1000_k1_workaround_lv(hw);
15621584 		if (ret_val)
15631585 			return ret_val;
1564
-		/* fall-thru */
1586
+		fallthrough;
15651587 	case e1000_pchlan:
15661588 		if (hw->phy.type == e1000_phy_82578) {
15671589 			ret_val = e1000_link_stall_workaround_hv(hw);
....@@ -1650,6 +1672,9 @@
16501672 	case e1000_pch_lpt:
16511673 	case e1000_pch_spt:
16521674 	case e1000_pch_cnp:
1675
+	case e1000_pch_tgp:
1676
+	case e1000_pch_adp:
1677
+	case e1000_pch_mtp:
16531678 		rc = e1000_init_phy_params_pchlan(hw);
16541679 		break;
16551680 	default:
....@@ -2021,7 +2046,7 @@
20212046 
20222047 	while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
20232048 	       (i++ < 30))
2024
-		usleep_range(10000, 20000);
2049
+		usleep_range(10000, 11000);
20252050 	return blocked ? E1000_BLK_PHY_RESET : 0;
20262051 }
20272052 
....@@ -2096,12 +2121,15 @@
20962121 			sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
20972122 			break;
20982123 		}
2099
-		/* Fall-thru */
2124
+		fallthrough;
21002125 	case e1000_pchlan:
21012126 	case e1000_pch2lan:
21022127 	case e1000_pch_lpt:
21032128 	case e1000_pch_spt:
21042129 	case e1000_pch_cnp:
2130
+	case e1000_pch_tgp:
2131
+	case e1000_pch_adp:
2132
+	case e1000_pch_mtp:
21052133 		sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
21062134 		break;
21072135 	default:
....@@ -2266,7 +2294,7 @@
22662294 /**
22672295  *  e1000_configure_k1_ich8lan - Configure K1 power state
22682296  *  @hw: pointer to the HW structure
2269
- *  @enable: K1 state to configure
2297
+ *  @k1_enable: K1 state to configure
22702298  *
22712299  *  Configure the K1 power state based on the provided parameter.
22722300  *  Assumes semaphore already acquired.
....@@ -2405,8 +2433,10 @@
24052433 }
24062434 
24072435 /**
2408
- *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2409
- *  done after every PHY reset.
2436
+ *  e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds
2437
+ *  @hw: pointer to the HW structure
2438
+ *
2439
+ *  A series of PHY workarounds to be done after every PHY reset.
24102440  **/
24112441 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
24122442 {
....@@ -2694,8 +2724,10 @@
26942724 }
26952725 
26962726 /**
2697
- *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2698
- *  done after every PHY reset.
2727
+ *  e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds
2728
+ *  @hw: pointer to the HW structure
2729
+ *
2730
+ *  A series of PHY workarounds to be done after every PHY reset.
26992731  **/
27002732 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
27012733 {
....@@ -2840,7 +2872,7 @@
28402872 		return 0;
28412873 
28422874 	/* Allow time for h/w to get to quiescent state after reset */
2843
-	usleep_range(10000, 20000);
2875
+	usleep_range(10000, 11000);
28442876 
28452877 	/* Perform any necessary post-reset workarounds */
28462878 	switch (hw->mac.type) {
....@@ -2876,7 +2908,7 @@
28762908 	if (hw->mac.type == e1000_pch2lan) {
28772909 		/* Ungate automatic PHY configuration on non-managed 82579 */
28782910 		if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2879
-			usleep_range(10000, 20000);
2911
+			usleep_range(10000, 11000);
28802912 			e1000_gate_hw_phy_config_ich8lan(hw, false);
28812913 		}
28822914 
....@@ -3139,6 +3171,9 @@
31393171 	switch (hw->mac.type) {
31403172 	case e1000_pch_spt:
31413173 	case e1000_pch_cnp:
3174
+	case e1000_pch_tgp:
3175
+	case e1000_pch_adp:
3176
+	case e1000_pch_mtp:
31423177 		bank1_offset = nvm->flash_bank_size;
31433178 		act_offset = E1000_ICH_NVM_SIG_WORD;
31443179 
....@@ -3185,7 +3220,7 @@
31853220 			return 0;
31863221 		}
31873222 		e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3188
-		/* fall-thru */
3223
+		fallthrough;
31893224 	default:
31903225 		/* set bank to 0 in case flash read fails */
31913226 		*bank = 0;
....@@ -3897,7 +3932,7 @@
38973932 	 */
38983933 	if (!ret_val) {
38993934 		nvm->ops.reload(hw);
3900
-		usleep_range(10000, 20000);
3935
+		usleep_range(10000, 11000);
39013936 	}
39023937 
39033938 out:
....@@ -4048,7 +4083,7 @@
40484083 	 */
40494084 	if (!ret_val) {
40504085 		nvm->ops.reload(hw);
4051
-		usleep_range(10000, 20000);
4086
+		usleep_range(10000, 11000);
40524087 	}
40534088 
40544089 out:
....@@ -4082,6 +4117,9 @@
40824117 	case e1000_pch_lpt:
40834118 	case e1000_pch_spt:
40844119 	case e1000_pch_cnp:
4120
+	case e1000_pch_tgp:
4121
+	case e1000_pch_adp:
4122
+	case e1000_pch_mtp:
40854123 		word = NVM_COMPAT;
40864124 		valid_csum_mask = NVM_COMPAT_VALID_CSUM;
40874125 		break;
....@@ -4096,13 +4134,17 @@
40964134 		return ret_val;
40974135 
40984136 	if (!(data & valid_csum_mask)) {
4099
-		data |= valid_csum_mask;
4100
-		ret_val = e1000_write_nvm(hw, word, 1, &data);
4101
-		if (ret_val)
4102
-			return ret_val;
4103
-		ret_val = e1000e_update_nvm_checksum(hw);
4104
-		if (ret_val)
4105
-			return ret_val;
4137
+		e_dbg("NVM Checksum valid bit not set\n");
4138
+
4139
+		if (hw->mac.type < e1000_pch_tgp) {
4140
+			data |= valid_csum_mask;
4141
+			ret_val = e1000_write_nvm(hw, word, 1, &data);
4142
+			if (ret_val)
4143
+				return ret_val;
4144
+			ret_val = e1000e_update_nvm_checksum(hw);
4145
+			if (ret_val)
4146
+				return ret_val;
4147
+		}
41064148 	}
41074149 
41084150 	return e1000e_validate_nvm_checksum_generic(hw);
....@@ -4672,7 +4714,7 @@
46724714 	ew32(TCTL, E1000_TCTL_PSP);
46734715 	e1e_flush();
46744716 
4675
-	usleep_range(10000, 20000);
4717
+	usleep_range(10000, 11000);
46764718 
46774719 	/* Workaround for ICH8 bit corruption issue in FIFO memory */
46784720 	if (hw->mac.type == e1000_ich8lan) {
....@@ -4769,7 +4811,7 @@
47694811 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
47704812 {
47714813 	struct e1000_mac_info *mac = &hw->mac;
4772
-	u32 ctrl_ext, txdctl, snoop;
4814
+	u32 ctrl_ext, txdctl, snoop, fflt_dbg;
47734815 	s32 ret_val;
47744816 	u16 i;
47754817 
....@@ -4827,6 +4869,15 @@
48274869 	else
48284870 		snoop = (u32)~(PCIE_NO_SNOOP_ALL);
48294871 	e1000e_set_pcie_no_snoop(hw, snoop);
4872
+
4873
+	/* Enable workaround for packet loss issue on TGP PCH
4874
+	 * Do not gate DMA clock from the modPHY block
4875
+	 */
4876
+	if (mac->type >= e1000_pch_tgp) {
4877
+		fflt_dbg = er32(FFLT_DBG);
4878
+		fflt_dbg |= E1000_FFLT_DBG_DONT_GATE_WAKE_DMA_CLK;
4879
+		ew32(FFLT_DBG, fflt_dbg);
4880
+	}
48304881 
48314882 	ctrl_ext = er32(CTRL_EXT);
48324883 	ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
....@@ -5948,3 +5999,23 @@
59485999 	.phy_ops		= &ich8_phy_ops,
59496000 	.nvm_ops		= &spt_nvm_ops,
59506001 };
6002
+
6003
+const struct e1000_info e1000_pch_tgp_info = {
6004
+	.mac			= e1000_pch_tgp,
6005
+	.flags			= FLAG_IS_ICH
6006
+				  | FLAG_HAS_WOL
6007
+				  | FLAG_HAS_HW_TIMESTAMP
6008
+				  | FLAG_HAS_CTRLEXT_ON_LOAD
6009
+				  | FLAG_HAS_AMT
6010
+				  | FLAG_HAS_FLASH
6011
+				  | FLAG_HAS_JUMBO_FRAMES
6012
+				  | FLAG_APME_IN_WUC,
6013
+	.flags2			= FLAG2_HAS_PHY_STATS
6014
+				  | FLAG2_HAS_EEE,
6015
+	.pba			= 26,
6016
+	.max_hw_frame_size	= 9022,
6017
+	.get_variants		= e1000_get_variants_ich8lan,
6018
+	.mac_ops		= &ich8_mac_ops,
6019
+	.phy_ops		= &ich8_phy_ops,
6020
+	.nvm_ops		= &spt_nvm_ops,
6021
+};