.. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | 3 | * Huawei HiNIC PCI Express Linux driver |
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3 | 4 | * Copyright(c) 2017 Huawei Technologies Co., Ltd |
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4 | | - * |
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5 | | - * This program is free software; you can redistribute it and/or modify it |
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6 | | - * under the terms and conditions of the GNU General Public License, |
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7 | | - * version 2, as published by the Free Software Foundation. |
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8 | | - * |
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9 | | - * This program is distributed in the hope it will be useful, but WITHOUT |
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10 | | - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 | | - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 | | - * for more details. |
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13 | | - * |
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14 | 5 | */ |
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15 | 6 | |
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16 | 7 | #include <linux/kernel.h> |
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.. | .. |
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27 | 18 | #include <linux/dma-mapping.h> |
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28 | 19 | #include <linux/prefetch.h> |
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29 | 20 | #include <linux/cpumask.h> |
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| 21 | +#include <linux/if_vlan.h> |
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30 | 22 | #include <asm/barrier.h> |
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31 | 23 | |
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32 | 24 | #include "hinic_common.h" |
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.. | .. |
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43 | 35 | #define RX_IRQ_NO_LLI_TIMER 0 |
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44 | 36 | #define RX_IRQ_NO_CREDIT 0 |
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45 | 37 | #define RX_IRQ_NO_RESEND_TIMER 0 |
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| 38 | +#define HINIC_RX_BUFFER_WRITE 16 |
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| 39 | + |
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| 40 | +#define HINIC_RX_IPV6_PKT 7 |
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| 41 | +#define LRO_PKT_HDR_LEN_IPV4 66 |
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| 42 | +#define LRO_PKT_HDR_LEN_IPV6 86 |
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| 43 | +#define LRO_REPLENISH_THLD 256 |
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| 44 | + |
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| 45 | +#define LRO_PKT_HDR_LEN(cqe) \ |
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| 46 | + (HINIC_GET_RX_PKT_TYPE(be32_to_cpu((cqe)->offload_type)) == \ |
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| 47 | + HINIC_RX_IPV6_PKT ? LRO_PKT_HDR_LEN_IPV6 : LRO_PKT_HDR_LEN_IPV4) |
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46 | 48 | |
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47 | 49 | /** |
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48 | 50 | * hinic_rxq_clean_stats - Clean the statistics of specific queue |
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.. | .. |
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55 | 57 | u64_stats_update_begin(&rxq_stats->syncp); |
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56 | 58 | rxq_stats->pkts = 0; |
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57 | 59 | rxq_stats->bytes = 0; |
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| 60 | + rxq_stats->errors = 0; |
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| 61 | + rxq_stats->csum_errors = 0; |
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| 62 | + rxq_stats->other_errors = 0; |
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58 | 63 | u64_stats_update_end(&rxq_stats->syncp); |
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59 | 64 | } |
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60 | 65 | |
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.. | .. |
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68 | 73 | struct hinic_rxq_stats *rxq_stats = &rxq->rxq_stats; |
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69 | 74 | unsigned int start; |
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70 | 75 | |
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71 | | - u64_stats_update_begin(&stats->syncp); |
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72 | 76 | do { |
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73 | | - start = u64_stats_fetch_begin(&rxq_stats->syncp); |
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| 77 | + start = u64_stats_fetch_begin_irq(&rxq_stats->syncp); |
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74 | 78 | stats->pkts = rxq_stats->pkts; |
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75 | 79 | stats->bytes = rxq_stats->bytes; |
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76 | | - } while (u64_stats_fetch_retry(&rxq_stats->syncp, start)); |
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77 | | - u64_stats_update_end(&stats->syncp); |
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| 80 | + stats->errors = rxq_stats->csum_errors + |
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| 81 | + rxq_stats->other_errors; |
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| 82 | + stats->csum_errors = rxq_stats->csum_errors; |
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| 83 | + stats->other_errors = rxq_stats->other_errors; |
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| 84 | + } while (u64_stats_fetch_retry_irq(&rxq_stats->syncp, start)); |
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78 | 85 | } |
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79 | 86 | |
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80 | 87 | /** |
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.. | .. |
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89 | 96 | hinic_rxq_clean_stats(rxq); |
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90 | 97 | } |
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91 | 98 | |
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| 99 | +static void rx_csum(struct hinic_rxq *rxq, u32 status, |
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| 100 | + struct sk_buff *skb) |
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| 101 | +{ |
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| 102 | + struct net_device *netdev = rxq->netdev; |
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| 103 | + u32 csum_err; |
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| 104 | + |
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| 105 | + csum_err = HINIC_RQ_CQE_STATUS_GET(status, CSUM_ERR); |
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| 106 | + |
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| 107 | + if (!(netdev->features & NETIF_F_RXCSUM)) |
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| 108 | + return; |
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| 109 | + |
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| 110 | + if (!csum_err) { |
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| 111 | + skb->ip_summed = CHECKSUM_UNNECESSARY; |
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| 112 | + } else { |
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| 113 | + if (!(csum_err & (HINIC_RX_CSUM_HW_CHECK_NONE | |
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| 114 | + HINIC_RX_CSUM_IPSU_OTHER_ERR))) |
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| 115 | + rxq->rxq_stats.csum_errors++; |
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| 116 | + skb->ip_summed = CHECKSUM_NONE; |
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| 117 | + } |
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| 118 | +} |
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92 | 119 | /** |
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93 | 120 | * rx_alloc_skb - allocate skb and map it to dma address |
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94 | 121 | * @rxq: rx queue |
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.. | .. |
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207 | 234 | wmb(); /* write all the wqes before update PI */ |
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208 | 235 | |
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209 | 236 | hinic_rq_update(rxq->rq, prod_idx); |
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210 | | - tasklet_schedule(&rxq->rx_task); |
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211 | 237 | } |
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212 | 238 | |
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213 | 239 | return i; |
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.. | .. |
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234 | 260 | |
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235 | 261 | rx_free_skb(rxq, rq->saved_skb[ci], hinic_sge_to_dma(&sge)); |
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236 | 262 | } |
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237 | | -} |
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238 | | - |
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239 | | -/** |
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240 | | - * rx_alloc_task - tasklet for queue allocation |
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241 | | - * @data: rx queue |
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242 | | - **/ |
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243 | | -static void rx_alloc_task(unsigned long data) |
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244 | | -{ |
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245 | | - struct hinic_rxq *rxq = (struct hinic_rxq *)data; |
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246 | | - |
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247 | | - (void)rx_alloc_pkts(rxq); |
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248 | 263 | } |
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249 | 264 | |
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250 | 265 | /** |
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.. | .. |
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299 | 314 | return num_wqes; |
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300 | 315 | } |
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301 | 316 | |
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| 317 | +static void hinic_copy_lp_data(struct hinic_dev *nic_dev, |
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| 318 | + struct sk_buff *skb) |
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| 319 | +{ |
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| 320 | + struct net_device *netdev = nic_dev->netdev; |
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| 321 | + u8 *lb_buf = nic_dev->lb_test_rx_buf; |
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| 322 | + int lb_len = nic_dev->lb_pkt_len; |
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| 323 | + int pkt_offset, frag_len, i; |
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| 324 | + void *frag_data = NULL; |
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| 325 | + |
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| 326 | + if (nic_dev->lb_test_rx_idx == LP_PKT_CNT) { |
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| 327 | + nic_dev->lb_test_rx_idx = 0; |
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| 328 | + netif_warn(nic_dev, drv, netdev, "Loopback test warning, receive too more test pkts\n"); |
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| 329 | + } |
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| 330 | + |
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| 331 | + if (skb->len != nic_dev->lb_pkt_len) { |
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| 332 | + netif_warn(nic_dev, drv, netdev, "Wrong packet length\n"); |
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| 333 | + nic_dev->lb_test_rx_idx++; |
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| 334 | + return; |
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| 335 | + } |
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| 336 | + |
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| 337 | + pkt_offset = nic_dev->lb_test_rx_idx * lb_len; |
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| 338 | + frag_len = (int)skb_headlen(skb); |
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| 339 | + memcpy(lb_buf + pkt_offset, skb->data, frag_len); |
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| 340 | + pkt_offset += frag_len; |
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| 341 | + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { |
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| 342 | + frag_data = skb_frag_address(&skb_shinfo(skb)->frags[i]); |
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| 343 | + frag_len = (int)skb_frag_size(&skb_shinfo(skb)->frags[i]); |
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| 344 | + memcpy((lb_buf + pkt_offset), frag_data, frag_len); |
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| 345 | + pkt_offset += frag_len; |
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| 346 | + } |
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| 347 | + nic_dev->lb_test_rx_idx++; |
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| 348 | +} |
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| 349 | + |
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302 | 350 | /** |
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303 | 351 | * rxq_recv - Rx handler |
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304 | 352 | * @rxq: rx queue |
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.. | .. |
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309 | 357 | static int rxq_recv(struct hinic_rxq *rxq, int budget) |
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310 | 358 | { |
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311 | 359 | struct hinic_qp *qp = container_of(rxq->rq, struct hinic_qp, rq); |
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| 360 | + struct net_device *netdev = rxq->netdev; |
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312 | 361 | u64 pkt_len = 0, rx_bytes = 0; |
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| 362 | + struct hinic_rq *rq = rxq->rq; |
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313 | 363 | struct hinic_rq_wqe *rq_wqe; |
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| 364 | + struct hinic_dev *nic_dev; |
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| 365 | + unsigned int free_wqebbs; |
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| 366 | + struct hinic_rq_cqe *cqe; |
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314 | 367 | int num_wqes, pkts = 0; |
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315 | 368 | struct hinic_sge sge; |
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| 369 | + unsigned int status; |
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316 | 370 | struct sk_buff *skb; |
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317 | | - u16 ci; |
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| 371 | + u32 offload_type; |
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| 372 | + u16 ci, num_lro; |
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| 373 | + u16 num_wqe = 0; |
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| 374 | + u32 vlan_len; |
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| 375 | + u16 vid; |
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| 376 | + |
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| 377 | + nic_dev = netdev_priv(netdev); |
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318 | 378 | |
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319 | 379 | while (pkts < budget) { |
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320 | 380 | num_wqes = 0; |
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.. | .. |
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324 | 384 | if (!rq_wqe) |
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325 | 385 | break; |
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326 | 386 | |
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| 387 | + /* make sure we read rx_done before packet length */ |
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| 388 | + dma_rmb(); |
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| 389 | + |
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| 390 | + cqe = rq->cqe[ci]; |
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| 391 | + status = be32_to_cpu(cqe->status); |
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327 | 392 | hinic_rq_get_sge(rxq->rq, rq_wqe, ci, &sge); |
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328 | 393 | |
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329 | 394 | rx_unmap_skb(rxq, hinic_sge_to_dma(&sge)); |
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| 395 | + |
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| 396 | + rx_csum(rxq, status, skb); |
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330 | 397 | |
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331 | 398 | prefetch(skb->data); |
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332 | 399 | |
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.. | .. |
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340 | 407 | HINIC_RX_BUF_SZ, ci); |
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341 | 408 | } |
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342 | 409 | |
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343 | | - hinic_rq_put_wqe(rxq->rq, ci, |
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| 410 | + hinic_rq_put_wqe(rq, ci, |
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344 | 411 | (num_wqes + 1) * HINIC_RQ_WQE_SIZE); |
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| 412 | + |
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| 413 | + offload_type = be32_to_cpu(cqe->offload_type); |
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| 414 | + vlan_len = be32_to_cpu(cqe->len); |
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| 415 | + if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && |
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| 416 | + HINIC_GET_RX_VLAN_OFFLOAD_EN(offload_type)) { |
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| 417 | + vid = HINIC_GET_RX_VLAN_TAG(vlan_len); |
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| 418 | + __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); |
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| 419 | + } |
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| 420 | + |
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| 421 | + if (unlikely(nic_dev->flags & HINIC_LP_TEST)) |
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| 422 | + hinic_copy_lp_data(nic_dev, skb); |
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345 | 423 | |
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346 | 424 | skb_record_rx_queue(skb, qp->q_id); |
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347 | 425 | skb->protocol = eth_type_trans(skb, rxq->netdev); |
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.. | .. |
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350 | 428 | |
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351 | 429 | pkts++; |
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352 | 430 | rx_bytes += pkt_len; |
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| 431 | + |
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| 432 | + num_lro = HINIC_GET_RX_NUM_LRO(status); |
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| 433 | + if (num_lro) { |
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| 434 | + rx_bytes += ((num_lro - 1) * |
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| 435 | + LRO_PKT_HDR_LEN(cqe)); |
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| 436 | + |
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| 437 | + num_wqe += |
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| 438 | + (u16)(pkt_len >> rxq->rx_buff_shift) + |
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| 439 | + ((pkt_len & (rxq->buf_len - 1)) ? 1 : 0); |
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| 440 | + } |
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| 441 | + |
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| 442 | + cqe->status = 0; |
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| 443 | + |
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| 444 | + if (num_wqe >= LRO_REPLENISH_THLD) |
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| 445 | + break; |
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353 | 446 | } |
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354 | 447 | |
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355 | | - if (pkts) |
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356 | | - tasklet_schedule(&rxq->rx_task); /* rx_alloc_pkts */ |
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| 448 | + free_wqebbs = hinic_get_rq_free_wqebbs(rxq->rq); |
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| 449 | + if (free_wqebbs > HINIC_RX_BUFFER_WRITE) |
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| 450 | + rx_alloc_pkts(rxq); |
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357 | 451 | |
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358 | 452 | u64_stats_update_begin(&rxq->rxq_stats.syncp); |
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359 | 453 | rxq->rxq_stats.pkts += pkts; |
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.. | .. |
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366 | 460 | static int rx_poll(struct napi_struct *napi, int budget) |
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367 | 461 | { |
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368 | 462 | struct hinic_rxq *rxq = container_of(napi, struct hinic_rxq, napi); |
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| 463 | + struct hinic_dev *nic_dev = netdev_priv(rxq->netdev); |
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369 | 464 | struct hinic_rq *rq = rxq->rq; |
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370 | 465 | int pkts; |
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371 | 466 | |
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.. | .. |
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374 | 469 | return budget; |
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375 | 470 | |
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376 | 471 | napi_complete(napi); |
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377 | | - enable_irq(rq->irq); |
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| 472 | + |
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| 473 | + if (!HINIC_IS_VF(nic_dev->hwdev->hwif)) |
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| 474 | + hinic_hwdev_set_msix_state(nic_dev->hwdev, |
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| 475 | + rq->msix_entry, |
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| 476 | + HINIC_MSIX_ENABLE); |
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| 477 | + |
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378 | 478 | return pkts; |
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379 | 479 | } |
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380 | 480 | |
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.. | .. |
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399 | 499 | struct hinic_dev *nic_dev; |
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400 | 500 | |
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401 | 501 | /* Disable the interrupt until napi will be completed */ |
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402 | | - disable_irq_nosync(rq->irq); |
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| 502 | + nic_dev = netdev_priv(rxq->netdev); |
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| 503 | + if (!HINIC_IS_VF(nic_dev->hwdev->hwif)) |
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| 504 | + hinic_hwdev_set_msix_state(nic_dev->hwdev, |
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| 505 | + rq->msix_entry, |
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| 506 | + HINIC_MSIX_DISABLE); |
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403 | 507 | |
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404 | 508 | nic_dev = netdev_priv(rxq->netdev); |
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405 | 509 | hinic_hwdev_msix_cnt_set(nic_dev->hwdev, rq->msix_entry); |
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.. | .. |
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411 | 515 | static int rx_request_irq(struct hinic_rxq *rxq) |
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412 | 516 | { |
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413 | 517 | struct hinic_dev *nic_dev = netdev_priv(rxq->netdev); |
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| 518 | + struct hinic_msix_config interrupt_info = {0}; |
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| 519 | + struct hinic_intr_coal_info *intr_coal = NULL; |
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414 | 520 | struct hinic_hwdev *hwdev = nic_dev->hwdev; |
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415 | 521 | struct hinic_rq *rq = rxq->rq; |
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416 | 522 | struct hinic_qp *qp; |
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417 | 523 | int err; |
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| 524 | + |
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| 525 | + qp = container_of(rq, struct hinic_qp, rq); |
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418 | 526 | |
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419 | 527 | rx_add_napi(rxq); |
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420 | 528 | |
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.. | .. |
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423 | 531 | RX_IRQ_NO_LLI_TIMER, RX_IRQ_NO_CREDIT, |
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424 | 532 | RX_IRQ_NO_RESEND_TIMER); |
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425 | 533 | |
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426 | | - err = request_irq(rq->irq, rx_irq, 0, rxq->irq_name, rxq); |
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| 534 | + intr_coal = &nic_dev->rx_intr_coalesce[qp->q_id]; |
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| 535 | + interrupt_info.msix_index = rq->msix_entry; |
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| 536 | + interrupt_info.coalesce_timer_cnt = intr_coal->coalesce_timer_cfg; |
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| 537 | + interrupt_info.pending_cnt = intr_coal->pending_limt; |
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| 538 | + interrupt_info.resend_timer_cnt = intr_coal->resend_timer_cfg; |
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| 539 | + |
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| 540 | + err = hinic_set_interrupt_cfg(hwdev, &interrupt_info); |
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427 | 541 | if (err) { |
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428 | | - rx_del_napi(rxq); |
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429 | | - return err; |
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| 542 | + netif_err(nic_dev, drv, rxq->netdev, |
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| 543 | + "Failed to set RX interrupt coalescing attribute\n"); |
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| 544 | + goto err_req_irq; |
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430 | 545 | } |
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431 | 546 | |
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432 | | - qp = container_of(rq, struct hinic_qp, rq); |
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| 547 | + err = request_irq(rq->irq, rx_irq, 0, rxq->irq_name, rxq); |
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| 548 | + if (err) |
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| 549 | + goto err_req_irq; |
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| 550 | + |
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433 | 551 | cpumask_set_cpu(qp->q_id % num_online_cpus(), &rq->affinity_mask); |
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434 | | - return irq_set_affinity_hint(rq->irq, &rq->affinity_mask); |
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| 552 | + err = irq_set_affinity_hint(rq->irq, &rq->affinity_mask); |
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| 553 | + if (err) |
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| 554 | + goto err_irq_affinity; |
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| 555 | + |
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| 556 | + return 0; |
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| 557 | + |
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| 558 | +err_irq_affinity: |
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| 559 | + free_irq(rq->irq, rxq); |
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| 560 | +err_req_irq: |
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| 561 | + rx_del_napi(rxq); |
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| 562 | + return err; |
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435 | 563 | } |
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436 | 564 | |
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437 | 565 | static void rx_free_irq(struct hinic_rxq *rxq) |
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.. | .. |
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455 | 583 | struct net_device *netdev) |
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456 | 584 | { |
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457 | 585 | struct hinic_qp *qp = container_of(rq, struct hinic_qp, rq); |
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458 | | - int err, pkts, irqname_len; |
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| 586 | + int err, pkts; |
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459 | 587 | |
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460 | 588 | rxq->netdev = netdev; |
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461 | 589 | rxq->rq = rq; |
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| 590 | + rxq->buf_len = HINIC_RX_BUF_SZ; |
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| 591 | + rxq->rx_buff_shift = ilog2(HINIC_RX_BUF_SZ); |
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462 | 592 | |
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463 | 593 | rxq_stats_init(rxq); |
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464 | 594 | |
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465 | | - irqname_len = snprintf(NULL, 0, "hinic_rxq%d", qp->q_id) + 1; |
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466 | | - rxq->irq_name = devm_kzalloc(&netdev->dev, irqname_len, GFP_KERNEL); |
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| 595 | + rxq->irq_name = devm_kasprintf(&netdev->dev, GFP_KERNEL, |
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| 596 | + "%s_rxq%d", netdev->name, qp->q_id); |
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467 | 597 | if (!rxq->irq_name) |
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468 | 598 | return -ENOMEM; |
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469 | | - |
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470 | | - sprintf(rxq->irq_name, "hinic_rxq%d", qp->q_id); |
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471 | | - |
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472 | | - tasklet_init(&rxq->rx_task, rx_alloc_task, (unsigned long)rxq); |
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473 | 599 | |
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474 | 600 | pkts = rx_alloc_pkts(rxq); |
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475 | 601 | if (!pkts) { |
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.. | .. |
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487 | 613 | |
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488 | 614 | err_req_rx_irq: |
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489 | 615 | err_rx_pkts: |
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490 | | - tasklet_kill(&rxq->rx_task); |
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491 | 616 | free_all_rx_skbs(rxq); |
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492 | 617 | devm_kfree(&netdev->dev, rxq->irq_name); |
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493 | 618 | return err; |
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.. | .. |
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503 | 628 | |
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504 | 629 | rx_free_irq(rxq); |
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505 | 630 | |
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506 | | - tasklet_kill(&rxq->rx_task); |
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507 | 631 | free_all_rx_skbs(rxq); |
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508 | 632 | devm_kfree(&netdev->dev, rxq->irq_name); |
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509 | 633 | } |
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