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2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f 
 kernel/drivers/mmc/host/sunxi-mmc.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Driver for sunxi SD/MMC host controllers
34  * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
....@@ -6,11 +7,6 @@
67  * (C) Copyright 2013-2014 David Lanzendörfer <david.lanzendoerfer@o2s.ch>
78  * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
89  * (C) Copyright 2017 Sootech SA
9
- *
10
- * This program is free software; you can redistribute it and/or
11
- * modify it under the terms of the GNU General Public License as
12
- * published by the Free Software Foundation; either version 2 of
13
- * the License, or (at your option) any later version.
1410  */
1511 
1612 #include <linux/clk.h>
....@@ -19,7 +15,6 @@
1915 #include <linux/device.h>
2016 #include <linux/dma-mapping.h>
2117 #include <linux/err.h>
22
-#include <linux/gpio.h>
2318 #include <linux/interrupt.h>
2419 #include <linux/io.h>
2520 #include <linux/kernel.h>
....@@ -32,7 +27,6 @@
3227 #include <linux/mmc/slot-gpio.h>
3328 #include <linux/module.h>
3429 #include <linux/of_address.h>
35
-#include <linux/of_gpio.h>
3630 #include <linux/of_platform.h>
3731 #include <linux/platform_device.h>
3832 #include <linux/pm_runtime.h>
....@@ -258,11 +252,16 @@
258252 	/* Does DATA0 needs to be masked while the clock is updated */
259253 	bool mask_data0;
260254 
261
-	/* hardware only supports new timing mode */
255
+	/*
256
+	 * hardware only supports new timing mode, either due to lack of
257
+	 * a mode switch in the clock controller, or the mmc controller
258
+	 * is permanently configured in the new timing mode, without the
259
+	 * NTSR mode switch.
260
+	 */
262261 	bool needs_new_timings;
263262 
264
-	/* hardware can switch between old and new timing modes */
265
-	bool has_timings_switch;
263
+	/* clock hardware can switch between old and new timing modes */
264
+	bool ccu_has_timings_switch;
266265 };
267266 
268267 struct sunxi_mmc_host {
....@@ -787,7 +786,7 @@
787786 		clock <<= 1;
788787 	}
789788 
790
-	if (host->use_new_timings && host->cfg->has_timings_switch) {
789
+	if (host->use_new_timings && host->cfg->ccu_has_timings_switch) {
791790 		ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
792791 		if (ret) {
793792 			dev_err(mmc_dev(mmc),
....@@ -822,6 +821,12 @@
822821 	/* update card clock rate to account for internal divider */
823822 	rate /= div;
824823 
824
+	/*
825
+	 * Configure the controller to use the new timing mode if needed.
826
+	 * On controllers that only support the new timing mode, such as
827
+	 * the eMMC controller on the A64, this register does not exist,
828
+	 * and any writes to it are ignored.
829
+	 */
825830 	if (host->use_new_timings) {
826831 		/* Don't touch the delay bits */
827832 		rval = mmc_readl(host, REG_SD_NTSR);
....@@ -946,9 +951,13 @@
946951 
947952 static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
948953 {
954
+	int ret;
955
+
949956 	/* vqmmc regulator is available */
950
-	if (!IS_ERR(mmc->supply.vqmmc))
951
-		return mmc_regulator_set_vqmmc(mmc, ios);
957
+	if (!IS_ERR(mmc->supply.vqmmc)) {
958
+		ret = mmc_regulator_set_vqmmc(mmc, ios);
959
+		return ret < 0 ? ret : 0;
960
+	}
952961 
953962 	/* no vqmmc regulator, assume fixed regulator at 3/3.3V */
954963 	if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
....@@ -1145,7 +1154,7 @@
11451154 	.idma_des_size_bits = 16,
11461155 	.clk_delays = sunxi_mmc_clk_delays,
11471156 	.can_calibrate = false,
1148
-	.has_timings_switch = true,
1157
+	.ccu_has_timings_switch = true,
11491158 };
11501159 
11511160 static const struct sunxi_mmc_cfg sun9i_a80_cfg = {
....@@ -1166,6 +1175,7 @@
11661175 	.idma_des_size_bits = 13,
11671176 	.clk_delays = NULL,
11681177 	.can_calibrate = true,
1178
+	.needs_new_timings = true,
11691179 };
11701180 
11711181 static const struct of_device_id sunxi_mmc_of_match[] = {
....@@ -1267,8 +1277,7 @@
12671277 	if (ret)
12681278 		return ret;
12691279 
1270
-	host->reg_base = devm_ioremap_resource(&pdev->dev,
1271
-			      platform_get_resource(pdev, IORESOURCE_MEM, 0));
1280
+	host->reg_base = devm_platform_ioremap_resource(pdev, 0);
12721281 	if (IS_ERR(host->reg_base))
12731282 		return PTR_ERR(host->reg_base);
12741283 
....@@ -1351,7 +1360,7 @@
13511360 		goto error_free_host;
13521361 	}
13531362 
1354
-	if (host->cfg->has_timings_switch) {
1363
+	if (host->cfg->ccu_has_timings_switch) {
13551364 		/*
13561365 		 * Supports both old and new timing modes.
13571366 		 * Try setting the clk to new timing mode.
....@@ -1385,9 +1394,18 @@
13851394 	mmc->f_min		=   400000;
13861395 	mmc->f_max		= 52000000;
13871396 	mmc->caps	       |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1388
-				  MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
1397
+				  MMC_CAP_SDIO_IRQ;
13891398 
1390
-	if (host->cfg->clk_delays || host->use_new_timings)
1399
+	/*
1400
+	 * Some H5 devices do not have signal traces precise enough to
1401
+	 * use HS DDR mode for their eMMC chips.
1402
+	 *
1403
+	 * We still enable HS DDR modes for all the other controller
1404
+	 * variants that support them.
1405
+	 */
1406
+	if ((host->cfg->clk_delays || host->use_new_timings) &&
1407
+	    !of_device_is_compatible(pdev->dev.of_node,
1408
+				     "allwinner,sun50i-h5-emmc"))
13911409 		mmc->caps      |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
13921410 
13931411 	ret = mmc_of_parse(mmc);