kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/drivers/mmc/host/cqhci.h
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@@ -1,13 +1,5 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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3
  */
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 #ifndef LINUX_MMC_CQHCI_H
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 #define LINUX_MMC_CQHCI_H
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@@ -30,10 +22,13 @@
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22
 
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 /* capabilities */
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 #define CQHCI_CAP			0x04
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+#define CQHCI_CAP_CS			0x10000000 /* Crypto Support */
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+
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 /* configuration */
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 #define CQHCI_CFG			0x08
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 #define CQHCI_DCMD			0x00001000
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 #define CQHCI_TASK_DESC_SZ		0x00000100
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+#define CQHCI_CRYPTO_GENERAL_ENABLE	0x00000002
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 #define CQHCI_ENABLE			0x00000001
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 /* control */
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@@ -47,8 +42,11 @@
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 #define CQHCI_IS_TCC			BIT(1)
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 #define CQHCI_IS_RED			BIT(2)
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 #define CQHCI_IS_TCL			BIT(3)
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+#define CQHCI_IS_GCE			BIT(4) /* General Crypto Error */
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+#define CQHCI_IS_ICCE			BIT(5) /* Invalid Crypto Config Error */
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47
 
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-#define CQHCI_IS_MASK (CQHCI_IS_TCC | CQHCI_IS_RED)
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+#define CQHCI_IS_MASK (CQHCI_IS_TCC | CQHCI_IS_RED | \
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+		       CQHCI_IS_GCE | CQHCI_IS_ICCE)
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 /* interrupt status enable */
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 #define CQHCI_ISTE			0x14
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@@ -86,8 +84,12 @@
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 /* task clear */
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 #define CQHCI_TCLR			0x38
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+/* task descriptor processing error */
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+#define CQHCI_TDPE			0x3c
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+
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 /* send status config 1 */
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 #define CQHCI_SSC1			0x40
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+#define CQHCI_SSC1_CBC_MASK		GENMASK(19, 16)
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 /* send status config 2 */
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 #define CQHCI_SSC2			0x44
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@@ -113,6 +115,10 @@
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 /* command response argument */
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 #define CQHCI_CRA			0x5C
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+
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+/* crypto capabilities */
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+#define CQHCI_CCAP			0x100
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+#define CQHCI_CRYPTOCAP			0x104
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 #define CQHCI_INT_ALL			0xF
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 #define CQHCI_IC_DEFAULT_ICCTH		31
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@@ -140,13 +146,73 @@
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 #define CQHCI_CMD_TIMING(x)		(((x) & 1) << 22)
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 #define CQHCI_RESP_TYPE(x)		(((x) & 0x3) << 23)
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+/* crypto task descriptor fields (for bits 64-127 of task descriptor) */
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+#define CQHCI_CRYPTO_ENABLE_BIT		(1ULL << 47)
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+#define CQHCI_CRYPTO_KEYSLOT(x)		((u64)(x) << 32)
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+
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 /* transfer descriptor fields */
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 #define CQHCI_DAT_LENGTH(x)		(((x) & 0xFFFF) << 16)
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 #define CQHCI_DAT_ADDR_LO(x)		(((x) & 0xFFFFFFFF) << 32)
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 #define CQHCI_DAT_ADDR_HI(x)		(((x) & 0xFFFFFFFF) << 0)
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+/* CCAP - Crypto Capability 100h */
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+union cqhci_crypto_capabilities {
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+	__le32 reg_val;
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+	struct {
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+		u8 num_crypto_cap;
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+		u8 config_count;
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+		u8 reserved;
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+		u8 config_array_ptr;
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+	};
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+};
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+
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+enum cqhci_crypto_key_size {
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+	CQHCI_CRYPTO_KEY_SIZE_INVALID	= 0,
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+	CQHCI_CRYPTO_KEY_SIZE_128	= 1,
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+	CQHCI_CRYPTO_KEY_SIZE_192	= 2,
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+	CQHCI_CRYPTO_KEY_SIZE_256	= 3,
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+	CQHCI_CRYPTO_KEY_SIZE_512	= 4,
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+};
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+
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+enum cqhci_crypto_alg {
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+	CQHCI_CRYPTO_ALG_AES_XTS		= 0,
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+	CQHCI_CRYPTO_ALG_BITLOCKER_AES_CBC	= 1,
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+	CQHCI_CRYPTO_ALG_AES_ECB		= 2,
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+	CQHCI_CRYPTO_ALG_ESSIV_AES_CBC		= 3,
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+};
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+
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+/* x-CRYPTOCAP - Crypto Capability X */
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+union cqhci_crypto_cap_entry {
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+	__le32 reg_val;
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+	struct {
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+		u8 algorithm_id;
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+		u8 sdus_mask; /* Supported data unit size mask */
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+		u8 key_size;
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+		u8 reserved;
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+	};
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+};
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+
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+#define CQHCI_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
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+#define CQHCI_CRYPTO_KEY_MAX_SIZE 64
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+/* x-CRYPTOCFG - Crypto Configuration X */
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+union cqhci_crypto_cfg_entry {
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+	__le32 reg_val[32];
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+	struct {
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+		u8 crypto_key[CQHCI_CRYPTO_KEY_MAX_SIZE];
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+		u8 data_unit_size;
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+		u8 crypto_cap_idx;
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+		u8 reserved_1;
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+		u8 config_enable;
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+		u8 reserved_multi_host;
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+		u8 reserved_2;
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+		u8 vsb[2];
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+		u8 reserved_3[56];
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+	};
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+};
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+
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 struct cqhci_host_ops;
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 struct mmc_host;
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+struct mmc_request;
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 struct cqhci_slot;
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 struct cqhci_host {
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@@ -202,6 +268,12 @@
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 	struct completion halt_comp;
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 	wait_queue_head_t wait_queue;
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 	struct cqhci_slot *slot;
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+
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+#ifdef CONFIG_MMC_CRYPTO
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+	union cqhci_crypto_capabilities crypto_capabilities;
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+	union cqhci_crypto_cap_entry *crypto_cap_array;
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+	u32 crypto_cfg_register;
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+#endif
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 };
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 struct cqhci_host_ops {
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@@ -210,6 +282,14 @@
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 	u32 (*read_l)(struct cqhci_host *host, int reg);
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 	void (*enable)(struct mmc_host *mmc);
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 	void (*disable)(struct mmc_host *mmc, bool recovery);
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+	void (*update_dcmd_desc)(struct mmc_host *mmc, struct mmc_request *mrq,
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+				 u64 *data);
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+	void (*pre_enable)(struct mmc_host *mmc);
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+	void (*post_disable)(struct mmc_host *mmc);
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+#ifdef CONFIG_MMC_CRYPTO
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+	int (*program_key)(struct cqhci_host *cq_host,
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+			   const union cqhci_crypto_cfg_entry *cfg, int slot);
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+#endif
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 };
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 static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg)
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@@ -234,7 +314,11 @@
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 		      int data_error);
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 int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc, bool dma64);
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 struct cqhci_host *cqhci_pltfm_init(struct platform_device *pdev);
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-int cqhci_suspend(struct mmc_host *mmc);
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+int cqhci_deactivate(struct mmc_host *mmc);
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+static inline int cqhci_suspend(struct mmc_host *mmc)
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+{
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+	return cqhci_deactivate(mmc);
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+}
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 int cqhci_resume(struct mmc_host *mmc);
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 #endif