kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/drivers/media/platform/rockchip/isp/regs.h
..
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@@ -1753,7 +1753,7 @@
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 static inline void mi_frame_end_int_enable(struct rkisp_stream *stream)
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 {
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 	struct rkisp_hw_dev *hw = stream->ispdev->hw_dev;
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-	void __iomem *base = !hw->is_unite ?
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+	void __iomem *base = hw->unite != ISP_UNITE_TWO ?
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 		hw->base_addr : hw->base_next_addr;
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 	void __iomem *addr = base + CIF_MI_IMSC;
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1759
 
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@@ -1763,7 +1763,7 @@
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 static inline void mi_frame_end_int_disable(struct rkisp_stream *stream)
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 {
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 	struct rkisp_hw_dev *hw = stream->ispdev->hw_dev;
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-	void __iomem *base = !hw->is_unite ?
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+	void __iomem *base = hw->unite != ISP_UNITE_TWO ?
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 		hw->base_addr : hw->base_next_addr;
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 	void __iomem *addr = base + CIF_MI_IMSC;
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@@ -1773,7 +1773,7 @@
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 static inline void mi_frame_end_int_clear(struct rkisp_stream *stream)
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 {
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 	struct rkisp_hw_dev *hw = stream->ispdev->hw_dev;
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-	void __iomem *base = !hw->is_unite ?
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+	void __iomem *base = hw->unite != ISP_UNITE_TWO ?
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 		hw->base_addr : hw->base_next_addr;
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 	void __iomem *addr = base + CIF_MI_ICR;
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1779
 
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@@ -1783,7 +1783,6 @@
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 static inline void stream_data_path(struct rkisp_stream *stream)
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 {
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 	struct rkisp_device *dev = stream->ispdev;
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-	bool is_unite = dev->hw_dev->is_unite;
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 	u32 dpcl = 0;
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 	if (stream->id == RKISP_STREAM_MP)
..
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@@ -1792,7 +1791,7 @@
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 		dpcl |= CIF_VI_DPCL_CHAN_MODE_SP;
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1792
 
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 	if (dpcl)
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-		rkisp_unite_set_bits(dev, CIF_VI_DPCL, 0, dpcl, true, is_unite);
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+		rkisp_unite_set_bits(dev, CIF_VI_DPCL, 0, dpcl, true);
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 }
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 static inline void mp_set_uv_swap(void __iomem *base)
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@@ -1914,16 +1913,15 @@
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 static inline void force_cfg_update(struct rkisp_device *dev)
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 {
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 	u32 val = CIF_MI_CTRL_INIT_OFFSET_EN | CIF_MI_CTRL_INIT_BASE_EN;
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-	bool is_unite = dev->hw_dev->is_unite;
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1916
 
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 	if (dev->isp_ver == ISP_V21) {
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 		val |= rkisp_read_reg_cache(dev, CIF_MI_CTRL);
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 		rkisp_write(dev, CIF_MI_CTRL, val, true);
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 	}
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 	dev->hw_dev->is_mi_update = true;
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-	rkisp_unite_set_bits(dev, CIF_MI_CTRL, 0, val, false, is_unite);
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+	rkisp_unite_set_bits(dev, CIF_MI_CTRL, 0, val, false);
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 	val = CIF_MI_INIT_SOFT_UPD;
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-	rkisp_unite_write(dev, CIF_MI_INIT, val, true, is_unite);
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+	rkisp_unite_write(dev, CIF_MI_INIT, val, true);
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 }
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 static inline void dmatx0_ctrl(void __iomem *base, u32 val)