kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/drivers/media/platform/rockchip/isp/capture_v30.c
..
..
@@ -332,7 +332,7 @@
332
332
 	if (dcrop->width == input_win->width &&
333
333
 	    dcrop->height == input_win->height &&
334
334
 	    dcrop->left == 0 && dcrop->top == 0 &&
335
-	    !dev->hw_dev->is_unite) {
335
+	    !dev->hw_dev->unite) {
336
336
 		rkisp_disable_dcrop(stream, async);
337
337
 		v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
338
338
 			 "stream %d crop disabled\n", stream->id);
..
..
@@ -472,7 +472,7 @@
472
472
 {
473
473
 	struct rkisp_device *dev = stream->ispdev;
474
474
 	struct v4l2_pix_format_mplane *out_fmt = &stream->out_fmt;
475
-	bool is_unite = dev->hw_dev->is_unite;
475
+	bool is_unite = !!dev->hw_dev->unite;
476
476
 	u32 val, mask;
477
477
 
478
478
        /*
..
..
@@ -480,26 +480,26 @@
480
480
 	* memory plane formats, so calculate the size explicitly.
481
481
 	*/
482
482
 	val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height;
483
-	rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false, is_unite);
483
+	rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false);
484
484
 
485
485
 	val = out_fmt->plane_fmt[1].sizeimage;
486
-	rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false, is_unite);
486
+	rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false);
487
487
 
488
488
 	val = out_fmt->plane_fmt[2].sizeimage;
489
-	rkisp_unite_write(dev, stream->config->mi.cr_size_init, val, false, is_unite);
489
+	rkisp_unite_write(dev, stream->config->mi.cr_size_init, val, false);
490
490
 
491
491
 	val = is_unite ? out_fmt->width / 2 : out_fmt->width;
492
-	rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_PIC_WIDTH, val, false, is_unite);
492
+	rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_PIC_WIDTH, val, false);
493
493
 
494
494
 	val = out_fmt->height;
495
-	rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_PIC_HEIGHT, val, false, is_unite);
495
+	rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_PIC_HEIGHT, val, false);
496
496
 
497
497
 	val = out_fmt->plane_fmt[0].bytesperline;
498
-	rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false, is_unite);
498
+	rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false);
499
499
 
500
500
 	val = stream->out_isp_fmt.uv_swap ? ISP3X_MI_XTD_FORMAT_MP_UV_SWAP : 0;
501
501
 	mask = ISP3X_MI_XTD_FORMAT_MP_UV_SWAP;
502
-	rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false, is_unite);
502
+	rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false);
503
503
 
504
504
 	mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_MP_YUV_MODE;
505
505
 	val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask;
..
..
@@ -511,13 +511,13 @@
511
511
 		val |= ISP3X_SEPERATE_YUV_CFG;
512
512
 	else
513
513
 		val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_MP_YUV_MODE;
514
-	rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false, is_unite);
514
+	rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false);
515
515
 
516
516
 	val = calc_burst_len(stream) | CIF_MI_CTRL_INIT_BASE_EN |
517
517
 		CIF_MI_CTRL_INIT_OFFSET_EN | CIF_MI_MP_AUTOUPDATE_ENABLE |
518
518
 		stream->out_isp_fmt.write_format;
519
519
 	mask = GENMASK(19, 16) | MI_CTRL_MP_FMT_MASK;
520
-	rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false, is_unite);
520
+	rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false);
521
521
 
522
522
 	mi_frame_end_int_enable(stream);
523
523
 	/* set up first buffer */
..
..
@@ -558,7 +558,7 @@
558
558
 	struct v4l2_pix_format_mplane *out_fmt = &stream->out_fmt;
559
559
 	struct ispsd_out_fmt *input_isp_fmt =
560
560
 			rkisp_get_ispsd_out_fmt(&dev->isp_sdev);
561
-	bool is_unite = dev->hw_dev->is_unite;
561
+	bool is_unite = !!dev->hw_dev->unite;
562
562
 	u32 sp_in_fmt, val, mask;
563
563
 
564
564
 	if (mbus_code_sp_in_fmt(input_isp_fmt->mbus_code,
..
..
@@ -572,26 +572,26 @@
572
572
 	* memory plane formats, so calculate the size explicitly.
573
573
 	*/
574
574
 	val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height;
575
-	rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false, is_unite);
575
+	rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false);
576
576
 
577
577
 	val = out_fmt->plane_fmt[1].sizeimage;
578
-	rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false, is_unite);
578
+	rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false);
579
579
 
580
580
 	val = out_fmt->plane_fmt[2].sizeimage;
581
-	rkisp_unite_write(dev, stream->config->mi.cr_size_init, val, false, is_unite);
581
+	rkisp_unite_write(dev, stream->config->mi.cr_size_init, val, false);
582
582
 
583
583
 	val = is_unite ? out_fmt->width / 2 : out_fmt->width;
584
-	rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_PIC_WIDTH, val, false, is_unite);
584
+	rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_PIC_WIDTH, val, false);
585
585
 
586
586
 	val = out_fmt->height;
587
-	rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_PIC_HEIGHT, val, false, is_unite);
587
+	rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_PIC_HEIGHT, val, false);
588
588
 
589
589
 	val = stream->u.sp.y_stride;
590
-	rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_LLENGTH, val, false, is_unite);
590
+	rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_LLENGTH, val, false);
591
591
 
592
592
 	val = stream->out_isp_fmt.uv_swap ? ISP3X_MI_XTD_FORMAT_SP_UV_SWAP : 0;
593
593
 	mask = ISP3X_MI_XTD_FORMAT_SP_UV_SWAP;
594
-	rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false, is_unite);
594
+	rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false);
595
595
 
596
596
 	mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_SP_YUV_MODE;
597
597
 	val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask;
..
..
@@ -603,14 +603,14 @@
603
603
 		val |= ISP3X_SEPERATE_YUV_CFG;
604
604
 	else
605
605
 		val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_SP_YUV_MODE;
606
-	rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false, is_unite);
606
+	rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false);
607
607
 
608
608
 	val = calc_burst_len(stream) | CIF_MI_CTRL_INIT_BASE_EN |
609
609
 		CIF_MI_CTRL_INIT_OFFSET_EN | stream->out_isp_fmt.write_format |
610
610
 		sp_in_fmt | stream->out_isp_fmt.output_format |
611
611
 		CIF_MI_SP_AUTOUPDATE_ENABLE;
612
612
 	mask = GENMASK(19, 16) | MI_CTRL_SP_FMT_MASK;
613
-	rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false, is_unite);
613
+	rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false);
614
614
 
615
615
 	mi_frame_end_int_enable(stream);
616
616
 	/* set up first buffer */
..
..
@@ -625,12 +625,12 @@
625
625
 	u32 h = ALIGN(stream->out_fmt.height, 16);
626
626
 	u32 w = ALIGN(stream->out_fmt.width, 16);
627
627
 	u32 offs = ALIGN(w * h / 16, RK_MPP_ALIGN);
628
-	bool is_unite = stream->ispdev->hw_dev->is_unite;
628
+	bool is_unite = !!stream->ispdev->hw_dev->unite;
629
629
 
630
630
 	rkisp_write(stream->ispdev, ISP3X_MPFBC_HEAD_OFFSET, offs, false);
631
-	rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_VIR_WIDTH, w, false, is_unite);
632
-	rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_PAYL_WIDTH, w, false, is_unite);
633
-	rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_VIR_HEIGHT, h, false, is_unite);
631
+	rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_VIR_WIDTH, w, false);
632
+	rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_PAYL_WIDTH, w, false);
633
+	rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_VIR_HEIGHT, h, false);
634
634
 	if (is_unite) {
635
635
 		u32 left_w = (stream->out_fmt.width / 2) & ~0xf;
636
636
 
..
..
@@ -638,8 +638,7 @@
638
638
 		rkisp_next_write(stream->ispdev, ISP3X_MPFBC_HEAD_OFFSET, offs, false);
639
639
 	}
640
640
 	rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, 0,
641
-			     CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN,
642
-			     false, is_unite);
641
+			     CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN, false);
643
642
 	mi_frame_end_int_enable(stream);
644
643
 	/* set up first buffer */
645
644
 	mi_frame_end(stream, FRAME_INIT);
..
..
@@ -650,7 +649,7 @@
650
649
 {
651
650
 	struct v4l2_pix_format_mplane *out_fmt = &stream->out_fmt;
652
651
 	struct rkisp_device *dev = stream->ispdev;
653
-	bool is_unite = dev->hw_dev->is_unite;
652
+	bool is_unite = dev->hw_dev->unite;
654
653
 	u32 val, mask;
655
654
 
656
655
        /*
..
..
@@ -658,19 +657,19 @@
658
657
 	* memory plane formats, so calculate the size explicitly.
659
658
 	*/
660
659
 	val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height;
661
-	rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false, is_unite);
660
+	rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false);
662
661
 
663
662
 	val = out_fmt->plane_fmt[1].sizeimage;
664
-	rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false, is_unite);
663
+	rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false);
665
664
 
666
665
 	val = is_unite ? out_fmt->width / 2 : out_fmt->width;
667
-	rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_PIC_WIDTH, val, false, is_unite);
666
+	rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_PIC_WIDTH, val, false);
668
667
 
669
668
 	val = out_fmt->height;
670
-	rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_PIC_HEIGHT, val, false, is_unite);
669
+	rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_PIC_HEIGHT, val, false);
671
670
 
672
671
 	val = out_fmt->plane_fmt[0].bytesperline;
673
-	rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_LLENGTH, val, false, is_unite);
672
+	rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_LLENGTH, val, false);
674
673
 
675
674
 	mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_BP_YUV_MODE;
676
675
 	val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask;
..
..
@@ -680,9 +679,9 @@
680
679
 		val |= ISP3X_SEPERATE_YUV_CFG;
681
680
 	else
682
681
 		val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_BP_YUV_MODE;
683
-	rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false, is_unite);
682
+	rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false);
684
683
 	val = CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN;
685
-	rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false, is_unite);
684
+	rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false);
686
685
 	mi_frame_end_int_enable(stream);
687
686
 	/* set up first buffer */
688
687
 	mi_frame_end(stream, FRAME_INIT);
..
..
@@ -697,8 +696,7 @@
697
696
 
698
697
 	if (isp_fmt->fmt_type == FMT_BAYER)
699
698
 		val = CIF_MI_CTRL_RAW_ENABLE;
700
-	rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val,
701
-			     false, stream->ispdev->hw_dev->is_unite);
699
+	rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false);
702
700
 }
703
701
 
704
702
 static void sp_enable_mi(struct rkisp_stream *stream)
..
..
@@ -711,21 +709,18 @@
711
709
 	if (fmt->fmt_type == FMT_RGB &&
712
710
 	    dev->isp_sdev.quantization == V4L2_QUANTIZATION_FULL_RANGE)
713
711
 		val |= mask;
714
-	rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL,
715
-			     mask, val, false,
716
-			     stream->ispdev->hw_dev->is_unite);
712
+	rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false);
717
713
 }
718
714
 
719
715
 static void fbc_enable_mi(struct rkisp_stream *stream)
720
716
 {
721
717
 	u32 val, mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_MPFBC_YUV_MASK |
722
718
 			ISP3X_MPFBC_SPARSE_MODE;
723
-	bool is_unite = stream->ispdev->hw_dev->is_unite;
724
719
 
725
720
 	/* config no effect immediately, read back is shadow, get config value from cache */
726
721
 	val = rkisp_read_reg_cache(stream->ispdev, ISP3X_MPFBC_CTRL) & ~mask;
727
722
 	val |= stream->out_isp_fmt.write_format | ISP3X_HEAD_OFFSET_EN | ISP3X_MPFBC_EN;
728
-	rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_CTRL, val, false, is_unite);
723
+	rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_CTRL, val, false);
729
724
 }
730
725
 
731
726
 static void bp_enable_mi(struct rkisp_stream *stream)
..
..
@@ -733,36 +728,31 @@
733
728
 	u32 val = stream->out_isp_fmt.write_format |
734
729
 		ISP3X_BP_ENABLE | ISP3X_BP_AUTO_UPD;
735
730
 
736
-	rkisp_unite_write(stream->ispdev, ISP3X_MI_BP_WR_CTRL, val, false,
737
-			  stream->ispdev->hw_dev->is_unite);
731
+	rkisp_unite_write(stream->ispdev, ISP3X_MI_BP_WR_CTRL, val, false);
738
732
 }
739
733
 
740
734
 static void mp_disable_mi(struct rkisp_stream *stream)
741
735
 {
742
736
 	u32 mask = CIF_MI_CTRL_MP_ENABLE | CIF_MI_CTRL_RAW_ENABLE;
743
737
 
744
-	rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, false,
745
-			       stream->ispdev->hw_dev->is_unite);
738
+	rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, false);
746
739
 }
747
740
 
748
741
 static void sp_disable_mi(struct rkisp_stream *stream)
749
742
 {
750
-	rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, CIF_MI_CTRL_SP_ENABLE,
751
-			       false, stream->ispdev->hw_dev->is_unite);
743
+	rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, CIF_MI_CTRL_SP_ENABLE, false);
752
744
 }
753
745
 
754
746
 static void fbc_disable_mi(struct rkisp_stream *stream)
755
747
 {
756
748
 	u32 mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_MPFBC_EN;
757
749
 
758
-	rkisp_unite_clear_bits(stream->ispdev, ISP3X_MPFBC_CTRL, mask,
759
-			       false, stream->ispdev->hw_dev->is_unite);
750
+	rkisp_unite_clear_bits(stream->ispdev, ISP3X_MPFBC_CTRL, mask, false);
760
751
 }
761
752
 
762
753
 static void bp_disable_mi(struct rkisp_stream *stream)
763
754
 {
764
-	rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_BP_WR_CTRL, ISP3X_BP_ENABLE,
765
-			       false, stream->ispdev->hw_dev->is_unite);
755
+	rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_BP_WR_CTRL, ISP3X_BP_ENABLE, false);
766
756
 }
767
757
 
768
758
 static void update_mi(struct rkisp_stream *stream)
..
..
@@ -786,24 +776,25 @@
786
776
 			rkisp_write(dev, reg, val, false);
787
777
 		}
788
778
 
789
-		if (dev->hw_dev->is_unite) {
779
+		if (dev->hw_dev->unite) {
790
780
 			u32 mult = stream->id != RKISP_STREAM_FBC ? 1 :
791
781
 				   (stream->out_isp_fmt.write_format ? 32 : 24);
782
+			u32 div = stream->out_isp_fmt.fourcc == V4L2_PIX_FMT_UYVY ? 1 : 2;
792
783
 
793
784
 			reg = stream->config->mi.y_base_ad_init;
794
785
 			val = stream->next_buf->buff_addr[RKISP_PLANE_Y];
795
-			val += ((stream->out_fmt.width / 2) & ~0xf);
786
+			val += ((stream->out_fmt.width / div) & ~0xf);
796
787
 			rkisp_next_write(dev, reg, val, false);
797
788
 
798
789
 			reg = stream->config->mi.cb_base_ad_init;
799
790
 			val = stream->next_buf->buff_addr[RKISP_PLANE_CB];
800
-			val += ((stream->out_fmt.width / 2) & ~0xf) * mult;
791
+			val += ((stream->out_fmt.width / div) & ~0xf) * mult;
801
792
 			rkisp_next_write(dev, reg, val, false);
802
793
 
803
794
 			if (stream->id != RKISP_STREAM_FBC && stream->id != RKISP_STREAM_BP) {
804
795
 				reg = stream->config->mi.cr_base_ad_init;
805
796
 				val = stream->next_buf->buff_addr[RKISP_PLANE_CR];
806
-				val += ((stream->out_fmt.width / 2) & ~0xf);
797
+				val += ((stream->out_fmt.width / div) & ~0xf);
807
798
 				rkisp_next_write(dev, reg, val, false);
808
799
 			}
809
800
 		}
..
..
@@ -817,22 +808,22 @@
817
808
 		stream->dbg.frameloss++;
818
809
 		val = dummy_buf->dma_addr;
819
810
 		reg = stream->config->mi.y_base_ad_init;
820
-		rkisp_unite_write(dev, reg, val, false, dev->hw_dev->is_unite);
811
+		rkisp_unite_write(dev, reg, val, false);
821
812
 		reg = stream->config->mi.cb_base_ad_init;
822
-		rkisp_unite_write(dev, reg, val, false, dev->hw_dev->is_unite);
813
+		rkisp_unite_write(dev, reg, val, false);
823
814
 		reg = stream->config->mi.cr_base_ad_init;
824
815
 		if (stream->id != RKISP_STREAM_FBC && stream->id != RKISP_STREAM_BP)
825
-			rkisp_unite_write(dev, reg, val, false, dev->hw_dev->is_unite);
816
+			rkisp_unite_write(dev, reg, val, false);
826
817
 	}
827
818
 
828
819
 	if (stream->id != RKISP_STREAM_FBC) {
829
820
 		reg = stream->config->mi.y_offs_cnt_init;
830
-		rkisp_unite_write(dev, reg, 0, false, dev->hw_dev->is_unite);
821
+		rkisp_unite_write(dev, reg, 0, false);
831
822
 		reg = stream->config->mi.cb_offs_cnt_init;
832
-		rkisp_unite_write(dev, reg, 0, false, dev->hw_dev->is_unite);
823
+		rkisp_unite_write(dev, reg, 0, false);
833
824
 		reg = stream->config->mi.cr_offs_cnt_init;
834
825
 		if (stream->id != RKISP_STREAM_BP)
835
-			rkisp_unite_write(dev, reg, 0, false, dev->hw_dev->is_unite);
826
+			rkisp_unite_write(dev, reg, 0, false);
836
827
 	}
837
828
 
838
829
 	v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
..
..
@@ -841,7 +832,7 @@
841
832
 		 rkisp_read(dev, stream->config->mi.y_base_ad_init, false),
842
833
 		 rkisp_read(dev, stream->config->mi.cb_base_ad_init, false),
843
834
 		 rkisp_read(dev, stream->config->mi.y_base_ad_shd, true));
844
-	if (dev->hw_dev->is_unite)
835
+	if (dev->hw_dev->unite)
845
836
 		v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
846
837
 			 "%s stream:%d Y:0x%x CB:0x%x | Y_SHD:0x%x, right\n",
847
838
 			 __func__, stream->id,
..
..
@@ -896,11 +887,10 @@
896
887
 {
897
888
 	struct rkisp_device *dev = stream->ispdev;
898
889
 	u32 val, mask = ISP3X_MPSELF_UPD | ISP3X_SPSELF_UPD | ISP3X_BPSELF_UPD;
899
-	bool is_unite = dev->hw_dev->is_unite;
900
890
 
901
891
 	if (stream->id == RKISP_STREAM_FBC) {
902
892
 		val = ISP3X_MPFBC_FORCE_UPD;
903
-		rkisp_unite_set_bits(dev, ISP3X_MPFBC_CTRL, 0, val, false, is_unite);
893
+		rkisp_unite_set_bits(dev, ISP3X_MPFBC_CTRL, 0, val, false);
904
894
 		return;
905
895
 	}
906
896
 
..
..
@@ -918,7 +908,7 @@
918
908
 		return;
919
909
 	}
920
910
 
921
-	rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL2, mask, val, false, is_unite);
911
+	rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL2, mask, val, false);
922
912
 }
923
913
 
924
914
 static int mi_frame_start(struct rkisp_stream *stream, u32 mis)
..
..
@@ -976,7 +966,10 @@
976
966
 		    (stream->frame_early && state == FRAME_IRQ))
977
967
 			goto end;
978
968
 	} else {
969
+		spin_lock_irqsave(&stream->vbq_lock, lock_flags);
979
970
 		buf = stream->curr_buf;
971
+		stream->curr_buf = NULL;
972
+		spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
980
973
 	}
981
974
 
982
975
 	if (buf) {
..
..
@@ -1686,7 +1679,7 @@
1686
1679
 	struct rkisp_stream *stream;
1687
1680
 	unsigned int i;
1688
1681
 
1689
-	if (dev->hw_dev->is_unite) {
1682
+	if (dev->hw_dev->unite) {
1690
1683
 		u32 val = rkisp_read(dev, ISP3X_MI_RIS, true);
1691
1684
 
1692
1685
 		if (val) {