~hc/RK356X_SDK_RELEASE.git

..	..	@@ -847,11 +847,13 @@
847	847	}
848	848
849	849	const struct
850		-cif_input_fmt get_input_fmt(struct v4l2_subdev sd, struct v4l2_rect *rect,
	850	+cif_input_fmt rkcif_get_input_fmt(struct rkcif_device dev, struct v4l2_rect *rect,
851	851	u32 pad_id, struct csi_channel_info *csi_info)
852	852	{
853	853	struct v4l2_subdev_format fmt;
	854	+ struct v4l2_subdev *sd = dev->terminal_sensor.sd;
854	855	struct rkmodule_channel_info ch_info = {0};
	856	+ struct rkmodule_capture_info capture_info;
855	857	int ret;
856	858	u32 i;
857	859
..	..	@@ -909,7 +911,26 @@
909	911	rect->top = 0;
910	912	rect->width = fmt.format.width;
911	913	rect->height = fmt.format.height;
912		-
	914	+ ret = v4l2_subdev_call(sd,
	915	+ core, ioctl,
	916	+ RKMODULE_GET_CAPTURE_MODE,
	917	+ &capture_info);
	918	+ if (!ret) {
	919	+ if (capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
	920	+ dev->hw_dev->is_rk3588s2) {
	921	+ for (i = 0; i < capture_info.multi_dev.dev_num; i++) {
	922	+ if (capture_info.multi_dev.dev_idx[i] == 0)
	923	+ capture_info.multi_dev.dev_idx[i] = 2;
	924	+ else if (capture_info.multi_dev.dev_idx[i] == 2)
	925	+ capture_info.multi_dev.dev_idx[i] = 4;
	926	+ else if (capture_info.multi_dev.dev_idx[i] == 3)
	927	+ capture_info.multi_dev.dev_idx[i] = 5;
	928	+ }
	929	+ }
	930	+ csi_info->capture_info = capture_info;
	931	+ } else {
	932	+ csi_info->capture_info.mode = RKMODULE_CAPTURE_MODE_NONE;
	933	+ }
913	934	for (i = 0; i < ARRAY_SIZE(in_fmts); i++)
914	935	if (fmt.format.code == in_fmts[i].mbus_code &&
915	936	fmt.format.field == in_fmts[i].field)
..	..	@@ -1594,7 +1615,7 @@
1594	1615	struct rkisp_rx_buf *dbufs;
1595	1616	struct rkcif_device *dev = stream->cifdev;
1596	1617
1597		- if (dev->sditf[0] && dev->sditf[0]->num_sensors != 0) {
	1618	+ if (dev->sditf[0] && dev->sditf[0]->sd.entity.num_links) {
1598	1619	if (dev->sditf[0]->is_combine_mode)
1599	1620	pad = media_entity_remote_pad(&dev->sditf[0]->pads[1]);
1600	1621	else
..	..	@@ -1670,6 +1691,20 @@
1670	1691	stream->skip_info.skip_en = false;
1671	1692	}
1672	1693
	1694	+static void rkcif_rdbk_with_tools(struct rkcif_stream *stream,
	1695	+ struct rkcif_rx_buffer *active_buf)
	1696	+{
	1697	+ unsigned long flags;
	1698	+
	1699	+ spin_lock_irqsave(&stream->tools_vdev->vbq_lock, flags);
	1700	+ if (stream->tools_vdev->state == RKCIF_STATE_STREAMING) {
	1701	+ list_add_tail(&active_buf->list, &stream->tools_vdev->buf_done_head);
	1702	+ if (!work_busy(&stream->tools_vdev->work))
	1703	+ schedule_work(&stream->tools_vdev->work);
	1704	+ }
	1705	+ spin_unlock_irqrestore(&stream->tools_vdev->vbq_lock, flags);
	1706	+}
	1707	+
1673	1708	static void rkcif_rdbk_frame_end_toisp(struct rkcif_stream *stream,
1674	1709	struct rkcif_rx_buffer *buffer)
1675	1710	{
..	..	@@ -1734,6 +1769,12 @@
1734	1769	rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_L]->dbufs);
1735	1770	rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_M]->dbufs);
1736	1771	rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_S]->dbufs);
	1772	+ rkcif_rdbk_with_tools(&dev->stream[RDBK_L], dev->rdbk_rx_buf[RDBK_L]);
	1773	+ rkcif_rdbk_with_tools(&dev->stream[RDBK_M], dev->rdbk_rx_buf[RDBK_M]);
	1774	+ rkcif_rdbk_with_tools(&dev->stream[RDBK_S], dev->rdbk_rx_buf[RDBK_S]);
	1775	+ atomic_dec(&dev->stream[RDBK_L].buf_cnt);
	1776	+ atomic_dec(&dev->stream[RDBK_M].buf_cnt);
	1777	+ atomic_dec(&dev->stream[RDBK_S].buf_cnt);
1737	1778	dev->rdbk_rx_buf[RDBK_L] = NULL;
1738	1779	dev->rdbk_rx_buf[RDBK_M] = NULL;
1739	1780	dev->rdbk_rx_buf[RDBK_S] = NULL;
..	..	@@ -1772,6 +1813,10 @@
1772	1813	dev->rdbk_rx_buf[RDBK_M]->dbufs.sequence = dev->rdbk_rx_buf[RDBK_L]->dbufs.sequence;
1773	1814	rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_L]->dbufs);
1774	1815	rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_M]->dbufs);
	1816	+ rkcif_rdbk_with_tools(&dev->stream[RDBK_L], dev->rdbk_rx_buf[RDBK_L]);
	1817	+ rkcif_rdbk_with_tools(&dev->stream[RDBK_M], dev->rdbk_rx_buf[RDBK_M]);
	1818	+ atomic_dec(&dev->stream[RDBK_L].buf_cnt);
	1819	+ atomic_dec(&dev->stream[RDBK_M].buf_cnt);
1775	1820	dev->rdbk_rx_buf[RDBK_L] = NULL;
1776	1821	dev->rdbk_rx_buf[RDBK_M] = NULL;
1777	1822	}
..	..	@@ -1783,14 +1828,51 @@
1783	1828	spin_unlock_irqrestore(&dev->hdr_lock, flags);
1784	1829	}
1785	1830
	1831	+static void rkcif_write_buff_addr_multi_dev_combine(struct rkcif_stream *stream,
	1832	+ u32 frm_addr_y, u32 frm_addr_uv,
	1833	+ u32 buff_addr_y, u32 buff_addr_cbcr,
	1834	+ bool is_dummy_buf)
	1835	+{
	1836	+ struct rkcif_device *dev = stream->cifdev;
	1837	+ struct rkmodule_capture_info *capture_info = &dev->channels[stream->id].capture_info;
	1838	+ u32 addr_y, addr_cbcr;
	1839	+ int addr_offset = 0;
	1840	+ int i = 0;
	1841	+ int tmp_host_index = dev->csi_host_idx;
	1842	+
	1843	+ for (i = 0; i < capture_info->multi_dev.dev_num; i++) {
	1844	+ if (is_dummy_buf) {
	1845	+ addr_y = buff_addr_y;
	1846	+ } else {
	1847	+ addr_offset = dev->channels[stream->id].left_virtual_width;
	1848	+ addr_y = buff_addr_y + addr_offset * i;
	1849	+ }
	1850	+ dev->csi_host_idx = capture_info->multi_dev.dev_idx[i];
	1851	+ rkcif_write_register(dev, frm_addr_y, addr_y);
	1852	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW &&
	1853	+ frm_addr_uv && buff_addr_cbcr) {
	1854	+ if (is_dummy_buf) {
	1855	+ addr_cbcr = buff_addr_cbcr;
	1856	+ } else {
	1857	+ addr_offset = dev->channels[stream->id].left_virtual_width;
	1858	+ addr_cbcr = buff_addr_cbcr + addr_offset * i;
	1859	+ }
	1860	+ rkcif_write_register(dev, frm_addr_uv, addr_cbcr);
	1861	+ }
	1862	+ }
	1863	+ dev->csi_host_idx = tmp_host_index;
	1864	+}
	1865	+
1786	1866	static void rkcif_assign_new_buffer_init_toisp(struct rkcif_stream *stream,
1787	1867	int channel_id)
1788	1868	{
1789	1869	struct rkcif_device *dev = stream->cifdev;
1790	1870	struct rkcif_rx_buffer *rx_buf;
1791	1871	struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	1872	+ struct rkmodule_capture_info *capture_info = &dev->channels[channel_id].capture_info;
1792	1873	u32 frm0_addr_y;
1793	1874	u32 frm1_addr_y;
	1875	+ u32 buff_addr_y;
1794	1876	unsigned long flags;
1795	1877
1796	1878	if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
..	..	@@ -1817,9 +1899,15 @@
1817	1899	}
1818	1900	}
1819	1901
1820		- if (stream->curr_buf_toisp)
1821		- rkcif_write_register(dev, frm0_addr_y,
1822		- stream->curr_buf_toisp->dummy.dma_addr);
	1902	+ if (stream->curr_buf_toisp) {
	1903	+ buff_addr_y = stream->curr_buf_toisp->dummy.dma_addr;
	1904	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	1905	+ rkcif_write_buff_addr_multi_dev_combine(stream, frm0_addr_y, 0,
	1906	+ buff_addr_y, 0, false);
	1907	+ } else {
	1908	+ rkcif_write_register(dev, frm0_addr_y, buff_addr_y);
	1909	+ }
	1910	+ }
1823	1911
1824	1912	if (!stream->next_buf_toisp) {
1825	1913	if (!list_empty(&stream->rx_buf_head)) {
..	..	@@ -1836,9 +1924,15 @@
1836	1924	}
1837	1925	}
1838	1926
1839		- if (stream->next_buf_toisp)
1840		- rkcif_write_register(dev, frm1_addr_y,
1841		- stream->next_buf_toisp->dummy.dma_addr);
	1927	+ if (stream->next_buf_toisp) {
	1928	+ buff_addr_y = stream->next_buf_toisp->dummy.dma_addr;
	1929	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	1930	+ rkcif_write_buff_addr_multi_dev_combine(stream, frm1_addr_y, 0,
	1931	+ buff_addr_y, 0, false);
	1932	+ } else {
	1933	+ rkcif_write_register(dev, frm1_addr_y, buff_addr_y);
	1934	+ }
	1935	+ }
1842	1936
1843	1937	spin_unlock_irqrestore(&stream->vbq_lock, flags);
1844	1938	stream->buf_owner = RKCIF_DMAEN_BY_ISP;
..	..	@@ -1849,10 +1943,11 @@
1849	1943	{
1850	1944	struct rkcif_device *dev = stream->cifdev;
1851	1945	struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	1946	+ struct rkmodule_capture_info *capture_info = &dev->channels[channel_id].capture_info;
1852	1947	struct rkcif_rx_buffer *buffer = NULL;
1853	1948	struct rkcif_rx_buffer *active_buf = NULL;
1854	1949	struct sditf_priv *priv = dev->sditf[0];
1855		- u32 frm_addr_y;
	1950	+ u32 frm_addr_y, buff_addr_y;
1856	1951	unsigned long flags;
1857	1952
1858	1953	if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
..	..	@@ -1889,14 +1984,18 @@
1889	1984	active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
1890	1985	active_buf->fe_timestamp = ktime_get_ns();
1891	1986	stream->last_frame_idx = stream->frame_idx;
1892		- if (dev->hdr.hdr_mode == NO_HDR)
	1987	+ if (dev->hdr.hdr_mode == NO_HDR) {
1893	1988	rkcif_s_rx_buffer(dev, &active_buf->dbufs);
1894		- else
	1989	+ if (dev->is_support_tools && stream->tools_vdev)
	1990	+ rkcif_rdbk_with_tools(stream, active_buf);
	1991	+ atomic_dec(&stream->buf_cnt);
	1992	+ } else {
1895	1993	rkcif_rdbk_frame_end_toisp(stream, active_buf);
1896		- stream->buf_num_toisp--;
	1994	+ }
1897	1995	} else {
1898		- rkcif_s_rx_buffer(dev, &stream->next_buf_toisp->dbufs);
1899		- stream->buf_num_toisp--;
	1996	+ rkcif_s_rx_buffer(dev, &active_buf->dbufs);
	1997	+ if (dev->is_support_tools && stream->tools_vdev)
	1998	+ rkcif_rdbk_with_tools(stream, active_buf);
1900	1999	}
1901	2000	} else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
1902	2001	if (stream->curr_buf_toisp == stream->next_buf_toisp)
..	..	@@ -1918,14 +2017,18 @@
1918	2017	active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
1919	2018	active_buf->fe_timestamp = ktime_get_ns();
1920	2019	stream->last_frame_idx = stream->frame_idx;
1921		- if (dev->hdr.hdr_mode == NO_HDR)
	2020	+ if (dev->hdr.hdr_mode == NO_HDR) {
1922	2021	rkcif_s_rx_buffer(dev, &active_buf->dbufs);
1923		- else
	2022	+ if (dev->is_support_tools && stream->tools_vdev)
	2023	+ rkcif_rdbk_with_tools(stream, active_buf);
	2024	+ atomic_dec(&stream->buf_cnt);
	2025	+ } else {
1924	2026	rkcif_rdbk_frame_end_toisp(stream, active_buf);
1925		- stream->buf_num_toisp--;
	2027	+ }
1926	2028	} else {
1927		- rkcif_s_rx_buffer(dev, &stream->curr_buf_toisp->dbufs);
1928		- stream->buf_num_toisp--;
	2029	+ rkcif_s_rx_buffer(dev, &active_buf->dbufs);
	2030	+ if (dev->is_support_tools && stream->tools_vdev)
	2031	+ rkcif_rdbk_with_tools(stream, active_buf);
1929	2032	}
1930	2033	}
1931	2034	if (stream->lack_buf_cnt)
..	..	@@ -1967,10 +2070,14 @@
1967	2070	active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
1968	2071	active_buf->fe_timestamp = ktime_get_ns();
1969	2072	stream->last_frame_idx = stream->frame_idx;
1970		- if (dev->hdr.hdr_mode == NO_HDR)
	2073	+ if (dev->hdr.hdr_mode == NO_HDR) {
1971	2074	rkcif_s_rx_buffer(dev, &active_buf->dbufs);
1972		- else
	2075	+ if (dev->is_support_tools && stream->tools_vdev)
	2076	+ rkcif_rdbk_with_tools(stream, active_buf);
	2077	+ atomic_dec(&stream->buf_cnt);
	2078	+ } else {
1973	2079	rkcif_rdbk_frame_end_toisp(stream, active_buf);
	2080	+ }
1974	2081	} else {
1975	2082	if (stream->cifdev->rdbk_debug && dev->hw_dev->dummy_buf.vaddr)
1976	2083	v4l2_info(&stream->cifdev->v4l2_dev,
..	..	@@ -1978,13 +2085,20 @@
1978	2085	stream->id,
1979	2086	stream->frame_idx - 1);
1980	2087	}
	2088	+ if (dev->is_support_tools && stream->tools_vdev && stream->curr_buf_toisp)
	2089	+ rkcif_rdbk_with_tools(stream, stream->curr_buf_toisp);
1981	2090	}
1982	2091
1983	2092	out_get_buf:
1984	2093	stream->frame_phase_cache = stream->frame_phase;
1985	2094	if (buffer) {
1986		- rkcif_write_register(dev, frm_addr_y,
1987		- buffer->dummy.dma_addr);
	2095	+ buff_addr_y = buffer->dummy.dma_addr;
	2096	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2097	+ rkcif_write_buff_addr_multi_dev_combine(stream, frm_addr_y, 0,
	2098	+ buff_addr_y, 0, false);
	2099	+ } else {
	2100	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2101	+ }
1988	2102	if (dev->rdbk_debug > 1 &&
1989	2103	stream->frame_idx < 15)
1990	2104	v4l2_info(&dev->v4l2_dev,
..	..	@@ -1994,8 +2108,13 @@
1994	2108	frm_addr_y, (u32)buffer->dummy.dma_addr);
1995	2109	} else if (dev->hw_dev->dummy_buf.vaddr && priv &&
1996	2110	priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO) {
1997		- rkcif_write_register(dev, frm_addr_y,
1998		- dev->hw_dev->dummy_buf.dma_addr);
	2111	+ buff_addr_y = dev->hw_dev->dummy_buf.dma_addr;
	2112	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2113	+ rkcif_write_buff_addr_multi_dev_combine(stream, frm_addr_y, 0,
	2114	+ buff_addr_y, 0, true);
	2115	+ } else {
	2116	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2117	+ }
1999	2118	}
2000	2119	spin_unlock_irqrestore(&stream->vbq_lock, flags);
2001	2120	return 0;
..	..	@@ -2018,8 +2137,9 @@
2018	2137	struct rkcif_device *dev = stream->cifdev;
2019	2138	struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
2020	2139	struct rkcif_rx_buffer *buffer = NULL;
	2140	+ struct rkmodule_capture_info *capture_info = &dev->channels[stream->id].capture_info;
2021	2141	struct rkcif_rx_buffer *active_buf = NULL;
2022		- u32 frm_addr_y;
	2142	+ u32 frm_addr_y, buff_addr_y;
2023	2143	u32 vblank = 0;
2024	2144	u32 vblank_ns = 0;
2025	2145	u64 cur_time = 0;
..	..	@@ -2082,8 +2202,15 @@
2082	2202	if (buffer) {
2083	2203	list_del(&buffer->list);
2084	2204	stream->curr_buf_toisp = buffer;
2085		- rkcif_write_register(dev, frm_addr_y,
2086		- stream->curr_buf_toisp->dummy.dma_addr);
	2205	+ buff_addr_y = stream->curr_buf_toisp->dummy.dma_addr;
	2206	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2207	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2208	+ frm_addr_y, 0,
	2209	+ buff_addr_y, 0,
	2210	+ false);
	2211	+ } else {
	2212	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2213	+ }
2087	2214	if (dev->rdbk_debug > 1 &&
2088	2215	stream->frame_idx < 15)
2089	2216	v4l2_info(&dev->v4l2_dev,
..	..	@@ -2091,7 +2218,6 @@
2091	2218	stream->id,
2092	2219	stream->frame_idx - 1, frm_addr_y,
2093	2220	(u32)stream->curr_buf_toisp->dummy.dma_addr);
2094		- stream->buf_num_toisp--;
2095	2221	}
2096	2222	} else if (frame_phase == CIF_CSI_FRAME1_READY) {
2097	2223	active_buf = stream->next_buf_toisp;
..	..	@@ -2100,8 +2226,15 @@
2100	2226	if (buffer) {
2101	2227	list_del(&buffer->list);
2102	2228	stream->next_buf_toisp = buffer;
2103		- rkcif_write_register(dev, frm_addr_y,
2104		- stream->next_buf_toisp->dummy.dma_addr);
	2229	+ buff_addr_y = stream->next_buf_toisp->dummy.dma_addr;
	2230	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2231	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2232	+ frm_addr_y, 0,
	2233	+ buff_addr_y, 0,
	2234	+ false);
	2235	+ } else {
	2236	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2237	+ }
2105	2238	if (dev->rdbk_debug > 1 &&
2106	2239	stream->frame_idx < 15)
2107	2240	v4l2_info(&dev->v4l2_dev,
..	..	@@ -2109,7 +2242,6 @@
2109	2242	stream->id,
2110	2243	stream->frame_idx - 1, frm_addr_y,
2111	2244	(u32)stream->next_buf_toisp->dummy.dma_addr);
2112		- stream->buf_num_toisp--;
2113	2245	}
2114	2246	}
2115	2247	if (stream->lack_buf_cnt)
..	..	@@ -2150,8 +2282,13 @@
2150	2282	stream->next_buf_toisp = stream->curr_buf_toisp;
2151	2283	else
2152	2284	stream->curr_buf_toisp = stream->next_buf_toisp;
2153		- rkcif_write_register(dev, frm_addr_y,
2154		- stream->curr_buf_toisp->dummy.dma_addr);
	2285	+ buff_addr_y = stream->curr_buf_toisp->dummy.dma_addr;
	2286	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2287	+ rkcif_write_buff_addr_multi_dev_combine(stream, frm_addr_y, 0,
	2288	+ buff_addr_y, 0, false);
	2289	+ } else {
	2290	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2291	+ }
2155	2292	}
2156	2293	}
2157	2294
..	..	@@ -2162,6 +2299,7 @@
2162	2299	struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
2163	2300	u32 frm0_addr_y, frm0_addr_uv;
2164	2301	u32 frm1_addr_y, frm1_addr_uv;
	2302	+ u32 buff_addr_y, buff_addr_cbcr;
2165	2303	unsigned long flags;
2166	2304	struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
2167	2305	struct csi_channel_info *channel = &dev->channels[channel_id];
..	..	@@ -2187,21 +2325,45 @@
2187	2325	stream->curr_buf = list_first_entry(&stream->buf_head,
2188	2326	struct rkcif_buffer,
2189	2327	queue);
	2328	+ v4l2_dbg(4, rkcif_debug, &dev->v4l2_dev, "%s %d, stream[%d] buf idx %d\n",
	2329	+ __func__, __LINE__, stream->id, stream->curr_buf->vb.vb2_buf.index);
2190	2330	list_del(&stream->curr_buf->queue);
2191	2331	}
2192	2332	}
2193	2333
2194	2334	if (stream->curr_buf) {
2195		- rkcif_write_register(dev, frm0_addr_y,
2196		- stream->curr_buf->buff_addr[RKCIF_PLANE_Y]);
2197		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2198		- rkcif_write_register(dev, frm0_addr_uv,
2199		- stream->curr_buf->buff_addr[RKCIF_PLANE_CBCR]);
	2335	+ buff_addr_y = stream->curr_buf->buff_addr[RKCIF_PLANE_Y];
	2336	+ buff_addr_cbcr = stream->curr_buf->buff_addr[RKCIF_PLANE_CBCR];
	2337	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2338	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2339	+ frm0_addr_y,
	2340	+ frm0_addr_uv,
	2341	+ buff_addr_y,
	2342	+ buff_addr_cbcr,
	2343	+ false);
	2344	+ } else {
	2345	+ rkcif_write_register(dev, frm0_addr_y,
	2346	+ stream->curr_buf->buff_addr[RKCIF_PLANE_Y]);
	2347	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2348	+ rkcif_write_register(dev, frm0_addr_uv,
	2349	+ stream->curr_buf->buff_addr[RKCIF_PLANE_CBCR]);
	2350	+ }
2200	2351	} else {
2201	2352	if (dummy_buf->vaddr) {
2202		- rkcif_write_register(dev, frm0_addr_y, dummy_buf->dma_addr);
2203		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2204		- rkcif_write_register(dev, frm0_addr_uv, dummy_buf->dma_addr);
	2353	+ buff_addr_y = dummy_buf->dma_addr;
	2354	+ buff_addr_cbcr = dummy_buf->dma_addr;
	2355	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2356	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2357	+ frm0_addr_y,
	2358	+ frm0_addr_uv,
	2359	+ buff_addr_y,
	2360	+ buff_addr_cbcr,
	2361	+ true);
	2362	+ } else {
	2363	+ rkcif_write_register(dev, frm0_addr_y, buff_addr_y);
	2364	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2365	+ rkcif_write_register(dev, frm0_addr_uv, buff_addr_cbcr);
	2366	+ }
2205	2367	} else {
2206	2368	if (stream->lack_buf_cnt < 2)
2207	2369	stream->lack_buf_cnt++;
..	..	@@ -2211,43 +2373,69 @@
2211	2373	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
2212	2374	stream->next_buf = stream->curr_buf;
2213	2375	if (stream->next_buf) {
2214		- rkcif_write_register(dev, frm1_addr_y,
2215		- stream->next_buf->buff_addr[RKCIF_PLANE_Y] + (channel->virtual_width / 2));
2216		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2217		- rkcif_write_register(dev, frm1_addr_uv,
2218		- stream->next_buf->buff_addr[RKCIF_PLANE_CBCR] + (channel->virtual_width / 2));
	2376	+ buff_addr_y = stream->next_buf->buff_addr[RKCIF_PLANE_Y];
	2377	+ buff_addr_cbcr = stream->next_buf->buff_addr[RKCIF_PLANE_CBCR];
	2378	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2379	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2380	+ frm1_addr_y,
	2381	+ frm1_addr_uv,
	2382	+ buff_addr_y,
	2383	+ buff_addr_cbcr,
	2384	+ false);
	2385	+ } else {
	2386	+ rkcif_write_register(dev, frm1_addr_y,
	2387	+ buff_addr_y + (channel->virtual_width / 2));
	2388	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2389	+ rkcif_write_register(dev, frm1_addr_uv,
	2390	+ buff_addr_cbcr + (channel->virtual_width / 2));
	2391	+ }
2219	2392	}
2220	2393	} else {
2221	2394	if (!stream->next_buf) {
2222	2395	if (!list_empty(&stream->buf_head)) {
2223	2396	stream->next_buf = list_first_entry(&stream->buf_head,
2224	2397	struct rkcif_buffer, queue);
	2398	+ v4l2_dbg(4, rkcif_debug, &dev->v4l2_dev, "%s %d, stream[%d] buf idx %d\n",
	2399	+ __func__, __LINE__, stream->id, stream->next_buf->vb.vb2_buf.index);
2225	2400	list_del(&stream->next_buf->queue);
2226	2401	}
2227	2402	}
2228	2403
2229		- if (stream->next_buf) {
2230		- rkcif_write_register(dev, frm1_addr_y,
2231		- stream->next_buf->buff_addr[RKCIF_PLANE_Y]);
2232		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2233		- rkcif_write_register(dev, frm1_addr_uv,
2234		- stream->next_buf->buff_addr[RKCIF_PLANE_CBCR]);
2235		- } else {
2236		- if (dummy_buf->vaddr) {
	2404	+ if (!stream->next_buf && dummy_buf->vaddr) {
	2405	+ buff_addr_y = dummy_buf->dma_addr;
	2406	+ buff_addr_cbcr = dummy_buf->dma_addr;
	2407	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2408	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2409	+ frm1_addr_y,
	2410	+ frm1_addr_uv,
	2411	+ buff_addr_y,
	2412	+ buff_addr_cbcr,
	2413	+ true);
	2414	+ } else {
2237	2415	rkcif_write_register(dev, frm1_addr_y, dummy_buf->dma_addr);
2238	2416	if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2239	2417	rkcif_write_register(dev, frm1_addr_uv, dummy_buf->dma_addr);
	2418	+ }
	2419	+
	2420	+ } else if (!stream->next_buf && stream->curr_buf) {
	2421	+ stream->next_buf = stream->curr_buf;
	2422	+ if (stream->lack_buf_cnt < 2)
	2423	+ stream->lack_buf_cnt++;
	2424	+ }
	2425	+ if (stream->next_buf) {
	2426	+ buff_addr_y = stream->next_buf->buff_addr[RKCIF_PLANE_Y];
	2427	+ buff_addr_cbcr = stream->next_buf->buff_addr[RKCIF_PLANE_CBCR];
	2428	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2429	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2430	+ frm1_addr_y,
	2431	+ frm1_addr_uv,
	2432	+ buff_addr_y,
	2433	+ buff_addr_cbcr,
	2434	+ false);
2240	2435	} else {
2241		- if (stream->curr_buf) {
2242		- stream->next_buf = stream->curr_buf;
2243		- rkcif_write_register(dev, frm1_addr_y,
2244		- stream->next_buf->buff_addr[RKCIF_PLANE_Y]);
2245		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2246		- rkcif_write_register(dev, frm1_addr_uv,
2247		- stream->next_buf->buff_addr[RKCIF_PLANE_CBCR]);
2248		- }
2249		- if (stream->lack_buf_cnt < 2)
2250		- stream->lack_buf_cnt++;
	2436	+ rkcif_write_register(dev, frm1_addr_y, buff_addr_y);
	2437	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2438	+ rkcif_write_register(dev, frm1_addr_uv, buff_addr_cbcr);
2251	2439	}
2252	2440	}
2253	2441	}
..	..	@@ -2295,6 +2483,7 @@
2295	2483	struct rkisp_rx_buf *dbufs = NULL;
2296	2484	struct dma_buf *dbuf = NULL;
2297	2485	int ret = 0;
	2486	+ u32 buff_addr_y, buff_addr_cbcr;
2298	2487	unsigned long flags;
2299	2488
2300	2489	if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
..	..	@@ -2315,16 +2504,15 @@
2315	2504	get_dvp_reg_index_of_frm1_uv_addr(channel_id);
2316	2505	}
2317	2506
2318		- if (dev->hdr.hdr_mode != NO_HDR && stream->id != 0 && (!dev->rdbk_buf[RDBK_L])) {
2319		- v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "%s %d\n", __func__, __LINE__);
2320		- return -EINVAL;
2321		- }
2322		-
2323	2507	if (stream->to_stop_dma) {
2324	2508	if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
2325	2509	v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "%s %d\n", __func__, __LINE__);
2326	2510	goto stop_dma;
2327	2511	} else {
	2512	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY)
	2513	+ stream->curr_buf = NULL;
	2514	+ else
	2515	+ stream->next_buf = NULL;
2328	2516	v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "%s %d\n", __func__, __LINE__);
2329	2517	return -EINVAL;
2330	2518	}
..	..	@@ -2347,8 +2535,8 @@
2347	2535	list_del(&stream->curr_buf->queue);
2348	2536	buffer = stream->curr_buf;
2349	2537	v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
2350		- "stream[%d] update curr_buf 0x%x\n",
2351		- stream->id, buffer->buff_addr[0]);
	2538	+ "stream[%d] update curr_buf 0x%x, buf idx %d\n",
	2539	+ stream->id, buffer->buff_addr[0], stream->curr_buf->vb.vb2_buf.index);
2352	2540	}
2353	2541	} else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
2354	2542	if (!stream->next_buf)
..	..	@@ -2368,8 +2556,8 @@
2368	2556	list_del(&stream->next_buf->queue);
2369	2557	buffer = stream->next_buf;
2370	2558	v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
2371		- "stream[%d] update next_buf 0x%x\n",
2372		- stream->id, buffer->buff_addr[0]);
	2559	+ "stream[%d] update next_buf 0x%x, buf idx %d\n",
	2560	+ stream->id, buffer->buff_addr[0], stream->next_buf->vb.vb2_buf.index);
2373	2561	}
2374	2562	}
2375	2563	}
..	..	@@ -2407,19 +2595,37 @@
2407	2595	stream->frame_phase_cache = stream->frame_phase;
2408	2596
2409	2597	if (buffer) {
	2598	+ buff_addr_y = buffer->buff_addr[RKCIF_PLANE_Y];
	2599	+ buff_addr_cbcr = buffer->buff_addr[RKCIF_PLANE_CBCR];
2410	2600	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED &&
2411	2601	stream->frame_phase == CIF_CSI_FRAME1_READY) {
2412		- rkcif_write_register(dev, frm_addr_y,
2413		- buffer->buff_addr[RKCIF_PLANE_Y] + (channel->virtual_width / 2));
2414		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2415		- rkcif_write_register(dev, frm_addr_uv,
2416		- buffer->buff_addr[RKCIF_PLANE_CBCR] + (channel->virtual_width / 2));
	2602	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2603	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2604	+ frm_addr_y,
	2605	+ frm_addr_uv,
	2606	+ buff_addr_y,
	2607	+ buff_addr_cbcr,
	2608	+ false);
	2609	+ } else {
	2610	+ rkcif_write_register(dev, frm_addr_y,
	2611	+ buff_addr_y + (channel->virtual_width / 2));
	2612	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2613	+ rkcif_write_register(dev, frm_addr_uv,
	2614	+ buff_addr_cbcr + (channel->virtual_width / 2));
	2615	+ }
2417	2616	} else {
2418		- rkcif_write_register(dev, frm_addr_y,
2419		- buffer->buff_addr[RKCIF_PLANE_Y]);
2420		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2421		- rkcif_write_register(dev, frm_addr_uv,
2422		- buffer->buff_addr[RKCIF_PLANE_CBCR]);
	2617	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2618	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2619	+ frm_addr_y,
	2620	+ frm_addr_uv,
	2621	+ buff_addr_y,
	2622	+ buff_addr_cbcr,
	2623	+ false);
	2624	+ } else {
	2625	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2626	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2627	+ rkcif_write_register(dev, frm_addr_uv, buff_addr_cbcr);
	2628	+ }
2423	2629	}
2424	2630	if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
2425	2631	if (stream->buf_replace_cnt < 2)
..	..	@@ -2439,12 +2645,16 @@
2439	2645	}
2440	2646	if (dbufs)
2441	2647	rkcif_s_rx_buffer(dev, dbufs);
2442		- stream->buf_num_toisp--;
2443	2648	}
2444	2649	} else {
2445	2650	if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
2446		- rkcif_write_register(dev, frm_addr_y,
2447		- stream->curr_buf_toisp->dummy.dma_addr);
	2651	+ buff_addr_y = stream->curr_buf_toisp->dummy.dma_addr;
	2652	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE)
	2653	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2654	+ frm_addr_y, 0,
	2655	+ buff_addr_y, 0, false);
	2656	+ else
	2657	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
2448	2658	if (stream->frame_phase == CIF_CSI_FRAME0_READY &&
2449	2659	stream->next_buf)
2450	2660	dbuf = stream->next_buf->dbuf;
..	..	@@ -2460,7 +2670,6 @@
2460	2670	dbufs = &stream->curr_buf_toisp->dbufs;
2461	2671	}
2462	2672	rkcif_s_rx_buffer(dev, dbufs);
2463		- stream->buf_num_toisp--;
2464	2673	if (stream->curr_buf && stream->frame_phase == CIF_CSI_FRAME0_READY) {
2465	2674	stream->curr_buf = NULL;
2466	2675	if (stream->buf_replace_cnt)
..	..	@@ -2471,11 +2680,24 @@
2471	2680	stream->buf_replace_cnt--;
2472	2681	}
2473	2682	} else if (dummy_buf->vaddr) {
2474		- rkcif_write_register(dev, frm_addr_y, dummy_buf->dma_addr);
2475		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2476		- rkcif_write_register(dev, frm_addr_uv, dummy_buf->dma_addr);
	2683	+
	2684	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2685	+ buff_addr_y = dummy_buf->dma_addr;
	2686	+ buff_addr_cbcr = dummy_buf->dma_addr;
	2687	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2688	+ frm_addr_y,
	2689	+ frm_addr_uv,
	2690	+ buff_addr_y,
	2691	+ buff_addr_cbcr,
	2692	+ true);
	2693	+ } else {
	2694	+ rkcif_write_register(dev, frm_addr_y, dummy_buf->dma_addr);
	2695	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2696	+ rkcif_write_register(dev, frm_addr_uv, dummy_buf->dma_addr);
	2697	+ }
2477	2698	dev->err_state \|= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
2478	2699	dev->irq_stats.not_active_buf_cnt[stream->id]++;
	2700	+
2479	2701	} else {
2480	2702	ret = -EINVAL;
2481	2703	stream->curr_buf = NULL;
..	..	@@ -2489,8 +2711,13 @@
2489	2711	stop_dma:
2490	2712	if (stream->buf_replace_cnt) {
2491	2713	spin_lock_irqsave(&stream->vbq_lock, flags);
2492		- rkcif_write_register(dev, frm_addr_y,
2493		- stream->curr_buf_toisp->dummy.dma_addr);
	2714	+ buff_addr_y = stream->curr_buf_toisp->dummy.dma_addr;
	2715	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE)
	2716	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2717	+ frm_addr_y, 0,
	2718	+ buff_addr_y, 0, false);
	2719	+ else
	2720	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
2494	2721	if (stream->frame_phase == CIF_CSI_FRAME0_READY &&
2495	2722	stream->next_buf)
2496	2723	dbuf = stream->next_buf->dbuf;
..	..	@@ -2507,15 +2734,12 @@
2507	2734	}
2508	2735	if (dbufs)
2509	2736	rkcif_s_rx_buffer(dev, dbufs);
2510		- stream->buf_num_toisp--;
2511	2737
2512	2738	if (stream->frame_phase == CIF_CSI_FRAME0_READY &&
2513	2739	stream->curr_buf) {
2514		- list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
2515	2740	stream->curr_buf = NULL;
2516	2741	} else if (stream->frame_phase == CIF_CSI_FRAME1_READY &&
2517	2742	stream->next_buf) {
2518		- list_add_tail(&stream->next_buf->queue, &stream->buf_head);
2519	2743	stream->next_buf = NULL;
2520	2744	}
2521	2745	stream->buf_replace_cnt--;
..	..	@@ -2587,8 +2811,10 @@
2587	2811	struct rkcif_device *dev = stream->cifdev;
2588	2812	struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
2589	2813	struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	2814	+ struct rkmodule_capture_info *capture_info = &dev->channels[stream->id].capture_info;
2590	2815	struct rkcif_buffer *buffer = NULL;
2591	2816	u32 frm_addr_y, frm_addr_uv;
	2817	+ u32 buff_addr_y, buff_addr_cbcr;
2592	2818	int channel_id = stream->id;
2593	2819	int ret = 0;
2594	2820	unsigned long flags;
..	..	@@ -2619,16 +2845,35 @@
2619	2845	}
2620	2846	spin_unlock_irqrestore(&stream->vbq_lock, flags);
2621	2847	if (buffer) {
2622		- rkcif_write_register(dev, frm_addr_y,
2623		- buffer->buff_addr[RKCIF_PLANE_Y]);
2624		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2625		- rkcif_write_register(dev, frm_addr_uv,
2626		- buffer->buff_addr[RKCIF_PLANE_CBCR]);
	2848	+ buff_addr_y = buffer->buff_addr[RKCIF_PLANE_Y];
	2849	+ buff_addr_cbcr = buffer->buff_addr[RKCIF_PLANE_CBCR];
	2850	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2851	+ rkcif_write_buff_addr_multi_dev_combine(stream, frm_addr_y,
	2852	+ frm_addr_uv,
	2853	+ buff_addr_y,
	2854	+ buff_addr_cbcr,
	2855	+ false);
	2856	+ } else {
	2857	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2858	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2859	+ rkcif_write_register(dev, frm_addr_uv, buff_addr_cbcr);
	2860	+ }
2627	2861	} else {
2628	2862	if (dummy_buf->vaddr) {
2629		- rkcif_write_register(dev, frm_addr_y, dummy_buf->dma_addr);
2630		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2631		- rkcif_write_register(dev, frm_addr_uv, dummy_buf->dma_addr);
	2863	+ buff_addr_y = dummy_buf->dma_addr;
	2864	+ buff_addr_cbcr = dummy_buf->dma_addr;
	2865	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2866	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2867	+ frm_addr_y,
	2868	+ frm_addr_uv,
	2869	+ buff_addr_y,
	2870	+ buff_addr_cbcr,
	2871	+ true);
	2872	+ } else {
	2873	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2874	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2875	+ rkcif_write_register(dev, frm_addr_uv, buff_addr_cbcr);
	2876	+ }
2632	2877	} else {
2633	2878	if (dev->chip_id < CHIP_RK3588_CIF)
2634	2879	ret = -EINVAL;
..	..	@@ -3163,6 +3408,7 @@
3163	3408	struct csi_channel_info *channel)
3164	3409	{
3165	3410	struct rkcif_device *dev = stream->cifdev;
	3411	+ struct sditf_priv *priv = dev->sditf[0];
3166	3412	const struct cif_output_fmt *fmt;
3167	3413	u32 fourcc;
3168	3414	int vc = dev->channels[stream->id].vc;
..	..	@@ -3187,7 +3433,7 @@
3187	3433	channel->crop_st_x = stream->crop[CROP_SRC_ACT].left;
3188	3434
3189	3435	channel->crop_st_y = stream->crop[CROP_SRC_ACT].top;
3190		- if (dev->sditf_cnt > 1 && dev->sditf_cnt <= RKCIF_MAX_SDITF)
	3436	+ if (priv && priv->is_combine_mode && dev->sditf_cnt <= RKCIF_MAX_SDITF)
3191	3437	channel->crop_st_y *= dev->sditf_cnt;
3192	3438	channel->width = stream->crop[CROP_SRC_ACT].width;
3193	3439	channel->height = stream->crop[CROP_SRC_ACT].height;
..	..	@@ -3197,7 +3443,7 @@
3197	3443	channel->crop_en = 0;
3198	3444	}
3199	3445
3200		- if (dev->sditf_cnt > 1 && dev->sditf_cnt <= RKCIF_MAX_SDITF)
	3446	+ if (priv && priv->is_combine_mode && dev->sditf_cnt <= RKCIF_MAX_SDITF)
3201	3447	channel->height *= dev->sditf_cnt;
3202	3448
3203	3449	fmt = rkcif_find_output_fmt(stream, stream->pixm.pixelformat);
..	..	@@ -3207,6 +3453,8 @@
3207	3453	return -EINVAL;
3208	3454	}
3209	3455
	3456	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE)
	3457	+ channel->width /= channel->capture_info.multi_dev.dev_num;
3210	3458	/*
3211	3459	* for mipi or lvds, when enable compact, the virtual width of raw10/raw12
3212	3460	* needs aligned with :ALIGN(bits_per_pixel * width / 8, 8), if enable 16bit mode
..	..	@@ -3216,9 +3464,19 @@
3216	3464	if (fmt->fmt_type == CIF_FMT_TYPE_RAW && stream->is_compact &&
3217	3465	fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888 &&
3218	3466	fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB565) {
3219		- channel->virtual_width = ALIGN(channel->width * fmt->raw_bpp / 8, 256);
	3467	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	3468	+ channel->virtual_width = ALIGN(channel->width * 2 * fmt->raw_bpp / 8, 256);
	3469	+ channel->left_virtual_width = channel->width * fmt->raw_bpp / 8;
	3470	+ } else {
	3471	+ channel->virtual_width = ALIGN(channel->width * fmt->raw_bpp / 8, 256);
	3472	+ }
3220	3473	} else {
3221		- channel->virtual_width = ALIGN(channel->width * fmt->bpp[0] / 8, 8);
	3474	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	3475	+ channel->virtual_width = ALIGN(channel->width * 2 * fmt->bpp[0] / 8, 8);
	3476	+ channel->left_virtual_width = ALIGN(channel->width * fmt->bpp[0] / 8, 8);
	3477	+ } else {
	3478	+ channel->virtual_width = ALIGN(channel->width * fmt->bpp[0] / 8, 8);
	3479	+ }
3222	3480	}
3223	3481
3224	3482	if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888 \|\| channel->fmt_val == CSI_WRDDR_TYPE_RGB565)
..	..	@@ -3237,6 +3495,8 @@
3237	3495	channel->width *= 2;
3238	3496	}
3239	3497	channel->virtual_width *= 2;
	3498	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE)
	3499	+ channel->left_virtual_width *= 2;
3240	3500	}
3241	3501	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
3242	3502	channel->virtual_width *= 2;
..	..	@@ -3585,15 +3845,18 @@
3585	3845
3586	3846	/config reg for rk3588/
3587	3847	static int rkcif_csi_channel_set_v1(struct rkcif_stream *stream,
3588		- struct csi_channel_info *channel,
3589		- enum v4l2_mbus_type mbus_type, unsigned int mode)
	3848	+ struct csi_channel_info *channel,
	3849	+ enum v4l2_mbus_type mbus_type, unsigned int mode,
	3850	+ int index)
3590	3851	{
3591	3852	unsigned int val = 0x0;
3592	3853	struct rkcif_device *dev = stream->cifdev;
3593	3854	struct rkcif_stream *detect_stream = &dev->stream[0];
3594	3855	struct sditf_priv *priv = dev->sditf[0];
	3856	+ struct rkmodule_capture_info *capture_info = &channel->capture_info;
3595	3857	unsigned int wait_line = 0x3fff;
3596	3858	unsigned int dma_en = 0;
	3859	+ int offset = 0;
3597	3860
3598	3861	if (channel->id >= 4)
3599	3862	return -EINVAL;
..	..	@@ -3609,21 +3872,28 @@
3609	3872	CSI_DMA_END_INTSTAT(channel->id) \|
3610	3873	CSI_LINE_INTSTAT_V1(channel->id)));
3611	3874
3612		- rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
3613		- CSI_START_INTEN(channel->id));
	3875	+ if (!(capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
	3876	+ index < capture_info->multi_dev.dev_num - 1)) {
3614	3877
3615		- if (priv && priv->mode.rdbk_mode && detect_stream->is_line_wake_up) {
3616	3878	rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
3617		- CSI_LINE_INTEN_RK3588(channel->id));
3618		- wait_line = dev->wait_line;
3619		- }
3620		- rkcif_write_register(dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1,
3621		- wait_line << 16 \| wait_line);
3622		- rkcif_write_register(dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3,
3623		- wait_line << 16 \| wait_line);
	3879	+ CSI_START_INTEN(channel->id));
3624	3880
3625		- rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
3626		- CSI_DMA_END_INTEN(channel->id));
	3881	+ if (priv && priv->mode.rdbk_mode && detect_stream->is_line_wake_up) {
	3882	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
	3883	+ CSI_LINE_INTEN_RK3588(channel->id));
	3884	+ wait_line = dev->wait_line;
	3885	+ }
	3886	+ rkcif_write_register(dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1,
	3887	+ wait_line << 16 \| wait_line);
	3888	+ rkcif_write_register(dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3,
	3889	+ wait_line << 16 \| wait_line);
	3890	+
	3891	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
	3892	+ CSI_DMA_END_INTEN(channel->id));
	3893	+
	3894	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
	3895	+ CSI_ALL_ERROR_INTEN_V1);
	3896	+ }
3627	3897	if (stream->cifdev->id_use_cnt == 0) {
3628	3898	val = CIF_MIPI_LVDS_SW_PRESS_VALUE_RK3588(0x3) \|
3629	3899	CIF_MIPI_LVDS_SW_PRESS_ENABLE \|
..	..	@@ -3637,24 +3907,25 @@
3637	3907	else
3638	3908	val \|= CIF_MIPI_LVDS_SW_SEL_LVDS_RV1106;
3639	3909	rkcif_write_register(dev, CIF_REG_MIPI_LVDS_CTRL, val);
3640		-
3641		- rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
3642		- CSI_ALL_ERROR_INTEN_V1);
3643	3910	}
3644	3911	#if IS_ENABLED(CONFIG_CPU_RV1106)
3645	3912	if (channel->id == 1)
3646	3913	rv1106_sdmmc_get_lock();
3647	3914	#endif
	3915	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
	3916	+ priv && priv->mode.rdbk_mode == RKISP_VICAP_ONLINE &&
	3917	+ (dev->hdr.hdr_mode == NO_HDR \|\|
	3918	+ (dev->hdr.hdr_mode == HDR_X2 && stream->id == 1) \|\|
	3919	+ (dev->hdr.hdr_mode == HDR_X3 && stream->id == 2)))
	3920	+ offset = channel->capture_info.multi_dev.pixel_offset;
	3921	+
3648	3922	rkcif_write_register(dev, get_reg_index_of_id_ctrl1(channel->id),
3649		- channel->width \| (channel->height << 16));
	3923	+ (channel->width + offset) \| (channel->height << 16));
3650	3924
3651	3925	#if IS_ENABLED(CONFIG_CPU_RV1106)
3652	3926	if (channel->id == 1)
3653	3927	rv1106_sdmmc_put_lock();
3654	3928	#endif
3655		-
3656		- rkcif_write_register(dev, get_reg_index_of_frm0_y_vlw(channel->id),
3657		- channel->virtual_width);
3658	3929
3659	3930	if (channel->crop_en)
3660	3931	rkcif_write_register(dev, get_reg_index_of_id_crop_start(channel->id),
..	..	@@ -3673,6 +3944,17 @@
3673	3944	rkcif_assign_new_buffer_pingpong_rockit(stream,
3674	3945	RKCIF_YUV_ADDR_STATE_INIT,
3675	3946	channel->id);
	3947	+
	3948	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
	3949	+ index == (capture_info->multi_dev.dev_num - 1) &&
	3950	+ priv && priv->mode.rdbk_mode != RKISP_VICAP_ONLINE)
	3951	+ rkcif_write_register(dev, get_reg_index_of_id_crop_start(channel->id),
	3952	+ channel->crop_st_y << 16 \|
	3953	+ (channel->crop_st_x + capture_info->multi_dev.pixel_offset));
	3954	+
	3955	+ rkcif_write_register(dev, get_reg_index_of_frm0_y_vlw(channel->id),
	3956	+ channel->virtual_width);
	3957	+
3676	3958	if (stream->lack_buf_cnt == 2)
3677	3959	stream->dma_en = 0;
3678	3960
..	..	@@ -3735,7 +4017,24 @@
3735	4017	}
3736	4018	if (dev->chip_id >= CHIP_RV1106_CIF)
3737	4019	rkcif_modify_frame_skip_config(stream);
3738		- stream->cifdev->id_use_cnt++;
	4020	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	4021	+ if (index == (capture_info->multi_dev.dev_num - 1))
	4022	+ stream->cifdev->id_use_cnt++;
	4023	+ } else {
	4024	+ stream->cifdev->id_use_cnt++;
	4025	+ }
	4026	+ if (!(capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
	4027	+ index < capture_info->multi_dev.dev_num - 1)) {
	4028	+ if (mode == RKCIF_STREAM_MODE_CAPTURE)
	4029	+ rkcif_assign_new_buffer_pingpong(stream,
	4030	+ RKCIF_YUV_ADDR_STATE_INIT,
	4031	+ channel->id);
	4032	+ else if (mode == RKCIF_STREAM_MODE_TOISP \|\|
	4033	+ mode == RKCIF_STREAM_MODE_TOISP_RDBK)
	4034	+ rkcif_assign_new_buffer_pingpong_toisp(stream,
	4035	+ RKCIF_YUV_ADDR_STATE_INIT,
	4036	+ channel->id);
	4037	+ }
3739	4038	return 0;
3740	4039	}
3741	4040
..	..	@@ -3747,6 +4046,7 @@
3747	4046	enum v4l2_mbus_type mbus_type = active_sensor->mbus.type;
3748	4047	struct csi_channel_info *channel;
3749	4048	u32 ret = 0;
	4049	+ int i;
3750	4050
3751	4051	if (stream->state < RKCIF_STATE_STREAMING) {
3752	4052	stream->frame_idx = 0;
..	..	@@ -3785,10 +4085,18 @@
3785	4085	} else if (mode == RKCIF_STREAM_MODE_ROCKIT) {
3786	4086	stream->dma_en \|= RKCIF_DMAEN_BY_ROCKIT;
3787	4087	}
3788		- if (stream->cifdev->chip_id < CHIP_RK3588_CIF)
	4088	+ if (stream->cifdev->chip_id < CHIP_RK3588_CIF) {
3789	4089	rkcif_csi_channel_set(stream, channel, mbus_type);
3790		- else
3791		- rkcif_csi_channel_set_v1(stream, channel, mbus_type, mode);
	4090	+ } else {
	4091	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	4092	+ for (i = 0; i < channel->capture_info.multi_dev.dev_num; i++) {
	4093	+ dev->csi_host_idx = channel->capture_info.multi_dev.dev_idx[i];
	4094	+ rkcif_csi_channel_set_v1(stream, channel, mbus_type, mode, i);
	4095	+ }
	4096	+ } else {
	4097	+ rkcif_csi_channel_set_v1(stream, channel, mbus_type, mode, 0);
	4098	+ }
	4099	+ }
3792	4100	} else {
3793	4101	if (stream->cifdev->chip_id >= CHIP_RK3588_CIF) {
3794	4102	if (mode == RKCIF_STREAM_MODE_CAPTURE) {
..	..	@@ -3828,7 +4136,9 @@
3828	4136	struct v4l2_mbus_config *mbus_cfg = &cif_dev->active_sensor->mbus;
3829	4137	u32 val;
3830	4138	int id;
	4139	+ int i = 0;
3831	4140
	4141	+ stream->cifdev->id_use_cnt--;
3832	4142	if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
3833	4143	mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
3834	4144	mbus_cfg->type == V4L2_MBUS_CCP2) {
..	..	@@ -3840,7 +4150,14 @@
3840	4150	else
3841	4151	val &= ~LVDS_ENABLE_CAPTURE;
3842	4152
3843		- rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(id), val);
	4153	+ if (cif_dev->channels[id].capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	4154	+ for (i = 0; i < cif_dev->channels[id].capture_info.multi_dev.dev_num; i++) {
	4155	+ cif_dev->csi_host_idx = cif_dev->channels[id].capture_info.multi_dev.dev_idx[i];
	4156	+ rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(id), val);
	4157	+ }
	4158	+ } else {
	4159	+ rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(id), val);
	4160	+ }
3844	4161
3845	4162	rkcif_write_register_or(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT,
3846	4163	CSI_START_INTSTAT(id) \|
..	..	@@ -3859,8 +4176,16 @@
3859	4176	if (stream->cifdev->id_use_cnt == 0) {
3860	4177	rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
3861	4178	~CSI_ALL_ERROR_INTEN_V1);
3862		- rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_CTRL,
3863		- ~CSI_ENABLE_CAPTURE);
	4179	+ if (cif_dev->channels[id].capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	4180	+ for (i = 0; i < cif_dev->channels[id].capture_info.multi_dev.dev_num; i++) {
	4181	+ cif_dev->csi_host_idx = cif_dev->channels[id].capture_info.multi_dev.dev_idx[i];
	4182	+ rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_CTRL,
	4183	+ ~CSI_ENABLE_CAPTURE);
	4184	+ }
	4185	+ } else {
	4186	+ rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_CTRL,
	4187	+ ~CSI_ENABLE_CAPTURE);
	4188	+ }
3864	4189	}
3865	4190	}
3866	4191
..	..	@@ -3876,7 +4201,6 @@
3876	4201	rkcif_config_dvp_pin(cif_dev, false);
3877	4202	}
3878	4203	}
3879		- stream->cifdev->id_use_cnt--;
3880	4204	stream->state = RKCIF_STATE_READY;
3881	4205	stream->dma_en = 0;
3882	4206	}
..	..	@@ -3955,7 +4279,7 @@
3955	4279	plane_fmt = &pixm->plane_fmt[i];
3956	4280	sizes[i] = plane_fmt->sizeimage / height * h;
3957	4281	}
3958		-
	4282	+ stream->total_buf_num = *num_buffers;
3959	4283	v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "%s count %d, size %d, extended(%d, %d)\n",
3960	4284	v4l2_type_names[queue->type], *num_buffers, sizes[0],
3961	4285	is_extended, extend_line->is_extended);
..	..	@@ -3973,6 +4297,8 @@
3973	4297	u32 frm_addr_y = 0, frm_addr_uv = 0;
3974	4298	u32 frm0_addr_y = 0, frm0_addr_uv = 0;
3975	4299	u32 frm1_addr_y = 0, frm1_addr_uv = 0;
	4300	+ u32 buff_addr_y = 0, buff_addr_cbcr = 0;
	4301	+ struct rkmodule_capture_info *capture_info = &dev->channels[channel_id].capture_info;
3976	4302	unsigned long flags;
3977	4303	int frame_phase = 0;
3978	4304	bool is_dual_update_buf = false;
..	..	@@ -4039,22 +4365,51 @@
4039	4365	}
4040	4366	if (buffer) {
4041	4367	if (is_dual_update_buf) {
4042		- rkcif_write_register(dev, frm0_addr_y,
4043		- buffer->buff_addr[RKCIF_PLANE_Y]);
4044		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
4045		- rkcif_write_register(dev, frm0_addr_uv,
4046		- buffer->buff_addr[RKCIF_PLANE_CBCR]);
4047		- rkcif_write_register(dev, frm1_addr_y,
4048		- buffer->buff_addr[RKCIF_PLANE_Y]);
4049		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
4050		- rkcif_write_register(dev, frm1_addr_uv,
4051		- buffer->buff_addr[RKCIF_PLANE_CBCR]);
	4368	+ buff_addr_y = buffer->buff_addr[RKCIF_PLANE_Y];
	4369	+ buff_addr_cbcr = buffer->buff_addr[RKCIF_PLANE_CBCR];
	4370	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	4371	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	4372	+ frm0_addr_y,
	4373	+ frm0_addr_uv,
	4374	+ buff_addr_y,
	4375	+ buff_addr_cbcr,
	4376	+ false);
	4377	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	4378	+ frm1_addr_y,
	4379	+ frm1_addr_uv,
	4380	+ buff_addr_y,
	4381	+ buff_addr_cbcr,
	4382	+ false);
	4383	+ } else {
	4384	+ rkcif_write_register(dev, frm0_addr_y, buff_addr_y);
	4385	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	4386	+ rkcif_write_register(dev,
	4387	+ frm0_addr_uv,
	4388	+ buff_addr_cbcr);
	4389	+ rkcif_write_register(dev, frm1_addr_y, buff_addr_y);
	4390	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	4391	+ rkcif_write_register(dev,
	4392	+ frm1_addr_uv,
	4393	+ buff_addr_cbcr);
	4394	+ }
4052	4395	} else {
4053		- rkcif_write_register(dev, frm_addr_y,
4054		- buffer->buff_addr[RKCIF_PLANE_Y]);
4055		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
4056		- rkcif_write_register(dev, frm_addr_uv,
4057		- buffer->buff_addr[RKCIF_PLANE_CBCR]);
	4396	+
	4397	+ buff_addr_y = buffer->buff_addr[RKCIF_PLANE_Y];
	4398	+ buff_addr_cbcr = buffer->buff_addr[RKCIF_PLANE_CBCR];
	4399	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	4400	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	4401	+ frm_addr_y,
	4402	+ frm_addr_uv,
	4403	+ buff_addr_y,
	4404	+ buff_addr_cbcr,
	4405	+ false);
	4406	+ } else {
	4407	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	4408	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	4409	+ rkcif_write_register(dev,
	4410	+ frm_addr_uv,
	4411	+ buff_addr_cbcr);
	4412	+ }
4058	4413	}
4059	4414	}
4060	4415	} else {
..	..	@@ -4065,11 +4420,17 @@
4065	4420	if (stream->frame_phase_cache == CIF_CSI_FRAME0_READY) {
4066	4421	stream->curr_buf = list_first_entry(&stream->buf_head,
4067	4422	struct rkcif_buffer, queue);
	4423	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
	4424	+ "%s %d, stream[%d] buf idx %d\n",
	4425	+ __func__, __LINE__, stream->id, stream->curr_buf->vb.vb2_buf.index);
4068	4426	if (stream->curr_buf)
4069	4427	list_del(&stream->curr_buf->queue);
4070	4428	} else if (stream->frame_phase_cache == CIF_CSI_FRAME1_READY) {
4071	4429	stream->next_buf = list_first_entry(&stream->buf_head,
4072	4430	struct rkcif_buffer, queue);
	4431	+ v4l2_dbg(4, rkcif_debug, &dev->v4l2_dev,
	4432	+ "%s %d, stream[%d] buf idx %d\n",
	4433	+ __func__, __LINE__, stream->id, stream->next_buf->vb.vb2_buf.index);
4073	4434	if (stream->next_buf)
4074	4435	list_del(&stream->next_buf->queue);
4075	4436	}
..	..	@@ -4098,6 +4459,7 @@
4098	4459	}
4099	4460	if (stream->lack_buf_cnt)
4100	4461	stream->lack_buf_cnt--;
	4462	+
4101	4463	} else {
4102	4464	v4l2_info(&dev->v4l2_dev, "%s %d, state %d, curr_buf %p, next_buf %p\n",
4103	4465	__func__, __LINE__, stream->state, stream->curr_buf, stream->next_buf);
..	..	@@ -4200,6 +4562,7 @@
4200	4562	v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
4201	4563	"stream[%d] buf queue, index: %d, dma_addr 0x%x\n",
4202	4564	stream->id, vb->index, cifbuf->buff_addr[0]);
	4565	+ atomic_inc(&stream->buf_cnt);
4203	4566	}
4204	4567
4205	4568	void rkcif_free_rx_buf(struct rkcif_stream *stream, int buf_num)
..	..	@@ -4229,6 +4592,8 @@
4229	4592	rkcif_free_buffer(dev, &buf->dummy);
4230	4593	else
4231	4594	list_add_tail(&buf->list_free, &priv->buf_free_list);
	4595	+ atomic_dec(&stream->buf_cnt);
	4596	+ stream->total_buf_num--;
4232	4597	}
4233	4598
4234	4599	if (dev->is_thunderboot) {
..	..	@@ -4322,7 +4687,6 @@
4322	4687	if (priv && priv->mode.rdbk_mode == RKISP_VICAP_ONLINE && i == 0) {
4323	4688	buf->dbufs.is_first = true;
4324	4689	rkcif_s_rx_buffer(dev, &buf->dbufs);
4325		- stream->buf_num_toisp--;
4326	4690	}
4327	4691	i++;
4328	4692	if (!dev->is_thunderboot && i >= buf_num) {
..	..	@@ -4338,7 +4702,8 @@
4338	4702	(u64)dummy->dma_addr, pixm->plane_fmt[0].sizeimage);
4339	4703	}
4340	4704	if (priv->buf_num) {
4341		- stream->buf_num_toisp = priv->buf_num;
	4705	+ stream->total_buf_num = priv->buf_num;
	4706	+ atomic_set(&stream->buf_cnt, priv->buf_num);
4342	4707	return 0;
4343	4708	} else {
4344	4709	return -EINVAL;
..	..	@@ -4352,6 +4717,7 @@
4352	4717	struct rkcif_dummy_buffer *dummy_buf = &hw->dummy_buf;
4353	4718	struct rkcif_device *tmp_dev = NULL;
4354	4719	struct v4l2_subdev_frame_interval_enum fie;
	4720	+ struct v4l2_subdev_format fmt;
4355	4721	u32 max_size = 0;
4356	4722	u32 size = 0;
4357	4723	int ret = 0;
..	..	@@ -4386,6 +4752,21 @@
4386	4752	continue;
4387	4753	}
4388	4754	}
	4755	+
	4756	+ if (max_size == 0 && dev->terminal_sensor.sd) {
	4757	+ fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
	4758	+ ret = v4l2_subdev_call(dev->terminal_sensor.sd,
	4759	+ pad, get_fmt, NULL, &fmt);
	4760	+ if (!ret) {
	4761	+ if (fmt.format.code == MEDIA_BUS_FMT_RGB888_1X24)
	4762	+ size = fmt.format.width * fmt.format.height * 3;
	4763	+ else
	4764	+ size = fmt.format.width * fmt.format.height * 2;
	4765	+ if (size > max_size)
	4766	+ max_size = size;
	4767	+ }
	4768	+ }
	4769	+
4389	4770	dummy_buf->size = max_size;
4390	4771
4391	4772	dummy_buf->is_need_vaddr = true;
..	..	@@ -4621,14 +5002,16 @@
4621	5002	} else if (mode == RKCIF_STREAM_MODE_CAPTURE && stream->dma_en & RKCIF_DMAEN_BY_VICAP) {
4622	5003	//only stop dma
4623	5004	stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
	5005	+ stream->is_wait_dma_stop = true;
4624	5006	wait_event_timeout(stream->wq_stopped,
4625		- stream->to_stop_dma != RKCIF_DMAEN_BY_VICAP,
	5007	+ !stream->is_wait_dma_stop,
4626	5008	msecs_to_jiffies(1000));
4627	5009	} else if (mode == RKCIF_STREAM_MODE_TOISP && stream->dma_en & RKCIF_DMAEN_BY_VICAP) {
4628	5010	//only stop dma
4629	5011	stream->to_stop_dma = RKCIF_DMAEN_BY_ISP;
	5012	+ stream->is_wait_dma_stop = true;
4630	5013	wait_event_timeout(stream->wq_stopped,
4631		- stream->to_stop_dma != RKCIF_DMAEN_BY_ISP,
	5014	+ !stream->is_wait_dma_stop,
4632	5015	msecs_to_jiffies(1000));
4633	5016	}
4634	5017	if ((mode & RKCIF_STREAM_MODE_CAPTURE) == RKCIF_STREAM_MODE_CAPTURE) {
..	..	@@ -4664,6 +5047,8 @@
4664	5047	vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
4665	5048	}
4666	5049	}
	5050	+ stream->total_buf_num = 0;
	5051	+ atomic_set(&stream->buf_cnt, 0);
4667	5052	stream->lack_buf_cnt = 0;
4668	5053	stream->dma_en &= ~RKCIF_DMAEN_BY_VICAP;
4669	5054	}
..	..	@@ -4704,10 +5089,12 @@
4704	5089	dev->wait_line = 0;
4705	5090	stream->is_line_wake_up = false;
4706	5091	}
4707		- tasklet_disable(&stream->vb_done_tasklet);
	5092	+ if (can_reset && hw_dev->dummy_buf.vaddr)
	5093	+ rkcif_destroy_dummy_buf(stream);
4708	5094	}
4709		- if (can_reset && hw_dev->dummy_buf.vaddr)
4710		- rkcif_destroy_dummy_buf(stream);
	5095	+ if (mode == RKCIF_STREAM_MODE_CAPTURE)
	5096	+ tasklet_disable(&stream->vb_done_tasklet);
	5097	+
4711	5098	stream->cur_stream_mode &= ~mode;
4712	5099	INIT_LIST_HEAD(&stream->vb_done_list);
4713	5100	v4l2_info(&dev->v4l2_dev, "stream[%d] stopping finished, dma_en 0x%x\n", stream->id, stream->dma_en);
..	..	@@ -4981,6 +5368,7 @@
4981	5368	stream->crop_mask \|= CROP_SRC_SENSOR_MASK;
4982	5369	dev->terminal_sensor.selection = input_sel;
4983	5370	} else {
	5371	+ stream->crop_mask &= ~CROP_SRC_SENSOR_MASK;
4984	5372	dev->terminal_sensor.selection.r = dev->terminal_sensor.raw_rect;
4985	5373	}
4986	5374	}
..	..	@@ -5001,8 +5389,10 @@
5001	5389	stream->crop[CROP_SRC_ACT].top = stream->crop[CROP_SRC_USR].top +
5002	5390	stream->crop[CROP_SRC_SENSOR].top;
5003	5391	}
5004		- } else {
	5392	+ } else if (stream->crop_mask & CROP_SRC_SENSOR_MASK) {
5005	5393	stream->crop[CROP_SRC_ACT] = stream->crop[CROP_SRC_SENSOR];
	5394	+ } else {
	5395	+ stream->crop[CROP_SRC_ACT] = dev->terminal_sensor.raw_rect;
5006	5396	}
5007	5397	}
5008	5398
..	..	@@ -5018,9 +5408,9 @@
5018	5408	struct v4l2_rect input, *crop;
5019	5409
5020	5410	if (dev->terminal_sensor.sd) {
5021		- stream->cif_fmt_in = get_input_fmt(dev->terminal_sensor.sd,
5022		- &input, stream->id,
5023		- &dev->channels[stream->id]);
	5411	+ stream->cif_fmt_in = rkcif_get_input_fmt(dev,
	5412	+ &input, stream->id,
	5413	+ &dev->channels[stream->id]);
5024	5414	if (!stream->cif_fmt_in) {
5025	5415	v4l2_err(v4l2_dev, "Input fmt is invalid\n");
5026	5416	return -EINVAL;
..	..	@@ -5562,6 +5952,7 @@
5562	5952	{
5563	5953	struct rkcif_hw *hw = cifdev->hw_dev;
5564	5954	struct rkcif_device *dev;
	5955	+ struct sditf_priv *priv;
5565	5956	int i = 0, j = 0;
5566	5957	int ret = 0;
5567	5958	int count = 0;
..	..	@@ -5610,12 +6001,12 @@
5610	6001	else
5611	6002	sync_cfg.group = 0;
5612	6003	}
	6004	+ cifdev->sync_cfg = sync_cfg;
5613	6005	if (sync_cfg.type == NO_SYNC_MODE \|\|
5614	6006	hw->sync_config[sync_cfg.group].is_attach) {
5615	6007	mutex_unlock(&hw->dev_lock);
5616	6008	return;
5617	6009	}
5618		- cifdev->sync_cfg = sync_cfg;
5619	6010
5620	6011	sync_config = &hw->sync_config[sync_cfg.group];
5621	6012	memset(sync_config, 0, sizeof(struct rkcif_multi_sync_config));
..	..	@@ -5639,26 +6030,31 @@
5639	6030	else
5640	6031	sync_cfg.group = 0;
5641	6032	} else {
5642		- for (j = 0; j < dev->sditf_cnt; j++) {
5643		- ret \|= v4l2_subdev_call(dev->sditf[j]->sensor_sd,
5644		- core, ioctl,
5645		- RKMODULE_GET_SYNC_MODE,
5646		- &sync_type);
5647		- if (!ret && sync_type)
5648		- break;
	6033	+ priv = dev->sditf[0];
	6034	+ if (priv && priv->is_combine_mode && dev->sditf_cnt <= RKCIF_MAX_SDITF) {
	6035	+ for (j = 0; j < dev->sditf_cnt; j++) {
	6036	+ ret \|= v4l2_subdev_call(dev->sditf[j]->sensor_sd,
	6037	+ core, ioctl,
	6038	+ RKMODULE_GET_SYNC_MODE,
	6039	+ &sync_type);
	6040	+ if (!ret && sync_type) {
	6041	+ priv = dev->sditf[j];
	6042	+ break;
	6043	+ }
	6044	+ }
	6045	+ if (!ret)
	6046	+ sync_cfg.type = sync_type;
	6047	+ else
	6048	+ sync_cfg.type = NO_SYNC_MODE;
	6049	+ ret = v4l2_subdev_call(priv->sensor_sd,
	6050	+ core, ioctl,
	6051	+ RKMODULE_GET_GROUP_ID,
	6052	+ &sync_group);
	6053	+ if (!ret && sync_group < RKCIF_MAX_GROUP)
	6054	+ sync_cfg.group = sync_group;
	6055	+ else
	6056	+ sync_cfg.group = 0;
5649	6057	}
5650		- if (!ret)
5651		- sync_cfg.type = sync_type;
5652		- else
5653		- sync_cfg.type = NO_SYNC_MODE;
5654		- ret = v4l2_subdev_call(dev->sditf[j]->sensor_sd,
5655		- core, ioctl,
5656		- RKMODULE_GET_GROUP_ID,
5657		- &sync_group);
5658		- if (!ret && sync_group < RKCIF_MAX_GROUP)
5659		- sync_cfg.group = sync_group;
5660		- else
5661		- sync_cfg.group = 0;
5662	6058	}
5663	6059	if (sync_cfg.group == cifdev->sync_cfg.group) {
5664	6060	if (sync_cfg.type == EXTERNAL_MASTER_MODE) {
..	..	@@ -5681,6 +6077,11 @@
5681	6077	sync_config->sync_mask \|= BIT(dev->csi_host_idx);
5682	6078	}
5683	6079	dev->sync_cfg = sync_cfg;
	6080	+ } else {
	6081	+ ret = v4l2_subdev_call(dev->terminal_sensor.sd,
	6082	+ core, ioctl,
	6083	+ RKMODULE_GET_SYNC_MODE,
	6084	+ &sync_type);
5684	6085	}
5685	6086	}
5686	6087	if (sync_config->int_master.count == 1) {
..	..	@@ -5714,15 +6115,18 @@
5714	6115	struct rkcif_hw *hw_dev = dev->hw_dev;
5715	6116	struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
5716	6117	struct rkcif_sensor_info *sensor_info = dev->active_sensor;
5717		- struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
	6118	+ struct rkcif_sensor_info *terminal_sensor = NULL;
5718	6119	struct rkmodule_hdr_cfg hdr_cfg;
	6120	+ struct rkcif_csi_info csi_info = {0};
5719	6121	int rkmodule_stream_seq = RKMODULE_START_STREAM_DEFAULT;
5720	6122	int ret;
	6123	+ int i = 0;
5721	6124
5722	6125	v4l2_info(&dev->v4l2_dev, "stream[%d] start streaming\n", stream->id);
5723	6126
5724	6127	rkcif_attach_sync_mode(dev);
5725	6128	mutex_lock(&dev->stream_lock);
	6129	+
5726	6130	if ((stream->cur_stream_mode & RKCIF_STREAM_MODE_CAPTURE) == mode) {
5727	6131	ret = -EBUSY;
5728	6132	v4l2_err(v4l2_dev, "stream in busy state\n");
..	..	@@ -5735,7 +6139,7 @@
5735	6139	else
5736	6140	stream->is_line_inten = false;
5737	6141
5738		- if (dev->active_sensor) {
	6142	+ if (!dev->active_sensor) {
5739	6143	ret = rkcif_update_sensor_info(stream);
5740	6144	if (ret < 0) {
5741	6145	v4l2_err(v4l2_dev,
..	..	@@ -5744,7 +6148,7 @@
5744	6148	goto out;
5745	6149	}
5746	6150	}
5747		-
	6151	+ terminal_sensor = &dev->terminal_sensor;
5748	6152	if (terminal_sensor->sd) {
5749	6153	ret = v4l2_subdev_call(terminal_sensor->sd,
5750	6154	core, ioctl,
..	..	@@ -5775,6 +6179,39 @@
5775	6179	goto destroy_buf;
5776	6180
5777	6181	mutex_lock(&hw_dev->dev_lock);
	6182	+ if (atomic_read(&dev->pipe.stream_cnt) == 0 &&
	6183	+ dev->active_sensor &&
	6184	+ (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	6185	+ dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY \|\|
	6186	+ dev->active_sensor->mbus.type == V4L2_MBUS_CCP2)) {
	6187	+ if (dev->channels[0].capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	6188	+ csi_info.csi_num = dev->channels[0].capture_info.multi_dev.dev_num;
	6189	+ if (csi_info.csi_num > RKCIF_MAX_CSI_NUM) {
	6190	+ v4l2_err(v4l2_dev,
	6191	+ "csi num %d, max %d\n",
	6192	+ csi_info.csi_num, RKCIF_MAX_CSI_NUM);
	6193	+ goto out;
	6194	+ }
	6195	+ for (i = 0; i < csi_info.csi_num; i++) {
	6196	+ csi_info.csi_idx[i] = dev->channels[0].capture_info.multi_dev.dev_idx[i];
	6197	+ if (dev->hw_dev->is_rk3588s2)
	6198	+ v4l2_info(v4l2_dev, "rk3588s2 combine mode attach to mipi%d\n",
	6199	+ csi_info.csi_idx[i]);
	6200	+ }
	6201	+ } else {
	6202	+ csi_info.csi_num = 1;
	6203	+ dev->csi_host_idx = dev->csi_host_idx_def;
	6204	+ csi_info.csi_idx[0] = dev->csi_host_idx;
	6205	+ }
	6206	+ ret = v4l2_subdev_call(dev->active_sensor->sd,
	6207	+ core, ioctl,
	6208	+ RKCIF_CMD_SET_CSI_IDX,
	6209	+ &csi_info);
	6210	+ if (ret)
	6211	+ v4l2_err(&dev->v4l2_dev, "set csi idx %d fail\n", dev->csi_host_idx);
	6212	+
	6213	+ }
	6214	+
5778	6215	if (((dev->active_sensor && dev->active_sensor->mbus.type == V4L2_MBUS_BT656) \|\|
5779	6216	dev->is_use_dummybuf) &&
5780	6217	(!dev->hw_dev->dummy_buf.vaddr) &&
..	..	@@ -5788,8 +6225,10 @@
5788	6225	}
5789	6226	mutex_unlock(&hw_dev->dev_lock);
5790	6227
5791		- if (stream->cur_stream_mode == RKCIF_STREAM_MODE_NONE) {
	6228	+ if (mode == RKCIF_STREAM_MODE_CAPTURE)
5792	6229	tasklet_enable(&stream->vb_done_tasklet);
	6230	+
	6231	+ if (stream->cur_stream_mode == RKCIF_STREAM_MODE_NONE) {
5793	6232	ret = dev->pipe.open(&dev->pipe, &node->vdev.entity, true);
5794	6233	if (ret < 0) {
5795	6234	v4l2_err(v4l2_dev, "open cif pipeline failed %d\n",
..	..	@@ -5807,7 +6246,7 @@
5807	6246	rkmodule_stream_seq == RKMODULE_START_STREAM_FRONT) {
5808	6247	ret = dev->pipe.set_stream(&dev->pipe, true);
5809	6248	if (ret < 0)
5810		- goto runtime_put;
	6249	+ goto destroy_buf;
5811	6250	}
5812	6251	}
5813	6252	if (dev->chip_id >= CHIP_RK1808_CIF) {
..	..	@@ -5823,7 +6262,7 @@
5823	6262	}
5824	6263
5825	6264	if (ret < 0)
5826		- goto runtime_put;
	6265	+ goto destroy_buf;
5827	6266
5828	6267	if (stream->cur_stream_mode == RKCIF_STREAM_MODE_NONE) {
5829	6268	ret = media_pipeline_start(&node->vdev.entity, &dev->pipe.pipe);
..	..	@@ -5869,15 +6308,19 @@
5869	6308	rkcif_stream_stop(stream);
5870	6309	pipe_stream_off:
5871	6310	dev->pipe.set_stream(&dev->pipe, false);
5872		-runtime_put:
5873		- pm_runtime_put_sync(dev->dev);
	6311	+
5874	6312	destroy_buf:
5875		- if (stream->next_buf)
5876		- vb2_buffer_done(&stream->next_buf->vb.vb2_buf,
5877		- VB2_BUF_STATE_QUEUED);
	6313	+ if (mode == RKCIF_STREAM_MODE_CAPTURE)
	6314	+ tasklet_disable(&stream->vb_done_tasklet);
5878	6315	if (stream->curr_buf)
5879		- vb2_buffer_done(&stream->curr_buf->vb.vb2_buf,
5880		- VB2_BUF_STATE_QUEUED);
	6316	+ list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
	6317	+ if (stream->next_buf &&
	6318	+ stream->next_buf != stream->curr_buf)
	6319	+ list_add_tail(&stream->next_buf->queue, &stream->buf_head);
	6320	+
	6321	+ stream->curr_buf = NULL;
	6322	+ stream->next_buf = NULL;
	6323	+ atomic_set(&stream->buf_cnt, 0);
5881	6324	while (!list_empty(&stream->buf_head)) {
5882	6325	struct rkcif_buffer *buf;
5883	6326
..	..	@@ -5942,6 +6385,7 @@
5942	6385	bool try)
5943	6386	{
5944	6387	struct rkcif_device *dev = stream->cifdev;
	6388	+ struct sditf_priv *priv = dev->sditf[0];
5945	6389	const struct cif_output_fmt *fmt;
5946	6390	const struct cif_input_fmt *cif_fmt_in = NULL;
5947	6391	struct v4l2_rect input_rect;
..	..	@@ -5949,6 +6393,7 @@
5949	6393	u32 xsubs = 1, ysubs = 1, i;
5950	6394	struct rkmodule_hdr_cfg hdr_cfg;
5951	6395	struct rkcif_extend_info *extend_line = &stream->extend_line;
	6396	+ struct csi_channel_info *channel_info = &dev->channels[stream->id];
5952	6397	int ret;
5953	6398
5954	6399	for (i = 0; i < RKCIF_MAX_PLANE; i++)
..	..	@@ -5962,9 +6407,9 @@
5962	6407	input_rect.height = RKCIF_DEFAULT_HEIGHT;
5963	6408
5964	6409	if (dev->terminal_sensor.sd) {
5965		- cif_fmt_in = get_input_fmt(dev->terminal_sensor.sd,
5966		- &input_rect, stream->id,
5967		- &dev->channels[stream->id]);
	6410	+ cif_fmt_in = rkcif_get_input_fmt(dev,
	6411	+ &input_rect, stream->id,
	6412	+ channel_info);
5968	6413	stream->cif_fmt_in = cif_fmt_in;
5969	6414	} else {
5970	6415	v4l2_err(&stream->cifdev->v4l2_dev,
..	..	@@ -6006,8 +6451,9 @@
6006	6451
6007	6452	planes = fmt->cplanes ? fmt->cplanes : fmt->mplanes;
6008	6453
6009		- if (cif_fmt_in && (cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8 \|\|
6010		- cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8))
	6454	+ if (cif_fmt_in &&
	6455	+ (cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8 \|\|
	6456	+ cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8))
6011	6457	stream->crop_enable = false;
6012	6458
6013	6459	for (i = 0; i < planes; i++) {
..	..	@@ -6032,7 +6478,7 @@
6032	6478	}
6033	6479	}
6034	6480
6035		- if (dev->sditf_cnt > 1 && dev->sditf_cnt <= RKCIF_MAX_SDITF)
	6481	+ if (priv && priv->is_combine_mode && dev->sditf_cnt <= RKCIF_MAX_SDITF)
6036	6482	height *= dev->sditf_cnt;
6037	6483
6038	6484	extend_line->pixm.height = height + RKMODULE_EXTEND_LINE;
..	..	@@ -6042,8 +6488,9 @@
6042	6488	* to optimize reading and writing of ddr, aliged with 256.
6043	6489	*/
6044	6490	if (fmt->fmt_type == CIF_FMT_TYPE_RAW &&
6045		- (stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8 \|\|
6046		- stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8)) {
	6491	+ cif_fmt_in &&
	6492	+ (cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8 \|\|
	6493	+ cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8)) {
6047	6494	stream->is_compact = false;
6048	6495	}
6049	6496
..	..	@@ -6157,6 +6604,7 @@
6157	6604
6158	6605	stream->is_high_align = false;
6159	6606	stream->is_finish_stop_dma = false;
	6607	+ stream->is_wait_dma_stop = false;
6160	6608
6161	6609	if (dev->chip_id == CHIP_RV1126_CIF \|\|
6162	6610	dev->chip_id == CHIP_RV1126_CIF_LITE)
..	..	@@ -6184,6 +6632,7 @@
6184	6632	stream->buf_owner = 0;
6185	6633	stream->buf_replace_cnt = 0;
6186	6634	stream->is_stop_capture = false;
	6635	+ atomic_set(&stream->buf_cnt, 0);
6187	6636	}
6188	6637
6189	6638	static int rkcif_fh_open(struct file *filp)
..	..	@@ -6329,9 +6778,9 @@
6329	6778	input_rect.height = RKCIF_DEFAULT_HEIGHT;
6330	6779
6331	6780	if (dev->terminal_sensor.sd)
6332		- get_input_fmt(dev->terminal_sensor.sd,
6333		- &input_rect, stream->id,
6334		- &csi_info);
	6781	+ rkcif_get_input_fmt(dev,
	6782	+ &input_rect, stream->id,
	6783	+ &csi_info);
6335	6784
6336	6785	if (dev->hw_dev->adapt_to_usbcamerahal) {
6337	6786	fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
..	..	@@ -6410,7 +6859,7 @@
6410	6859	return -EINVAL;
6411	6860
6412	6861	if (dev->terminal_sensor.sd) {
6413		- cif_fmt_in = get_input_fmt(dev->terminal_sensor.sd,
	6862	+ cif_fmt_in = rkcif_get_input_fmt(dev,
6414	6863	&input_rect, stream->id,
6415	6864	&dev->channels[stream->id]);
6416	6865	stream->cif_fmt_in = cif_fmt_in;
..	..	@@ -6796,8 +7245,8 @@
6796	7245	break;
6797	7246	case RKCIF_CMD_SET_CSI_MEMORY_MODE:
6798	7247	if (dev->terminal_sensor.sd) {
6799		- in_fmt = get_input_fmt(dev->terminal_sensor.sd,
6800		- &rect, 0, &csi_info);
	7248	+ in_fmt = rkcif_get_input_fmt(dev,
	7249	+ &rect, 0, &csi_info);
6801	7250	if (in_fmt == NULL) {
6802	7251	v4l2_err(&dev->v4l2_dev, "can't get sensor input format\n");
6803	7252	return -EINVAL;
..	..	@@ -6876,6 +7325,7 @@
6876	7325	v4l2_dbg(2, rkcif_debug, &stream->cifdev->v4l2_dev,
6877	7326	"stream[%d] vb done, index: %d, sequence %d\n", stream->id,
6878	7327	vb_done->vb2_buf.index, vb_done->sequence);
	7328	+ atomic_dec(&stream->buf_cnt);
6879	7329	}
6880	7330
6881	7331	static void rkcif_tasklet_handle(unsigned long data)
..	..	@@ -8147,7 +8597,11 @@
8147	8597
8148	8598	if (active_buf) {
8149	8599	vb_done = &active_buf->vb;
8150		- vb_done->vb2_buf.timestamp = stream->readout.fs_timestamp;
	8600	+ if (cif_dev->chip_id < CHIP_RK3588_CIF &&
	8601	+ cif_dev->active_sensor->mbus.type == V4L2_MBUS_BT656)
	8602	+ vb_done->vb2_buf.timestamp = stream->readout.fe_timestamp;
	8603	+ else
	8604	+ vb_done->vb2_buf.timestamp = stream->readout.fs_timestamp;
8151	8605	vb_done->sequence = stream->frame_idx - 1;
8152	8606	active_buf->fe_timestamp = ktime_get_ns();
8153	8607	if (stream->is_line_wake_up) {
..	..	@@ -8308,8 +8762,10 @@
8308	8762	spin_lock_irqsave(&priv->cif_dev->buffree_lock, flags);
8309	8763	for (i = 0; i < priv->buf_num; i++) {
8310	8764	rx_buf = &stream->rx_buf[i];
8311		- if (rx_buf && (!rx_buf->dummy.is_free) && rx_buf != buf)
	8765	+ if (rx_buf && (!rx_buf->dummy.is_free) && rx_buf != buf) {
8312	8766	list_add_tail(&rx_buf->list_free, &priv->buf_free_list);
	8767	+ stream->total_buf_num--;
	8768	+ }
8313	8769	}
8314	8770	spin_unlock_irqrestore(&priv->cif_dev->buffree_lock, flags);
8315	8771	schedule_work(&priv->buffree_work.work);
..	..	@@ -8379,11 +8835,13 @@
8379	8835	active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
8380	8836	active_buf->fe_timestamp = ktime_get_ns();
8381	8837	stream->last_frame_idx = stream->frame_idx;
8382		- if (stream->cifdev->hdr.hdr_mode == NO_HDR)
	8838	+ if (stream->cifdev->hdr.hdr_mode == NO_HDR) {
8383	8839	rkcif_s_rx_buffer(stream->cifdev, &active_buf->dbufs);
8384		- else
	8840	+ if (stream->cifdev->is_support_tools && stream->tools_vdev)
	8841	+ rkcif_rdbk_with_tools(stream, active_buf);
	8842	+ } else {
8385	8843	rkcif_rdbk_frame_end_toisp(stream, active_buf);
8386		- stream->buf_num_toisp--;
	8844	+ }
8387	8845	}
8388	8846	}
8389	8847	}
..	..	@@ -8455,8 +8913,8 @@
8455	8913
8456	8914	if (!stream->is_line_wake_up) {
8457	8915	ret = rkcif_assign_new_buffer_pingpong(stream,
8458		- RKCIF_YUV_ADDR_STATE_UPDATE,
8459		- mipi_id);
	8916	+ RKCIF_YUV_ADDR_STATE_UPDATE,
	8917	+ mipi_id);
8460	8918	if (ret && cif_dev->chip_id < CHIP_RK3588_CIF)
8461	8919	return;
8462	8920	} else {
..	..	@@ -8464,6 +8922,10 @@
8464	8922	if (ret && cif_dev->chip_id < CHIP_RK3588_CIF)
8465	8923	return;
8466	8924	}
	8925	+ if (cif_dev->chip_id < CHIP_RK3588_CIF &&
	8926	+ cif_dev->active_sensor->mbus.type == V4L2_MBUS_BT656 &&
	8927	+ stream->id != 0)
	8928	+ stream->frame_idx++;
8467	8929	if (!stream->is_line_wake_up && stream->dma_en & RKCIF_DMAEN_BY_VICAP)
8468	8930	rkcif_buf_done_prepare(stream, active_buf, mipi_id, 0);
8469	8931
..	..	@@ -8590,6 +9052,7 @@
8590	9052	struct rkcif_sensor_info *terminal_sensor = &cif_dev->terminal_sensor;
8591	9053	struct rkcif_resume_info *resume_info = &cif_dev->reset_work.resume_info;
8592	9054	struct rkcif_timer *timer = &cif_dev->reset_watchdog_timer;
	9055	+ struct sditf_priv *priv = cif_dev->sditf[0];
8593	9056	int i, j, ret = 0;
8594	9057	u32 on, sof_cnt;
8595	9058	int capture_mode = 0;
..	..	@@ -8658,10 +9121,12 @@
8658	9121	__func__, on ? "on" : "off", p->subdevs[i]->name);
8659	9122	}
8660	9123
8661		- for (i = 0; i < cif_dev->sditf_cnt; i++) {
8662		- if (cif_dev->sditf[i] && cif_dev->sditf[i]->sensor_sd)
8663		- ret = v4l2_subdev_call(cif_dev->sditf[i]->sensor_sd, core, ioctl,
8664		- RKMODULE_SET_QUICK_STREAM, &on);
	9124	+ if (priv && priv->is_combine_mode && cif_dev->sditf_cnt <= RKCIF_MAX_SDITF) {
	9125	+ for (i = 0; i < cif_dev->sditf_cnt; i++) {
	9126	+ if (cif_dev->sditf[i] && cif_dev->sditf[i]->sensor_sd)
	9127	+ ret = v4l2_subdev_call(cif_dev->sditf[i]->sensor_sd, core, ioctl,
	9128	+ RKMODULE_SET_QUICK_STREAM, &on);
	9129	+ }
8665	9130	}
8666	9131
8667	9132	rockchip_clear_system_status(SYS_STATUS_CIF0);
..	..	@@ -8756,10 +9221,12 @@
8756	9221	p->subdevs[i]->name);
8757	9222	}
8758	9223
8759		- for (i = 0; i < cif_dev->sditf_cnt; i++) {
8760		- if (cif_dev->sditf[i] && cif_dev->sditf[i]->sensor_sd)
8761		- v4l2_subdev_call(cif_dev->sditf[i]->sensor_sd, core, ioctl,
8762		- RKMODULE_SET_QUICK_STREAM, &on);
	9224	+ if (priv && priv->is_combine_mode && cif_dev->sditf_cnt <= RKCIF_MAX_SDITF) {
	9225	+ for (i = 0; i < cif_dev->sditf_cnt; i++) {
	9226	+ if (cif_dev->sditf[i] && cif_dev->sditf[i]->sensor_sd)
	9227	+ v4l2_subdev_call(cif_dev->sditf[i]->sensor_sd, core, ioctl,
	9228	+ RKMODULE_SET_QUICK_STREAM, &on);
	9229	+ }
8763	9230	}
8764	9231
8765	9232	if (cif_dev->chip_id < CHIP_RK3588_CIF)
..	..	@@ -9437,6 +9904,11 @@
9437	9904	rkcif_write_register(cif_dev, CIF_REG_DVP_CTRL, val);
9438	9905	}
9439	9906	stream->to_stop_dma = 0;
	9907	+ v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
	9908	+ "stream[%d] replace_cnt %d, y_addr 0x%x, 0x%x\n",
	9909	+ stream->id, stream->buf_replace_cnt,
	9910	+ rkcif_read_register(cif_dev, get_reg_index_of_frm0_y_addr(stream->id)),
	9911	+ rkcif_read_register(cif_dev, get_reg_index_of_frm1_y_addr(stream->id)));
9440	9912	return 0;
9441	9913	}
9442	9914
..	..	@@ -9616,15 +10088,16 @@
9616	10088
9617	10089	sync_config = &hw->sync_config[cif_dev->sync_cfg.group];
9618	10090	sync_config->sync_code \|= BIT(cif_dev->csi_host_idx);
9619		- if (sync_config->sync_code != sync_config->sync_mask)
9620		- return -EINVAL;
9621		-
9622	10091	v4l2_dbg(3, rkcif_debug, &cif_dev->v4l2_dev,
9623		- "sync code 0x%x, mask 0x%x, update 0x%x, cache 0x%x\n",
	10092	+ "sync code 0x%x, mask 0x%x, update 0x%x, cache 0x%x, timestamp %llu\n",
9624	10093	sync_config->sync_code,
9625	10094	sync_config->sync_mask,
9626	10095	sync_config->update_code,
9627		- sync_config->update_cache);
	10096	+ sync_config->update_cache,
	10097	+ detect_stream->readout.fs_timestamp);
	10098	+
	10099	+ if (sync_config->sync_code != sync_config->sync_mask)
	10100	+ return -EINVAL;
9628	10101
9629	10102	for (i = 0; i < sync_config->dev_cnt; i++) {
9630	10103	if (sync_config->mode == RKCIF_MASTER_MASTER) {
..	..	@@ -9973,7 +10446,12 @@
9973	10446	stream->frame_idx - 1,
9974	10447	stream->frame_phase,
9975	10448	ktime_get_ns());
9976		-
	10449	+ if (stream->is_finish_stop_dma && stream->is_wait_dma_stop) {
	10450	+ stream->is_wait_dma_stop = false;
	10451	+ wake_up(&stream->wq_stopped);
	10452	+ stream->is_finish_stop_dma = false;
	10453	+ continue;
	10454	+ }
9977	10455	if (stream->crop_dyn_en)
9978	10456	rkcif_dynamic_crop(stream);
9979	10457
..	..	@@ -9982,11 +10460,20 @@
9982	10460	is_update = true;
9983	10461	else
9984	10462	is_update = rkcif_check_buffer_prepare(stream);
	10463	+ v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
	10464	+ "dma capture by vicap, is_updata %d, group mode %d, dma_en %d\n",
	10465	+ is_update, cif_dev->sync_cfg.type, stream->dma_en);
9985	10466	if (is_update)
9986	10467	rkcif_update_stream(cif_dev, stream, mipi_id);
9987	10468	} else if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
	10469	+ v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
	10470	+ "dma capture by isp, dma_en 0x%x\n",
	10471	+ stream->dma_en);
9988	10472	rkcif_update_stream_toisp(cif_dev, stream, mipi_id);
9989	10473	} else if (stream->dma_en & RKCIF_DMAEN_BY_ROCKIT) {
	10474	+ v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
	10475	+ "dma capture by rockit, dma_en 0x%x\n",
	10476	+ stream->dma_en);
9990	10477	rkcif_update_stream_rockit(cif_dev, stream, mipi_id);
9991	10478	}
9992	10479
..	..	@@ -10003,11 +10490,10 @@
10003	10490	}
10004	10491
10005	10492	spin_lock_irqsave(&stream->vbq_lock, flags);
10006		- if (stream->is_finish_stop_dma) {
10007		- wake_up(&stream->wq_stopped);
10008		- stream->is_finish_stop_dma = false;
10009		- }
10010	10493	if (!(stream->dma_en & RKCIF_DMAEN_BY_ISP) && stream->lack_buf_cnt == 2) {
	10494	+ v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
	10495	+ "stream[%d] to stop dma, lack_buf_cnt %d\n",
	10496	+ stream->id, stream->lack_buf_cnt);
10011	10497	stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
10012	10498	rkcif_stop_dma_capture(stream);
10013	10499	}