kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/drivers/media/i2c/rk628/rk628_mipi_dphy.h
..
..
@@ -18,6 +18,9 @@
18
18
 
19
19
 /* Test Code: 0x44 (HS RX Control of Lane 0) */
20
20
 #define HSFREQRANGE(x)			UPDATE(x, 6, 1)
21
+#define HSTX(x)				UPDATE(x, 6, 0)
22
+#define HSZERO(x)			UPDATE(x, 5, 0)
23
+#define HSPOST(x)			UPDATE(x, 4, 0)
21
24
 
22
25
 static inline void testif_testclk_assert(struct rk628 *rk628)
23
26
 {
..
..
@@ -189,6 +192,40 @@
189
192
 	testif_write(rk628, 0x44, HSFREQRANGE(hsfreqrange));
190
193
 }
191
194
 
195
+static void __maybe_unused mipi_dphy_init_hsmanual(struct rk628 *rk628, bool manual)
196
+{
197
+	if (manual) {
198
+		//config mipi timing when mipi freq is 1250Mbps
199
+		testif_write(rk628, 0x71, HSTX(0x4a) | BIT(7));
200
+		usleep_range(1500, 2000);
201
+		testif_write(rk628, 0x72, HSZERO(0xf) | BIT(6));
202
+		usleep_range(1500, 2000);
203
+		testif_write(rk628, 0x73, HSTX(0x5d) | BIT(7));
204
+		usleep_range(1500, 2000);
205
+		testif_write(rk628, 0x61, HSTX(0x3a) | BIT(7));
206
+		usleep_range(1500, 2000);
207
+		testif_write(rk628, 0x62, HSZERO(0x3a) | BIT(6));
208
+		usleep_range(1500, 2000);
209
+		testif_write(rk628, 0x63, HSTX(0x5a) | BIT(7));
210
+		usleep_range(1500, 2000);
211
+		testif_write(rk628, 0x65, HSPOST(0x1f) | BIT(5));
212
+	} else {
213
+		testif_write(rk628, 0x71, 0);
214
+		usleep_range(1500, 2000);
215
+		testif_write(rk628, 0x72, 0);
216
+		usleep_range(1500, 2000);
217
+		testif_write(rk628, 0x73, 0);
218
+		usleep_range(1500, 2000);
219
+		testif_write(rk628, 0x61, 0);
220
+		usleep_range(1500, 2000);
221
+		testif_write(rk628, 0x62, 0);
222
+		usleep_range(1500, 2000);
223
+		testif_write(rk628, 0x63, 0);
224
+		usleep_range(1500, 2000);
225
+		testif_write(rk628, 0x65, 0);
226
+	}
227
+}
228
+
192
229
 static inline int mipi_dphy_reset(struct rk628 *rk628)
193
230
 {
194
231
 	u32 val, mask;