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2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f 
 kernel/drivers/media/i2c/gc2093.c
....@@ -82,6 +82,8 @@
8282 
8383 #define GC2093_LANES		2
8484 
85
+#define OF_CAMERA_HDR_MODE		"rockchip,camera-hdr-mode"
86
+
8587 static const char * const gc2093_supply_names[] = {
8688 	"dovdd",    /* Digital I/O power */
8789 	"avdd",     /* Analog power */
....@@ -142,7 +144,6 @@
142144 	struct mutex        lock;
143145 	bool		    streaming;
144146 	bool		    power_on;
145
-	unsigned int        cfg_num;
146147 	const struct gc2093_mode *cur_mode;
147148 
148149 	u32		module_index;
....@@ -421,6 +422,138 @@
421422 	{0x024d, 0x01},
422423 };
423424 
425
+/*
426
+ * window size=1920*1080 mipi@2lane
427
+ * mclk=27M mipi_clk=792Mbps
428
+ * pixel_line_total=2640 line_frame_total=1500
429
+ * row_time=20us frame_rate=50fps
430
+ */
431
+static const struct reg_sequence gc2093_1080p_25fps_hdr_settings[] = {
432
+	/* System */
433
+	{0x03fe, 0x80},
434
+	{0x03fe, 0x80},
435
+	{0x03fe, 0x80},
436
+	{0x03fe, 0x00},
437
+	{0x03f2, 0x00},
438
+	{0x03f3, 0x00},
439
+	{0x03f4, 0x36},
440
+	{0x03f5, 0xc0},
441
+	{0x03f6, 0x0B},
442
+	{0x03f7, 0x01},
443
+	{0x03f8, 0x58},
444
+	{0x03f9, 0x40},
445
+	{0x03fc, 0x8e},
446
+	/* Cisctl & Analog */
447
+	{0x0087, 0x18},
448
+	{0x00ee, 0x30},
449
+	{0x00d0, 0xbf},
450
+	{0x01a0, 0x00},
451
+	{0x01a4, 0x40},
452
+	{0x01a5, 0x40},
453
+	{0x01a6, 0x40},
454
+	{0x01af, 0x09},
455
+	{0x0001, 0x00},
456
+	{0x0002, 0x02},
457
+	{0x0003, 0x04},
458
+	{0x0004, 0x02},
459
+	{0x0005, 0x02},
460
+	{0x0006, 0x94},
461
+	{0x0007, 0x00},
462
+	{0x0008, 0x11},
463
+	{0x0009, 0x00},
464
+	{0x000a, 0x02},
465
+	{0x000b, 0x00},
466
+	{0x000c, 0x04},
467
+	{0x000d, 0x04},
468
+	{0x000e, 0x40},
469
+	{0x000f, 0x07},
470
+	{0x0010, 0x8c},
471
+	{0x0013, 0x15},
472
+	{0x0019, 0x0c},
473
+	{0x0041, 0x05},
474
+	{0x0042, 0xdc},
475
+	{0x0053, 0x60},
476
+	{0x008d, 0x92},
477
+	{0x0090, 0x00},
478
+	{0x00c7, 0xe1},
479
+	{0x001b, 0x73},
480
+	{0x0028, 0x0d},
481
+	{0x0029, 0x24},
482
+	{0x002b, 0x04},
483
+	{0x002e, 0x23},
484
+	{0x0037, 0x03},
485
+	{0x0043, 0x04},
486
+	{0x0044, 0x20},
487
+	{0x004a, 0x01},
488
+	{0x004b, 0x20},
489
+	{0x0055, 0x30},
490
+	{0x006b, 0x44},
491
+	{0x0077, 0x00},
492
+	{0x0078, 0x20},
493
+	{0x007c, 0xa1},
494
+	{0x00d3, 0xd4},
495
+	{0x00e6, 0x50},
496
+	/* Gain */
497
+	{0x00b6, 0xc0},
498
+	{0x00b0, 0x60},
499
+	/* Isp */
500
+	{0x0102, 0x89},
501
+	{0x0104, 0x01},
502
+	{0x010e, 0x01},
503
+	{0x0158, 0x00},
504
+	{0x0183, 0x01},
505
+	{0x0187, 0x50},
506
+	/* Dark sun*/
507
+	{0x0123, 0x08},
508
+	{0x0123, 0x00},
509
+	{0x0120, 0x01},
510
+	{0x0121, 0x00},
511
+	{0x0122, 0x10},
512
+	{0x0124, 0x03},
513
+	{0x0125, 0xff},
514
+	{0x0126, 0x3c},
515
+	{0x001a, 0x8c},
516
+	{0x00c6, 0xe0},
517
+	/* Blk */
518
+	{0x0026, 0x30},
519
+	{0x0142, 0x00},
520
+	{0x0149, 0x1e},
521
+	{0x014a, 0x0f},
522
+	{0x014b, 0x00},
523
+	{0x0155, 0x00},
524
+	{0x0414, 0x78},
525
+	{0x0415, 0x78},
526
+	{0x0416, 0x78},
527
+	{0x0417, 0x78},
528
+	{0x0454, 0x78},
529
+	{0x0455, 0x78},
530
+	{0x0456, 0x78},
531
+	{0x0457, 0x78},
532
+	{0x04e0, 0x18},
533
+	/* Window */
534
+	{0x0192, 0x02},
535
+	{0x0194, 0x03},
536
+	{0x0195, 0x04},
537
+	{0x0196, 0x38},
538
+	{0x0197, 0x07},
539
+	{0x0198, 0x80},
540
+	/* MIPI */
541
+	{0x019a, 0x06},
542
+	{0x007b, 0x2a},
543
+	{0x0023, 0x2d},
544
+	{0x0201, 0x27},
545
+	{0x0202, 0x56},
546
+	{0x0203, 0xb6},
547
+	{0x0212, 0x80},
548
+	{0x0213, 0x07},
549
+	{0x0215, 0x12},
550
+	{0x003e, 0x91},
551
+	/* HDR En */
552
+	{0x0027, 0x71},
553
+	{0x0215, 0x92},
554
+	{0x024d, 0x01},
555
+};
556
+
424557 static const struct gc2093_mode supported_modes[] = {
425558 	{
426559 		.width = 1920,
....@@ -451,6 +584,25 @@
451584 		.link_freq_index = LINK_FREQ_396M_INDEX,
452585 		.reg_list = gc2093_1080p_hdr_settings,
453586 		.reg_num = ARRAY_SIZE(gc2093_1080p_hdr_settings),
587
+		.hdr_mode = HDR_X2,
588
+		.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
589
+		.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
590
+		.vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
591
+		.vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
592
+	},
593
+	{
594
+		.width = 1920,
595
+		.height = 1080,
596
+		.max_fps = {
597
+			.numerator = 10000,
598
+			.denominator = 250000,
599
+		},
600
+		.exp_def = 0x460,
601
+		.hts_def = 0xa50,
602
+		.vts_def = 0x5dc,
603
+		.link_freq_index = LINK_FREQ_396M_INDEX,
604
+		.reg_list = gc2093_1080p_25fps_hdr_settings,
605
+		.reg_num = ARRAY_SIZE(gc2093_1080p_25fps_hdr_settings),
454606 		.hdr_mode = HDR_X2,
455607 		.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
456608 		.vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
....@@ -585,6 +737,7 @@
585737 
586738 	switch (ctrl->id) {
587739 	case V4L2_CID_EXPOSURE:
740
+		dev_dbg(gc2093->dev, "set exposure value 0x%x\n", ctrl->val);
588741 		if (gc2093->cur_mode->hdr_mode != NO_HDR)
589742 			goto ctrl_end;
590743 		dev_dbg(gc2093->dev, "set exposure value 0x%x\n", ctrl->val);
....@@ -594,29 +747,36 @@
594747 					ctrl->val & 0xff);
595748 		break;
596749 	case V4L2_CID_ANALOGUE_GAIN:
750
+		dev_dbg(gc2093->dev, "set gain value 0x%x, mode: %d\n",
751
+				ctrl->val, gc2093->cur_mode->hdr_mode);
597752 		if (gc2093->cur_mode->hdr_mode != NO_HDR)
598753 			goto ctrl_end;
599754 		dev_dbg(gc2093->dev, "set gain value 0x%x\n", ctrl->val);
600755 		gc2093_set_gain(gc2093, ctrl->val);
601756 		break;
602757 	case V4L2_CID_VBLANK:
758
+		dev_dbg(gc2093->dev, "set blank value 0x%x\n", ctrl->val);
603759 		vts = gc2093->cur_mode->height + ctrl->val;
604760 		gc2093->cur_vts = vts;
605761 		ret = gc2093_write_reg(gc2093, GC2093_REG_VTS_H,
606762 				       (vts >> 8) & 0x3f);
607763 		ret |= gc2093_write_reg(gc2093, GC2093_REG_VTS_L,
608764 					vts & 0xff);
765
+		if (!ret)
766
+			gc2093->cur_vts = ctrl->val + gc2093->cur_mode->height;
609767 		if (gc2093->cur_vts != gc2093->cur_mode->vts_def)
610768 			gc2093_modify_fps_info(gc2093);
611769 		dev_dbg(gc2093->dev, " set blank value 0x%x\n", ctrl->val);
612770 		break;
613771 	case V4L2_CID_HFLIP:
614
-			regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG,
615
-					   MIRROR_MASK, ctrl->val ? MIRROR_MASK : 0);
772
+		dev_dbg(gc2093->dev, "set hflip 0x%x\n", ctrl->val);
773
+		regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG,
774
+				   MIRROR_MASK, ctrl->val ? MIRROR_MASK : 0);
616775 		break;
617776 	case V4L2_CID_VFLIP:
618
-			regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG,
619
-					   FLIP_MASK,  ctrl->val ? FLIP_MASK : 0);
777
+		dev_dbg(gc2093->dev, "set vflip 0x%x\n", ctrl->val);
778
+		regmap_update_bits(gc2093->regmap, GC2093_MIRROR_FLIP_REG,
779
+				   FLIP_MASK,  ctrl->val ? FLIP_MASK : 0);
620780 		break;
621781 	default:
622782 		dev_warn(gc2093->dev, "%s Unhandled id:0x%x, val:0x%x\n",
....@@ -673,7 +833,7 @@
673833 					   h_blank, h_blank, 1, h_blank);
674834 	if (gc2093->hblank)
675835 		gc2093->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
676
-
836
+	gc2093->cur_fps = mode->max_fps;
677837 	vblank_def = mode->vts_def - mode->height;
678838 	gc2093->cur_vts = mode->vts_def;
679839 	gc2093->vblank = v4l2_ctrl_new_std(handler, &gc2093_ctrl_ops,
....@@ -820,11 +980,24 @@
820980 	strlcpy(inf->base.module, gc2093->module_name, sizeof(inf->base.module));
821981 }
822982 
983
+static int gc2093_get_channel_info(struct gc2093 *gc2093,
984
+				   struct rkmodule_channel_info *ch_info)
985
+{
986
+	if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
987
+		return -EINVAL;
988
+	ch_info->vc = gc2093->cur_mode->vc[ch_info->index];
989
+	ch_info->width = gc2093->cur_mode->width;
990
+	ch_info->height = gc2093->cur_mode->height;
991
+	ch_info->bus_fmt = GC2093_MEDIA_BUS_FMT;
992
+	return 0;
993
+}
994
+
823995 static long gc2093_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
824996 {
825997 	struct gc2093 *gc2093 = to_gc2093(sd);
826998 	struct preisp_hdrae_exp_s *hdrae_exp = arg;
827999 	struct rkmodule_hdr_cfg *hdr_cfg;
1000
+	struct rkmodule_channel_info *ch_info;
8281001 	long ret = 0;
8291002 	u32 i, h, w;
8301003 	u32 stream = 0;
....@@ -914,15 +1087,18 @@
9141087 		hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
9151088 		w = gc2093->cur_mode->width;
9161089 		h = gc2093->cur_mode->height;
917
-		for (i = 0; i < gc2093->cfg_num; i++) {
1090
+		for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
9181091 			if (w == supported_modes[i].width &&
9191092 			h == supported_modes[i].height &&
9201093 			supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) {
9211094 				gc2093->cur_mode = &supported_modes[i];
9221095 				break;
9231096 			}
1097
+			dev_err(gc2093->dev, "i:%d,w:%d, h:%d, hdr:%d\n",
1098
+					i, supported_modes[i].width, supported_modes[i].height,
1099
+					supported_modes[i].hdr_mode);
9241100 		}
925
-		if (i == gc2093->cfg_num) {
1101
+		if (i == ARRAY_SIZE(supported_modes)) {
9261102 			dev_err(gc2093->dev, "not find hdr mode:%d %dx%d config\n",
9271103 				hdr_cfg->hdr_mode, w, h);
9281104 			ret = -EINVAL;
....@@ -958,6 +1134,10 @@
9581134 			usleep_range(delay_us, delay_us + 2000);
9591135 		}
9601136 		break;
1137
+	case RKMODULE_GET_CHANNEL_INFO:
1138
+		ch_info = (struct rkmodule_channel_info *)arg;
1139
+		ret = gc2093_get_channel_info(gc2093, ch_info);
1140
+		break;
9611141 	default:
9621142 		ret = -ENOIOCTLCMD;
9631143 		break;
....@@ -990,8 +1170,16 @@
9901170 			}
9911171 		}
9921172 	}
1173
+	dev_info(gc2093->dev,
1174
+		 "%dx%d@%d, mode %d, vts 0x%x\n",
1175
+		 gc2093->cur_mode->width,
1176
+		 gc2093->cur_mode->height,
1177
+		 gc2093->cur_fps.denominator / gc2093->cur_fps.numerator,
1178
+		 gc2093->cur_mode->hdr_mode,
1179
+		 gc2093->cur_vts);
1180
+	dev_info(gc2093->dev, "is_tb:%d\n", gc2093->is_thunderboot);
9931181 	return gc2093_write_reg(gc2093, GC2093_REG_CTRL_MODE,
994
-				GC2093_MODE_STREAMING);
1182
+							GC2093_MODE_STREAMING);
9951183 }
9961184 
9971185 static int __gc2093_stop_stream(struct gc2093 *gc2093)
....@@ -1013,6 +1201,7 @@
10131201 	struct rkmodule_inf *inf;
10141202 	struct rkmodule_hdr_cfg *hdr;
10151203 	struct preisp_hdrae_exp_s *hdrae;
1204
+	struct rkmodule_channel_info *ch_info;
10161205 	long ret = 0;
10171206 	u32 stream = 0;
10181207 
....@@ -1082,6 +1271,21 @@
10821271 		else
10831272 			ret = -EFAULT;
10841273 		break;
1274
+	case RKMODULE_GET_CHANNEL_INFO:
1275
+		ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
1276
+		if (!ch_info) {
1277
+			ret = -ENOMEM;
1278
+			return ret;
1279
+		}
1280
+
1281
+		ret = gc2093_ioctl(sd, cmd, ch_info);
1282
+		if (!ret) {
1283
+			ret = copy_to_user(up, ch_info, sizeof(*ch_info));
1284
+			if (ret)
1285
+				ret = -EFAULT;
1286
+		}
1287
+		kfree(ch_info);
1288
+		break;
10851289 	default:
10861290 		ret = -ENOIOCTLCMD;
10871291 		break;
....@@ -1100,11 +1304,17 @@
11001304 	fps = DIV_ROUND_CLOSEST(gc2093->cur_mode->max_fps.denominator,
11011305 					gc2093->cur_mode->max_fps.numerator);
11021306 
1103
-	dev_info(gc2093->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
1104
-				gc2093->cur_mode->width,
1105
-				gc2093->cur_mode->height,
1106
-				fps);
1307
+	dev_info(gc2093->dev,
1308
+		 "%dx%d@%d, mode %d, vts 0x%x\n",
1309
+		 gc2093->cur_mode->width,
1310
+		 gc2093->cur_mode->height,
1311
+		 gc2093->cur_fps.denominator / gc2093->cur_fps.numerator,
1312
+		 gc2093->cur_mode->hdr_mode,
1313
+		 gc2093->cur_vts);
11071314 
1315
+	dev_info(gc2093->dev,
1316
+		 "stream:%d\n, on:%d",
1317
+		 gc2093->streaming, on);
11081318 	mutex_lock(&gc2093->lock);
11091319 	on = !!on;
11101320 	if (on == gc2093->streaming)
....@@ -1151,7 +1361,10 @@
11511361 	struct gc2093 *gc2093 = to_gc2093(sd);
11521362 	const struct gc2093_mode *mode = gc2093->cur_mode;
11531363 
1154
-	fi->interval = mode->max_fps;
1364
+	if (gc2093->streaming)
1365
+		fi->interval = gc2093->cur_fps;
1366
+	else
1367
+		fi->interval = mode->max_fps;
11551368 
11561369 	return 0;
11571370 }
....@@ -1184,9 +1397,7 @@
11841397 				   struct v4l2_subdev_pad_config *cfg,
11851398 				   struct v4l2_subdev_frame_size_enum *fse)
11861399 {
1187
-	struct gc2093 *gc2093 = to_gc2093(sd);
1188
-
1189
-	if (fse->index >= gc2093->cfg_num)
1400
+	if (fse->index >= ARRAY_SIZE(supported_modes))
11901401 		return -EINVAL;
11911402 
11921403 	if (fse->code != GC2093_MEDIA_BUS_FMT)
....@@ -1203,9 +1414,7 @@
12031414 						  struct v4l2_subdev_pad_config *cfg,
12041415 						  struct v4l2_subdev_frame_interval_enum *fie)
12051416 {
1206
-	struct gc2093 *gc2093 = to_gc2093(sd);
1207
-
1208
-	if (fie->index >= gc2093->cfg_num)
1417
+	if (fie->index >= ARRAY_SIZE(supported_modes))
12091418 		return -EINVAL;
12101419 
12111420 	fie->code = GC2093_MEDIA_BUS_FMT;
....@@ -1401,6 +1610,136 @@
14011610 			   gc2093_runtime_resume, NULL)
14021611 };
14031612 
1613
+
1614
+#ifdef CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP
1615
+static u32 rk_cam_hdr;
1616
+static u32 rk_cam_w;
1617
+static u32 rk_cam_h;
1618
+static u32 rk_cam_fps;
1619
+
1620
+static int __init __maybe_unused rk_cam_hdr_setup(char *str)
1621
+{
1622
+	int ret = 0;
1623
+	unsigned long val = 0;
1624
+
1625
+	ret = kstrtoul(str, 0, &val);
1626
+	if (!ret)
1627
+		rk_cam_hdr = (u32)val;
1628
+	else
1629
+		pr_err("get rk_cam_hdr fail\n");
1630
+	return 1;
1631
+}
1632
+
1633
+static int __init __maybe_unused rk_cam_w_setup(char *str)
1634
+{
1635
+	int ret = 0;
1636
+	unsigned long val = 0;
1637
+
1638
+	ret = kstrtoul(str, 0, &val);
1639
+	if (!ret)
1640
+		rk_cam_w = (u32)val;
1641
+	else
1642
+		pr_err("get rk_cam_w fail\n");
1643
+	return 1;
1644
+}
1645
+
1646
+static int __init __maybe_unused rk_cam_h_setup(char *str)
1647
+{
1648
+	int ret = 0;
1649
+	unsigned long val = 0;
1650
+
1651
+	ret = kstrtoul(str, 0, &val);
1652
+	if (!ret)
1653
+		rk_cam_h = (u32)val;
1654
+	else
1655
+		pr_err("get rk_cam_h fail\n");
1656
+	return 1;
1657
+}
1658
+
1659
+static int __init __maybe_unused rk_cam_fps_setup(char *str)
1660
+{
1661
+	int ret = 0;
1662
+	unsigned long val = 0;
1663
+
1664
+	ret = kstrtoul(str, 0, &val);
1665
+	if (!ret)
1666
+		rk_cam_fps = (u32)val;
1667
+	else
1668
+		pr_err("get rk_cam_fps fail\n");
1669
+	return 1;
1670
+}
1671
+
1672
+__setup("rk_cam_hdr=", rk_cam_hdr_setup);
1673
+__setup("rk_cam_w=", rk_cam_w_setup);
1674
+__setup("rk_cam_h=", rk_cam_h_setup);
1675
+__setup("rk_cam_fps=", rk_cam_fps_setup);
1676
+
1677
+static void find_terminal_resolution(struct gc2093 *gc2093)
1678
+{
1679
+	int i = 0;
1680
+	const struct gc2093_mode *mode = NULL;
1681
+	const struct gc2093_mode *fit_mode = NULL;
1682
+	u32 cur_fps = 0;
1683
+	u32 dst_fps = 0;
1684
+	u32 tmp_fps = 0;
1685
+
1686
+	if (rk_cam_w == 0 || rk_cam_h == 0 ||
1687
+	    rk_cam_fps == 0)
1688
+		goto err_find_res;
1689
+
1690
+	dev_info(gc2093->dev, "find resolution width: %d, height: %d, hdr: %d, fps: %d\n",
1691
+		 rk_cam_w, rk_cam_h, rk_cam_hdr, rk_cam_fps);
1692
+	dst_fps = rk_cam_fps;
1693
+	for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1694
+		mode = &supported_modes[i];
1695
+		cur_fps = mode->max_fps.denominator / mode->max_fps.numerator;
1696
+		if (mode->width == rk_cam_w && mode->height == rk_cam_h &&
1697
+		    mode->hdr_mode == rk_cam_hdr) {
1698
+			if (cur_fps == dst_fps) {
1699
+				gc2093->cur_mode = mode;
1700
+				return;
1701
+			}
1702
+			if (cur_fps >= dst_fps) {
1703
+				if (fit_mode) {
1704
+					tmp_fps = fit_mode->max_fps.denominator /
1705
+							  fit_mode->max_fps.numerator;
1706
+					if (tmp_fps - dst_fps > cur_fps - dst_fps)
1707
+						fit_mode = mode;
1708
+				} else {
1709
+					fit_mode = mode;
1710
+				}
1711
+			}
1712
+		}
1713
+	}
1714
+	if (fit_mode) {
1715
+		gc2093->cur_mode = fit_mode;
1716
+		return;
1717
+	}
1718
+err_find_res:
1719
+	dev_err(gc2093->dev, "not match %dx%d@%dfps mode %d\n!",
1720
+		rk_cam_w, rk_cam_h, dst_fps, rk_cam_hdr);
1721
+	gc2093->cur_mode = &supported_modes[0];
1722
+}
1723
+#else
1724
+static void find_terminal_resolution(struct gc2093 *gc2093)
1725
+{
1726
+	u32 hdr_mode = 0;
1727
+	struct device_node *node = gc2093->dev->of_node;
1728
+	int i = 0;
1729
+
1730
+	of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
1731
+	for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1732
+		if (hdr_mode == supported_modes[i].hdr_mode) {
1733
+			gc2093->cur_mode = &supported_modes[i];
1734
+			break;
1735
+		}
1736
+	}
1737
+	if (i == ARRAY_SIZE(supported_modes))
1738
+		gc2093->cur_mode = &supported_modes[0];
1739
+
1740
+}
1741
+#endif
1742
+
14041743 static int gc2093_probe(struct i2c_client *client,
14051744 			 const struct i2c_device_id *id)
14061745 {
....@@ -1448,6 +1787,8 @@
14481787 		return -EINVAL;
14491788 	}
14501789 
1790
+	find_terminal_resolution(gc2093);
1791
+
14511792 	gc2093->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
14521793 	if (IS_ERR(gc2093->reset_gpio))
14531794 		dev_warn(dev, "Failed to get reset-gpios\n");
....@@ -1463,11 +1804,6 @@
14631804 	}
14641805 
14651806 	mutex_init(&gc2093->lock);
1466
-
1467
-	/* set default mode */
1468
-	gc2093->cur_mode = &supported_modes[0];
1469
-	gc2093->cfg_num = ARRAY_SIZE(supported_modes);
1470
-	gc2093->cur_vts = gc2093->cur_mode->vts_def;
14711807 
14721808 	sd = &gc2093->subdev;
14731809 	v4l2_i2c_subdev_init(sd, client, &gc2093_subdev_ops);