hc
2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f
kernel/drivers/i2c/busses/i2c-ismt.c
....@@ -75,11 +75,14 @@
7575 /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */
7676 #define PCI_DEVICE_ID_INTEL_S1200_SMT0 0x0c59
7777 #define PCI_DEVICE_ID_INTEL_S1200_SMT1 0x0c5a
78
+#define PCI_DEVICE_ID_INTEL_CDF_SMT 0x18ac
7879 #define PCI_DEVICE_ID_INTEL_DNV_SMT 0x19ac
80
+#define PCI_DEVICE_ID_INTEL_EBG_SMT 0x1bff
7981 #define PCI_DEVICE_ID_INTEL_AVOTON_SMT 0x1f15
8082
8183 #define ISMT_DESC_ENTRIES 2 /* number of descriptor entries */
8284 #define ISMT_MAX_RETRIES 3 /* number of SMBus retries to attempt */
85
+#define ISMT_LOG_ENTRIES 3 /* number of interrupt cause log entries */
8386
8487 /* Hardware Descriptor Constants - Control Field */
8588 #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */
....@@ -173,15 +176,16 @@
173176 u8 head; /* ring buffer head pointer */
174177 struct completion cmp; /* interrupt completion */
175178 u8 buffer[I2C_SMBUS_BLOCK_MAX + 16]; /* temp R/W data buffer */
179
+ dma_addr_t log_dma;
180
+ u32 *log;
176181 };
177182
178
-/**
179
- * ismt_ids - PCI device IDs supported by this driver
180
- */
181183 static const struct pci_device_id ismt_ids[] = {
182184 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) },
183185 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) },
186
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMT) },
184187 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMT) },
188
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMT) },
185189 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) },
186190 { 0, }
187191 };
....@@ -195,6 +199,8 @@
195199
196200 /**
197201 * __ismt_desc_dump() - dump the contents of a specific descriptor
202
+ * @dev: the iSMT device
203
+ * @desc: the iSMT hardware descriptor
198204 */
199205 static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc)
200206 {
....@@ -405,6 +411,9 @@
405411 /* Initialize the descriptor */
406412 memset(desc, 0, sizeof(struct ismt_desc));
407413 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write);
414
+
415
+ /* Always clear the log entries */
416
+ memset(priv->log, 0, ISMT_LOG_ENTRIES * sizeof(u32));
408417
409418 /* Initialize common control bits */
410419 if (likely(pci_dev_msi_enabled(priv->pci_dev)))
....@@ -626,11 +635,6 @@
626635 I2C_FUNC_SMBUS_PEC;
627636 }
628637
629
-/**
630
- * smbus_algorithm - the adapter algorithm and supported functionality
631
- * @smbus_xfer: the adapter algorithm
632
- * @functionality: functionality supported by the adapter
633
- */
634638 static const struct i2c_algorithm smbus_algorithm = {
635639 .smbus_xfer = ismt_access,
636640 .functionality = ismt_func,
....@@ -694,6 +698,8 @@
694698
695699 /* initialize the Master Descriptor Base Address (MDBA) */
696700 writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA);
701
+
702
+ writeq(priv->log_dma, priv->smba + ISMT_GR_SMTICL);
697703
698704 /* initialize the Master Control Register (MCTRL) */
699705 writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL);
....@@ -779,11 +785,15 @@
779785 if (!priv->hw)
780786 return -ENOMEM;
781787
782
- memset(priv->hw, 0, (ISMT_DESC_ENTRIES * sizeof(struct ismt_desc)));
783
-
784788 priv->head = 0;
785789 init_completion(&priv->cmp);
786790
791
+ priv->log = dmam_alloc_coherent(&priv->pci_dev->dev,
792
+ ISMT_LOG_ENTRIES * sizeof(u32),
793
+ &priv->log_dma, GFP_KERNEL);
794
+ if (!priv->log)
795
+ return -ENOMEM;
796
+
787797 return 0;
788798 }
789799