kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
..
..
@@ -1256,7 +1256,7 @@
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 			VOP_FEATURE_HDR10 | VOP_FEATURE_OVERSCAN,
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 	 .gamma_lut_len = 1024,
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 	 .cubic_lut_len = 729, /* 9x9x9 */
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-	 .max_output = { 4096, 2304 },
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+	 .max_output = { 4096, 4096 },
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 	 .pre_scan_max_dly = { 69, 53, 53, 42 },
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 	 .intr = &rk3568_vp0_intr,
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 	 .hdr_table = &rk3568_vop_hdr_table,
..
..
@@ -1267,7 +1267,7 @@
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 	 .soc_id = { 0x3568, 0x3566 },
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 	 .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
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 	 .gamma_lut_len = 1024,
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-	 .max_output = { 2048, 1536 },
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+	 .max_output = { 2048, 2048 },
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 	 .pre_scan_max_dly = { 40, 40, 40, 40 },
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 	 .intr = &rk3568_vp1_intr,
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 	 .regs = &rk3568_vop_vp1_regs,
..
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@@ -1277,7 +1277,7 @@
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 	 .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
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 	 .soc_id = { 0x3568, 0x3566 },
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 	 .gamma_lut_len = 1024,
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-	 .max_output = { 1920, 1080 },
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+	 .max_output = { 1920, 1920 },
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 	 .pre_scan_max_dly = { 40, 40, 40, 40 },
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 	 .intr = &rk3568_vp2_intr,
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 	 .regs = &rk3568_vop_vp2_regs,
..
..
@@ -1883,6 +1883,7 @@
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 	.afbc_enable = VOP_REG(RK3568_CLUSTER0_CTRL, 0x1, 1),
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 	.enable = VOP_REG(RK3568_CLUSTER0_CTRL, 1, 0),
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 	.lb_mode = VOP_REG(RK3568_CLUSTER0_CTRL, 0xf, 4),
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+	.frm_reset_en = VOP_REG(RK3568_CLUSTER0_CTRL, 1, 31),
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 	.src_color_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
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 	.dst_color_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
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 	.src_alpha_ctrl = VOP_REG(RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
..
..
@@ -1893,6 +1894,7 @@
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 	.afbc_enable = VOP_REG(RK3568_CLUSTER1_CTRL, 0x1, 1),
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 	.enable = VOP_REG(RK3568_CLUSTER1_CTRL, 1, 0),
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 	.lb_mode = VOP_REG(RK3568_CLUSTER1_CTRL, 0xf, 4),
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+	.frm_reset_en = VOP_REG(RK3568_CLUSTER1_CTRL, 1, 31),
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 	.src_color_ctrl = VOP_REG(RK3568_CLUSTER1_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
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 	.dst_color_ctrl = VOP_REG(RK3568_CLUSTER1_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
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 	.src_alpha_ctrl = VOP_REG(RK3568_CLUSTER1_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
..
..
@@ -1903,6 +1905,7 @@
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 	.afbc_enable = VOP_REG(RK3588_CLUSTER2_CTRL, 0x1, 1),
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 	.enable = VOP_REG(RK3588_CLUSTER2_CTRL, 1, 0),
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 	.lb_mode = VOP_REG(RK3588_CLUSTER2_CTRL, 0xf, 4),
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+	.frm_reset_en = VOP_REG(RK3588_CLUSTER2_CTRL, 1, 31),
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 	.src_color_ctrl = VOP_REG(RK3588_CLUSTER2_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
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 	.dst_color_ctrl = VOP_REG(RK3588_CLUSTER2_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
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 	.src_alpha_ctrl = VOP_REG(RK3588_CLUSTER2_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
..
..
@@ -1913,6 +1916,7 @@
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 	.afbc_enable = VOP_REG(RK3588_CLUSTER3_CTRL, 0x1, 1),
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 	.enable = VOP_REG(RK3588_CLUSTER3_CTRL, 1, 0),
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 	.lb_mode = VOP_REG(RK3588_CLUSTER3_CTRL, 0xf, 4),
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+	.frm_reset_en = VOP_REG(RK3588_CLUSTER3_CTRL, 1, 31),
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 	.src_color_ctrl = VOP_REG(RK3588_CLUSTER3_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
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 	.dst_color_ctrl = VOP_REG(RK3588_CLUSTER3_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
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 	.src_alpha_ctrl = VOP_REG(RK3588_CLUSTER3_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),