kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
..
..
@@ -666,11 +666,13 @@
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666
 static bool is_rb_swap(uint32_t bus_format, uint32_t output_mode)
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667
 {
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 	/*
669
-	 * The default component order of serial rgb3x8 formats
669
+	 * The default component order of serial formats
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 	 * is BGR. So it is needed to enable RB swap.
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 	 */
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 	if (bus_format == MEDIA_BUS_FMT_RGB888_3X8 ||
673
-	    bus_format == MEDIA_BUS_FMT_RGB888_DUMMY_4X8)
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+	    bus_format == MEDIA_BUS_FMT_RGB888_DUMMY_4X8 ||
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+	    bus_format == MEDIA_BUS_FMT_RGB666_3X6 ||
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+	    bus_format == MEDIA_BUS_FMT_RGB565_2X8_LE)
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 		return true;
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 	else
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 		return false;
..
..
@@ -1871,6 +1873,9 @@
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 					to_vop_plane_state(plane->state);
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 #endif
1873
1875
 
1876
+	rockchip_drm_dbg(vop->dev, VOP_DEBUG_PLANE, "disable win%d-area%d by %s\n",
1877
+			 win->win_id, win->area_id, current->comm);
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+
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 	if (!old_state->crtc)
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 		return;
1876
1881
 
..
..
@@ -1980,6 +1985,7 @@
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 	uint32_t val;
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 	bool rb_swap, global_alpha_en;
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 	int is_yuv = fb->format->is_yuv;
1988
+	struct drm_format_name_buf format_name;
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1989
 
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 #if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
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 	bool AFBC_flag = false;
..
..
@@ -2144,6 +2150,13 @@
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 	VOP_WIN_SET(vop, win, enable, 1);
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 	VOP_WIN_SET(vop, win, gate, 1);
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 	spin_unlock(&vop->reg_lock);
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+
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+	drm_get_format_name(fb->format->format, &format_name);
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+	rockchip_drm_dbg(vop->dev, VOP_DEBUG_PLANE,
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+			 "update win%d-area%d [%dx%d->%dx%d@(%d, %d)] zpos:%d fmt[%s%s] addr[%pad] by %s\n",
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+			 win->win_id, win->area_id, actual_w, actual_h,
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+			 dsp_w, dsp_h, dsp_stx, dsp_sty, vop_plane_state->zpos, format_name.str,
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+			 fb->modifier ? "[AFBC]" : "", &vop_plane_state->yrgb_mst, current->comm);
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 	/*
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 	 * spi interface(vop_plane_state->yrgb_kvaddr, fb->pixel_format,
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2162
 	 * actual_w, actual_h)
..
..
@@ -2325,7 +2338,7 @@
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 		return;
2326
2339
 
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 	__drm_atomic_helper_plane_reset(plane, &vop_plane_state->base);
2328
-	win->state.zpos = win->zpos;
2341
+	vop_plane_state->base.zpos = win->zpos;
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 	vop_plane_state->global_alpha = 0xff;
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2343
 }
2331
2344
 
..
..
@@ -2514,7 +2527,7 @@
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 	spin_unlock_irqrestore(&drm->event_lock, flags);
2515
2528
 }
2516
2529
 
2517
-static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on)
2530
+static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on, void *data)
2518
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 {
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 	struct rockchip_drm_private *private = crtc->dev->dev_private;
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 	struct vop *vop = to_vop(crtc);
..
..
@@ -3078,8 +3091,8 @@
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 {
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 	struct vop *vop = to_vop(crtc);
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 	const struct vop_data *vop_data = vop->data;
3081
-	struct rockchip_crtc_state *s =
3082
-			to_rockchip_crtc_state(crtc->state);
3094
+	struct drm_crtc_state *new_crtc_state = container_of(mode, struct drm_crtc_state, mode);
3095
+	struct rockchip_crtc_state *s = to_rockchip_crtc_state(new_crtc_state);
3083
3096
 
3084
3097
 	if (mode->hdisplay > vop_data->max_output.width)
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3098
 		return false;
..
..
@@ -3094,6 +3107,10 @@
3094
3107
 	    (VOP_MAJOR(vop->version) == 2 && VOP_MINOR(vop->version) >= 12 &&
3095
3108
 	     s->output_if & VOP_OUTPUT_IF_BT656))
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 		adj_mode->crtc_clock *= 2;
3110
+
3111
+	if (vop->mcu_timing.mcu_pix_total)
3112
+		adj_mode->crtc_clock *= rockchip_drm_get_cycles_per_pixel(s->bus_format) *
3113
+					(vop->mcu_timing.mcu_pix_total + 1);
3097
3114
 
3098
3115
 	adj_mode->crtc_clock =
3099
3116
 		DIV_ROUND_UP(clk_round_rate(vop->dclk, adj_mode->crtc_clock * 1000),
..
..
@@ -3118,12 +3135,14 @@
3118
3135
 
3119
3136
 	switch (s->bus_format) {
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3137
 	case MEDIA_BUS_FMT_RGB565_1X16:
3138
+	case MEDIA_BUS_FMT_RGB565_2X8_LE:
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 		VOP_CTRL_SET(vop, dither_down_en, 1);
3122
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 		VOP_CTRL_SET(vop, dither_down_mode, RGB888_TO_RGB565);
3123
3141
 		break;
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 	case MEDIA_BUS_FMT_RGB666_1X18:
3125
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 	case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
3126
3144
 	case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
3145
+	case MEDIA_BUS_FMT_RGB666_3X6:
3127
3146
 		VOP_CTRL_SET(vop, dither_down_en, 1);
3128
3147
 		VOP_CTRL_SET(vop, dither_down_mode, RGB888_TO_RGB666);
3129
3148
 		break;
..
..
@@ -4023,6 +4042,7 @@
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 	spin_lock_irqsave(&vop->irq_lock, flags);
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 	vop->pre_overlay = s->hdr.pre_overlay;
4025
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 	vop_cfg_done(vop);
4045
+	rockchip_drm_dbg(vop->dev, VOP_DEBUG_CFG_DONE, "cfg_done\n\n");
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 	/*
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 	 * rk322x and rk332x odd-even field will mistake when in interlace mode.
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4048
 	 * we must switch to frame effect before switch screen and switch to
..
..
@@ -4388,6 +4408,7 @@
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 		 * frame effective, but actually it's effective immediately, so
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 		 * we config this register at frame start.
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 		 */
4411
+		rockchip_drm_dbg(vop->dev, VOP_DEBUG_VSYNC, "vsync\n");
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4412
 		spin_lock_irqsave(&vop->irq_lock, flags);
4392
4413
 		VOP_CTRL_SET(vop, level2_overlay_en, vop->pre_overlay);
4393
4414
 		VOP_CTRL_SET(vop, alpha_hard_calc, vop->pre_overlay);