kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
..
..
@@ -125,6 +125,7 @@
125
125
 	hbp = mode->htotal - mode->hsync_end;
126
126
 
127
127
 	mode->clock *= 2;
128
+	mode->crtc_clock *= 2;
128
129
 	mode->hdisplay = hactive * 2;
129
130
 	mode->hsync_start = mode->hdisplay + hfp * 2;
130
131
 	mode->hsync_end = mode->hsync_start + hsync * 2;
..
..
@@ -143,6 +144,7 @@
143
144
 	hbp = mode->htotal - mode->hsync_end;
144
145
 
145
146
 	mode->clock /= 2;
147
+	mode->crtc_clock /= 2;
146
148
 	mode->hdisplay = hactive / 2;
147
149
 	mode->hsync_start = mode->hdisplay + hfp / 2;
148
150
 	mode->hsync_end = mode->hsync_start + hsync / 2;
..
..
@@ -197,6 +199,30 @@
197
199
 	return 0;
198
200
 }
199
201
 EXPORT_SYMBOL(rockchip_drm_get_bpp);
202
+
203
+uint32_t rockchip_drm_get_cycles_per_pixel(uint32_t bus_format)
204
+{
205
+	switch (bus_format) {
206
+	case MEDIA_BUS_FMT_RGB565_1X16:
207
+	case MEDIA_BUS_FMT_RGB666_1X18:
208
+	case MEDIA_BUS_FMT_RGB888_1X24:
209
+	case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
210
+		return 1;
211
+	case MEDIA_BUS_FMT_RGB565_2X8_LE:
212
+	case MEDIA_BUS_FMT_BGR565_2X8_LE:
213
+		return 2;
214
+	case MEDIA_BUS_FMT_RGB666_3X6:
215
+	case MEDIA_BUS_FMT_RGB888_3X8:
216
+	case MEDIA_BUS_FMT_BGR888_3X8:
217
+		return 3;
218
+	case MEDIA_BUS_FMT_RGB888_DUMMY_4X8:
219
+	case MEDIA_BUS_FMT_BGR888_DUMMY_4X8:
220
+		return 4;
221
+	default:
222
+		return 1;
223
+	}
224
+}
225
+EXPORT_SYMBOL(rockchip_drm_get_cycles_per_pixel);
200
226
 
201
227
 /**
202
228
  * rockchip_drm_of_find_possible_crtcs - find the possible CRTCs for an active
..
..
@@ -1289,6 +1315,12 @@
1289
1315
 }
1290
1316
 #endif
1291
1317
 
1318
+static const struct drm_prop_enum_list split_area[] = {
1319
+	{ ROCKCHIP_DRM_SPLIT_UNSET, "UNSET" },
1320
+	{ ROCKCHIP_DRM_SPLIT_LEFT_SIDE, "LEFT" },
1321
+	{ ROCKCHIP_DRM_SPLIT_RIGHT_SIDE, "RIGHT" },
1322
+};
1323
+
1292
1324
 static int rockchip_drm_create_properties(struct drm_device *dev)
1293
1325
 {
1294
1326
 	struct drm_property *prop;
..
..
@@ -1324,6 +1356,11 @@
1324
1356
 		return -ENOMEM;
1325
1357
 	private->connector_id_prop = prop;
1326
1358
 
1359
+	prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM, "SPLIT_AREA",
1360
+					split_area,
1361
+					ARRAY_SIZE(split_area));
1362
+	private->split_area_prop = prop;
1363
+
1327
1364
 	prop = drm_property_create_object(dev,
1328
1365
 					  DRM_MODE_PROP_ATOMIC | DRM_MODE_PROP_IMMUTABLE,
1329
1366
 					  "SOC_ID", DRM_MODE_OBJECT_CRTC);
..
..
@@ -1337,6 +1374,9 @@
1337
1374
 	private->aclk_prop = drm_property_create_range(dev, 0, "ACLK", 0, UINT_MAX);
1338
1375
 	private->bg_prop = drm_property_create_range(dev, 0, "BACKGROUND", 0, UINT_MAX);
1339
1376
 	private->line_flag_prop = drm_property_create_range(dev, 0, "LINE_FLAG1", 0, UINT_MAX);
1377
+	private->cubic_lut_prop = drm_property_create(dev, DRM_MODE_PROP_BLOB, "CUBIC_LUT", 0);
1378
+	private->cubic_lut_size_prop = drm_property_create_range(dev, DRM_MODE_PROP_IMMUTABLE,
1379
+								 "CUBIC_LUT_SIZE", 0, UINT_MAX);
1340
1380
 
1341
1381
 	return drm_mode_create_tv_properties(dev, 0, NULL);
1342
1382
 }