kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/drivers/gpu/drm/rockchip/cdn-dp-reg.h
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@@ -8,6 +8,7 @@
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 #define _CDN_DP_REG_H
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 #include <linux/bitops.h>
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+#include <linux/phy/phy.h>
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 #define ADDR_IMEM		0x10000
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 #define ADDR_DMEM		0x20000
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@@ -129,7 +130,7 @@
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 #define HPD_EVENT_MASK			0x211c
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 #define HPD_EVENT_DET			0x2120
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-/* dpyx framer addr */
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+/* dptx framer addr */
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 #define DP_FRAMER_GLOBAL_CONFIG		0x2200
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 #define DP_SW_RESET			0x2204
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 #define DP_FRAMER_TU			0x2208
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@@ -320,6 +321,13 @@
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 #define GENERAL_BUS_SETTINGS            0x03
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 #define GENERAL_TEST_ACCESS             0x04
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+/* AUX status*/
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+#define AUX_STATUS_ACK			0
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+#define AUX_STATUS_NACK			1
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+#define AUX_STATUS_DEFER			2
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+#define AUX_STATUS_SINK_ERROR		3
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+#define AUX_STATUS_BUS_ERROR		4
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+
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 #define DPTX_SET_POWER_MNG			0x00
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 #define DPTX_SET_HOST_CAPABILITIES		0x01
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 #define DPTX_GET_EDID				0x02
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@@ -416,6 +424,40 @@
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 /* Reference cycles when using lane clock as reference */
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 #define LANE_REF_CYC				0x8000
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+/* register CM_VID_CTRL */
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+#define LANE_VID_REF_CYC(x)                    (((x) & (BIT(24) - 1)) << 0)
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+#define NMVID_MEAS_TOLERANCE(x)                        (((x) & 0xf) << 24)
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+
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+/* register DP_TX_PHY_CONFIG_REG */
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+#define DP_TX_PHY_TRAINING_ENABLE(x)           ((x) & 1)
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+#define DP_TX_PHY_TRAINING_TYPE_PRBS7          (0 << 1)
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+#define DP_TX_PHY_TRAINING_TYPE_TPS1           (1 << 1)
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+#define DP_TX_PHY_TRAINING_TYPE_TPS2           (2 << 1)
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+#define DP_TX_PHY_TRAINING_TYPE_TPS3           (3 << 1)
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+#define DP_TX_PHY_TRAINING_TYPE_TPS4           (4 << 1)
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+#define DP_TX_PHY_TRAINING_TYPE_PLTPAT         (5 << 1)
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+#define DP_TX_PHY_TRAINING_TYPE_D10_2          (6 << 1)
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+#define DP_TX_PHY_TRAINING_TYPE_HBR2CPAT       (8 << 1)
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+#define DP_TX_PHY_TRAINING_PATTERN(x)          ((x) << 1)
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+#define DP_TX_PHY_SCRAMBLER_BYPASS(x)          (((x) & 1) << 5)
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+#define DP_TX_PHY_ENCODER_BYPASS(x)            (((x) & 1) << 6)
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+#define DP_TX_PHY_SKEW_BYPASS(x)               (((x) & 1) << 7)
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+#define DP_TX_PHY_DISPARITY_RST(x)             (((x) & 1) << 8)
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+#define DP_TX_PHY_LANE0_SKEW(x)                (((x) & 7) << 9)
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+#define DP_TX_PHY_LANE1_SKEW(x)                (((x) & 7) << 12)
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+#define DP_TX_PHY_LANE2_SKEW(x)                (((x) & 7) << 15)
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+#define DP_TX_PHY_LANE3_SKEW(x)                (((x) & 7) << 18)
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+#define DP_TX_PHY_10BIT_ENABLE(x)              (((x) & 1) << 21)
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+
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+/* register DP_FRAMER_GLOBAL_CONFIG */
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+#define NUM_LANES(x)           ((x) & 3)
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+#define SST_MODE               (0 << 2)
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+#define RG_EN                  (0 << 4)
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+#define GLOBAL_EN              BIT(3)
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+#define NO_VIDEO               BIT(5)
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+#define ENC_RST_DIS            BIT(6)
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+#define WR_VHSYNC_FALL         BIT(7)
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+
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 enum voltage_swing_level {
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 	VOLTAGE_LEVEL_0,
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 	VOLTAGE_LEVEL_1,
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@@ -461,8 +503,12 @@
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 int cdn_dp_event_config(struct cdn_dp_device *dp);
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 u32 cdn_dp_get_event(struct cdn_dp_device *dp);
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 int cdn_dp_get_hpd_status(struct cdn_dp_device *dp);
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-int cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr, u8 value);
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-int cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr, u8 *data, u16 len);
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+int cdn_dp_reg_write(struct cdn_dp_device *dp, u16 addr, u32 val);
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+ssize_t cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr,
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+			  u8 *data, u16 len);
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+ssize_t cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr,
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+			 u8 *data, u16 len);
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+int cdn_dp_get_aux_status(struct cdn_dp_device *dp);
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 int cdn_dp_get_edid_block(void *dp, u8 *edid,
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 			  unsigned int block, size_t length);
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 int cdn_dp_train_link(struct cdn_dp_device *dp);
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@@ -471,4 +517,5 @@
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 int cdn_dp_audio_stop(struct cdn_dp_device *dp, struct audio_info *audio);
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 int cdn_dp_audio_mute(struct cdn_dp_device *dp, bool enable);
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 int cdn_dp_audio_config(struct cdn_dp_device *dp, struct audio_info *audio);
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+int cdn_dp_software_train_link(struct cdn_dp_device *dp);
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 #endif /* _CDN_DP_REG_H */