kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/drivers/gpu/drm/rockchip/cdn-dp-link-training.c
..
..
@@ -14,14 +14,24 @@
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 static void cdn_dp_set_signal_levels(struct cdn_dp_device *dp)
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 {
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 	struct cdn_dp_port *port = dp->port[dp->active_port];
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-	int rate = drm_dp_bw_code_to_link_rate(dp->link.rate);
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+	union phy_configure_opts phy_cfg = {0};
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 	u8 swing = (dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) >>
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 		   DP_TRAIN_VOLTAGE_SWING_SHIFT;
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 	u8 pre_emphasis = (dp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
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 			  >> DP_TRAIN_PRE_EMPHASIS_SHIFT;
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+	unsigned int lane;
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-	tcphy_dp_set_phy_config(port->phy, rate, dp->link.num_lanes,
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-				swing, pre_emphasis);
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+	for (lane = 0; lane < dp->max_lanes; lane++) {
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+		phy_cfg.dp.voltage[lane] = swing;
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+		phy_cfg.dp.pre[lane] = pre_emphasis;
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+	}
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+
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+	phy_cfg.dp.lanes = dp->max_lanes;
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+	phy_cfg.dp.link_rate = drm_dp_bw_code_to_link_rate(dp->max_rate) / 100;
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+	phy_cfg.dp.set_lanes = false;
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+	phy_cfg.dp.set_rate = false;
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+	phy_cfg.dp.set_voltages = true;
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+	phy_configure(port->phy, &phy_cfg);
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 }
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36
 
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 static int cdn_dp_set_pattern(struct cdn_dp_device *dp, uint8_t dp_train_pat)
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@@ -30,7 +40,7 @@
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 	int ret;
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 	uint8_t pattern = dp_train_pat & DP_TRAINING_PATTERN_MASK;
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-	global_config = NUM_LANES(dp->link.num_lanes - 1) | SST_MODE |
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+	global_config = NUM_LANES(dp->max_lanes - 1) | SST_MODE |
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 			GLOBAL_EN | RG_EN | ENC_RST_DIS | WR_VHSYNC_FALL;
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45
 
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 	phy_config = DP_TX_PHY_ENCODER_BYPASS(0) |
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@@ -63,7 +73,7 @@
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 		return ret;
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 	}
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-	ret = cdn_dp_reg_write(dp, DPTX_LANE_EN, BIT(dp->link.num_lanes) - 1);
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+	ret = cdn_dp_reg_write(dp, DPTX_LANE_EN, BIT(dp->max_lanes) - 1);
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 	if (ret) {
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 		DRM_ERROR("fail to set DPTX_LANE_EN, error: %d\n", ret);
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 		return ret;
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@@ -106,7 +116,7 @@
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 	uint8_t v = 0, p = 0;
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 	uint8_t preemph_max;
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118
 
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-	for (i = 0; i < dp->link.num_lanes; i++) {
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+	for (i = 0; i < dp->max_lanes; i++) {
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 		v = max(v, drm_dp_get_adjust_request_voltage(link_status, i));
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 		p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status,
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 								  i));
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@@ -119,7 +129,7 @@
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 	if (p >= preemph_max)
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 		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
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-	for (i = 0; i < dp->link.num_lanes; i++)
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+	for (i = 0; i < dp->max_lanes; i++)
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 		dp->train_set[i] = v | p;
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 }
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@@ -149,7 +159,7 @@
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 {
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 	int lane;
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161
 
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-	for (lane = 0; lane < dp->link.num_lanes; lane++)
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+	for (lane = 0; lane < dp->max_lanes; lane++)
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 		if ((dp->train_set[lane] & DP_TRAIN_MAX_SWING_REACHED) == 0)
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 			return false;
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@@ -163,8 +173,8 @@
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 	cdn_dp_set_signal_levels(dp);
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174
 
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 	ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
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-				dp->train_set, dp->link.num_lanes);
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-	if (ret != dp->link.num_lanes)
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+				dp->train_set, dp->max_lanes);
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+	if (ret != dp->max_lanes)
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 		return -EINVAL;
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 	return 0;
..
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@@ -183,8 +193,8 @@
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 		len = 1;
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 	} else {
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 		/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
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-		memcpy(buf + 1, dp->train_set, dp->link.num_lanes);
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-		len = dp->link.num_lanes + 1;
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+		memcpy(buf + 1, dp->train_set, dp->max_lanes);
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+		len = dp->max_lanes + 1;
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 	}
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 	ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_PATTERN_SET,
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@@ -237,7 +247,7 @@
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 			return -EINVAL;
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 		}
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-		if (drm_dp_clock_recovery_ok(link_status, dp->link.num_lanes)) {
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+		if (drm_dp_clock_recovery_ok(link_status, dp->max_lanes)) {
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 			DRM_DEBUG_KMS("clock recovery OK\n");
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 			return 0;
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 		}
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@@ -301,12 +311,12 @@
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 		/* Make sure clock is still ok */
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 		if (!drm_dp_clock_recovery_ok(link_status,
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-					      dp->link.num_lanes)) {
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+					      dp->max_lanes)) {
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 			DRM_DEBUG_KMS("Clock recovery check failed\n");
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 			break;
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 		}
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-		if (drm_dp_channel_eq_ok(link_status,  dp->link.num_lanes)) {
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+		if (drm_dp_channel_eq_ok(link_status,  dp->max_lanes)) {
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 			DRM_DEBUG_KMS("Channel EQ done\n");
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 			return 0;
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 		}
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@@ -338,17 +348,17 @@
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348
 
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 static int cdn_dp_get_lower_link_rate(struct cdn_dp_device *dp)
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 {
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-	switch (dp->link.rate) {
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+	switch (dp->max_rate) {
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 	case DP_LINK_BW_1_62:
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 		return -EINVAL;
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 	case DP_LINK_BW_2_7:
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-		dp->link.rate = DP_LINK_BW_1_62;
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+		dp->max_rate = DP_LINK_BW_1_62;
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 		break;
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 	case DP_LINK_BW_5_4:
348
-		dp->link.rate = DP_LINK_BW_2_7;
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+		dp->max_rate = DP_LINK_BW_2_7;
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 		break;
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 	default:
351
-		dp->link.rate = DP_LINK_BW_5_4;
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+		dp->max_rate = DP_LINK_BW_5_4;
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 		break;
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 	}
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..
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@@ -372,12 +382,12 @@
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382
 
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 	source_max = dp->lanes;
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 	sink_max = drm_dp_max_lane_count(dp->dpcd);
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-	dp->link.num_lanes = min(source_max, sink_max);
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+	dp->max_lanes = min(source_max, sink_max);
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386
 
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 	source_max = drm_dp_bw_code_to_link_rate(CDN_DP_MAX_LINK_RATE);
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 	sink_max = drm_dp_max_link_rate(dp->dpcd);
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 	rate = min(source_max, sink_max);
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-	dp->link.rate = drm_dp_link_rate_to_bw_code(rate);
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+	dp->max_rate = drm_dp_link_rate_to_bw_code(rate);
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 	ssc_on = !!(dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5);
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 	link_config[0] = ssc_on ? DP_SPREAD_AMP_0_5 : 0;
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..
@@ -387,23 +397,21 @@
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 	drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
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398
 
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 	while (true) {
390
-		ret = tcphy_dp_set_link_rate(port->phy,
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-				drm_dp_bw_code_to_link_rate(dp->link.rate),
392
-				ssc_on);
393
-		if (ret) {
394
-			DRM_ERROR("failed to set link rate: %d\n", ret);
395
-			return ret;
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-		}
400
+		union phy_configure_opts phy_cfg = {0};
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401
 
398
-		ret = tcphy_dp_set_lane_count(port->phy, dp->link.num_lanes);
399
-		if (ret) {
400
-			DRM_ERROR("failed to set lane count: %d\n", ret);
402
+		phy_cfg.dp.lanes = dp->max_lanes;
403
+		phy_cfg.dp.link_rate = drm_dp_bw_code_to_link_rate(dp->max_rate) / 100;
404
+		phy_cfg.dp.ssc = ssc_on;
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+		phy_cfg.dp.set_lanes = true;
406
+		phy_cfg.dp.set_rate = true;
407
+		phy_cfg.dp.set_voltages = false;
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+		ret = phy_configure(port->phy, &phy_cfg);
409
+		if (ret)
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 			return ret;
402
-		}
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 		/* Write the link configuration data */
405
-		link_config[0] = dp->link.rate;
406
-		link_config[1] = dp->link.num_lanes;
413
+		link_config[0] = dp->max_rate;
414
+		link_config[1] = dp->max_lanes;
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 		if (drm_dp_enhanced_frame_cap(dp->dpcd))
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 			link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
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 		drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, link_config, 2);