kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c
..
..
@@ -131,8 +131,28 @@
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 	}
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 };
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+MODULE_FIRMWARE("nvidia/gp102/gr/fecs_bl.bin");
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+MODULE_FIRMWARE("nvidia/gp102/gr/fecs_inst.bin");
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+MODULE_FIRMWARE("nvidia/gp102/gr/fecs_data.bin");
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+MODULE_FIRMWARE("nvidia/gp102/gr/fecs_sig.bin");
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+MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_bl.bin");
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+MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_inst.bin");
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+MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_data.bin");
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+MODULE_FIRMWARE("nvidia/gp102/gr/gpccs_sig.bin");
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+MODULE_FIRMWARE("nvidia/gp102/gr/sw_ctx.bin");
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+MODULE_FIRMWARE("nvidia/gp102/gr/sw_nonctx.bin");
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+MODULE_FIRMWARE("nvidia/gp102/gr/sw_bundle_init.bin");
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+MODULE_FIRMWARE("nvidia/gp102/gr/sw_method_init.bin");
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+
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+static const struct gf100_gr_fwif
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+gp102_gr_fwif[] = {
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+	{  0, gm200_gr_load, &gp102_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr },
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+	{ -1, gm200_gr_nofw },
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+	{}
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+};
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+
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 int
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 gp102_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
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 {
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-	return gm200_gr_new_(&gp102_gr, device, index, pgr);
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+	return gf100_gr_new_(gp102_gr_fwif, device, index, pgr);
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 }