kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/drivers/gpu/drm/nouveau/nv17_fence.c
..
..
@@ -21,14 +21,16 @@
21
21
  *
22
22
  * Authors: Ben Skeggs <bskeggs@redhat.com>
23
23
  */
24
-
25
-#include <nvif/os.h>
26
-#include <nvif/class.h>
27
-#include <nvif/cl0002.h>
28
-
29
24
 #include "nouveau_drv.h"
30
25
 #include "nouveau_dma.h"
31
26
 #include "nv10_fence.h"
27
+
28
+#include <nvif/push006c.h>
29
+
30
+#include <nvif/class.h>
31
+#include <nvif/cl0002.h>
32
+
33
+#include <nvhw/class/cl176e.h>
32
34
 
33
35
 int
34
36
 nv17_fence_sync(struct nouveau_fence *fence,
..
..
@@ -37,6 +39,8 @@
37
39
 	struct nouveau_cli *cli = (void *)prev->user.client;
38
40
 	struct nv10_fence_priv *priv = chan->drm->fence;
39
41
 	struct nv10_fence_chan *fctx = chan->fence;
42
+	struct nvif_push *ppush = prev->chan.push;
43
+	struct nvif_push *npush = chan->chan.push;
40
44
 	u32 value;
41
45
 	int ret;
42
46
 
..
..
@@ -48,23 +52,21 @@
48
52
 	priv->sequence += 2;
49
53
 	spin_unlock(&priv->lock);
50
54
 
51
-	ret = RING_SPACE(prev, 5);
55
+	ret = PUSH_WAIT(ppush, 5);
52
56
 	if (!ret) {
53
-		BEGIN_NV04(prev, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4);
54
-		OUT_RING  (prev, fctx->sema.handle);
55
-		OUT_RING  (prev, 0);
56
-		OUT_RING  (prev, value + 0);
57
-		OUT_RING  (prev, value + 1);
58
-		FIRE_RING (prev);
57
+		PUSH_MTHD(ppush, NV176E, SET_CONTEXT_DMA_SEMAPHORE, fctx->sema.handle,
58
+					 SEMAPHORE_OFFSET, 0,
59
+					 SEMAPHORE_ACQUIRE, value + 0,
60
+					 SEMAPHORE_RELEASE, value + 1);
61
+		PUSH_KICK(ppush);
59
62
 	}
60
63
 
61
-	if (!ret && !(ret = RING_SPACE(chan, 5))) {
62
-		BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4);
63
-		OUT_RING  (chan, fctx->sema.handle);
64
-		OUT_RING  (chan, 0);
65
-		OUT_RING  (chan, value + 1);
66
-		OUT_RING  (chan, value + 2);
67
-		FIRE_RING (chan);
64
+	if (!ret && !(ret = PUSH_WAIT(npush, 5))) {
65
+		PUSH_MTHD(npush, NV176E, SET_CONTEXT_DMA_SEMAPHORE, fctx->sema.handle,
66
+					 SEMAPHORE_OFFSET, 0,
67
+					 SEMAPHORE_ACQUIRE, value + 1,
68
+					 SEMAPHORE_RELEASE, value + 2);
69
+		PUSH_KICK(npush);
68
70
 	}
69
71
 
70
72
 	mutex_unlock(&cli->mutex);
..
..
@@ -76,7 +78,7 @@
76
78
 {
77
79
 	struct nv10_fence_priv *priv = chan->drm->fence;
78
80
 	struct nv10_fence_chan *fctx;
79
-	struct ttm_mem_reg *reg = &priv->bo->bo.mem;
81
+	struct ttm_resource *reg = &priv->bo->bo.mem;
80
82
 	u32 start = reg->start * PAGE_SIZE;
81
83
 	u32 limit = start + reg->size - 1;
82
84
 	int ret = 0;
..
..
@@ -90,7 +92,8 @@
90
92
 	fctx->base.read = nv10_fence_read;
91
93
 	fctx->base.sync = nv17_fence_sync;
92
94
 
93
-	ret = nvif_object_init(&chan->user, NvSema, NV_DMA_FROM_MEMORY,
95
+	ret = nvif_object_ctor(&chan->user, "fenceCtxDma", NvSema,
96
+			       NV_DMA_FROM_MEMORY,
94
97
 			       &(struct nv_dma_v0) {
95
98
 					.target = NV_DMA_V0_TARGET_VRAM,
96
99
 					.access = NV_DMA_V0_ACCESS_RDWR,
..
..
@@ -127,10 +130,11 @@
127
130
 	priv->base.context_del = nv10_fence_context_del;
128
131
 	spin_lock_init(&priv->lock);
129
132
 
130
-	ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
133
+	ret = nouveau_bo_new(&drm->client, 4096, 0x1000,
134
+			     NOUVEAU_GEM_DOMAIN_VRAM,
131
135
 			     0, 0x0000, NULL, NULL, &priv->bo);
132
136
 	if (!ret) {
133
-		ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM, false);
137
+		ret = nouveau_bo_pin(priv->bo, NOUVEAU_GEM_DOMAIN_VRAM, false);
134
138
 		if (!ret) {
135
139
 			ret = nouveau_bo_map(priv->bo);
136
140
 			if (ret)