kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/drivers/gpu/drm/nouveau/nv04_fbcon.c
..
..
@@ -21,10 +21,12 @@
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  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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  * DEALINGS IN THE SOFTWARE.
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  */
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-
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+#define NVIF_DEBUG_PRINT_DISABLE
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 #include "nouveau_drv.h"
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 #include "nouveau_dma.h"
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 #include "nouveau_fbcon.h"
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+
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+#include <nvif/push006c.h>
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30
 
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 int
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 nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
..
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@@ -32,17 +34,17 @@
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 	struct nouveau_fbdev *nfbdev = info->par;
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 	struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev);
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 	struct nouveau_channel *chan = drm->channel;
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+	struct nvif_push *push = chan->chan.push;
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 	int ret;
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39
 
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-	ret = RING_SPACE(chan, 4);
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+	ret = PUSH_WAIT(push, 4);
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 	if (ret)
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 		return ret;
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43
 
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-	BEGIN_NV04(chan, NvSubImageBlit, 0x0300, 3);
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-	OUT_RING(chan, (region->sy << 16) | region->sx);
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-	OUT_RING(chan, (region->dy << 16) | region->dx);
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-	OUT_RING(chan, (region->height << 16) | region->width);
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-	FIRE_RING(chan);
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+	PUSH_NVSQ(push, NV05F, 0x0300, (region->sy << 16) | region->sx,
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+			       0x0304, (region->dy << 16) | region->dx,
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+			       0x0308, (region->height << 16) | region->width);
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+	PUSH_KICK(push);
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 	return 0;
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 }
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..
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@@ -52,24 +54,22 @@
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 	struct nouveau_fbdev *nfbdev = info->par;
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 	struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev);
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 	struct nouveau_channel *chan = drm->channel;
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+	struct nvif_push *push = chan->chan.push;
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 	int ret;
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59
 
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-	ret = RING_SPACE(chan, 7);
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+	ret = PUSH_WAIT(push, 7);
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 	if (ret)
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 		return ret;
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63
 
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-	BEGIN_NV04(chan, NvSubGdiRect, 0x02fc, 1);
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-	OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3);
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-	BEGIN_NV04(chan, NvSubGdiRect, 0x03fc, 1);
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+	PUSH_NVSQ(push, NV04A, 0x02fc, (rect->rop != ROP_COPY) ? 1 : 3);
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 	if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
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 	    info->fix.visual == FB_VISUAL_DIRECTCOLOR)
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-		OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]);
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+		PUSH_NVSQ(push, NV04A, 0x03fc, ((uint32_t *)info->pseudo_palette)[rect->color]);
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 	else
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-		OUT_RING(chan, rect->color);
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-	BEGIN_NV04(chan, NvSubGdiRect, 0x0400, 2);
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-	OUT_RING(chan, (rect->dx << 16) | rect->dy);
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-	OUT_RING(chan, (rect->width << 16) | rect->height);
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-	FIRE_RING(chan);
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+		PUSH_NVSQ(push, NV04A, 0x03fc, rect->color);
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+	PUSH_NVSQ(push, NV04A, 0x0400, (rect->dx << 16) | rect->dy,
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+			       0x0404, (rect->width << 16) | rect->height);
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+	PUSH_KICK(push);
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 	return 0;
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 }
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..
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@@ -79,6 +79,7 @@
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 	struct nouveau_fbdev *nfbdev = info->par;
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 	struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev);
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 	struct nouveau_channel *chan = drm->channel;
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+	struct nvif_push *push = chan->chan.push;
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 	uint32_t fg;
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 	uint32_t bg;
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 	uint32_t dsize;
..
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@@ -88,7 +89,7 @@
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 	if (image->depth != 1)
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 		return -ENODEV;
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-	ret = RING_SPACE(chan, 8);
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+	ret = PUSH_WAIT(push, 8);
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 	if (ret)
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 		return ret;
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@@ -101,31 +102,29 @@
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 		bg = image->bg_color;
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 	}
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-	BEGIN_NV04(chan, NvSubGdiRect, 0x0be4, 7);
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-	OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff));
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-	OUT_RING(chan, ((image->dy + image->height) << 16) |
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-			 ((image->dx + image->width) & 0xffff));
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-	OUT_RING(chan, bg);
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-	OUT_RING(chan, fg);
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-	OUT_RING(chan, (image->height << 16) | ALIGN(image->width, 8));
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-	OUT_RING(chan, (image->height << 16) | image->width);
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-	OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff));
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+	PUSH_NVSQ(push, NV04A, 0x0be4, (image->dy << 16) | (image->dx & 0xffff),
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+			       0x0be8, ((image->dy + image->height) << 16) |
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+				       ((image->dx + image->width) & 0xffff),
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+			       0x0bec, bg,
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+			       0x0bf0, fg,
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+			       0x0bf4, (image->height << 16) | ALIGN(image->width, 8),
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+			       0x0bf8, (image->height << 16) | image->width,
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+			       0x0bfc, (image->dy << 16) | (image->dx & 0xffff));
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 	dsize = ALIGN(ALIGN(image->width, 8) * image->height, 32) >> 5;
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 	while (dsize) {
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 		int iter_len = dsize > 128 ? 128 : dsize;
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-		ret = RING_SPACE(chan, iter_len + 1);
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+		ret = PUSH_WAIT(push, iter_len + 1);
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 		if (ret)
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 			return ret;
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-		BEGIN_NV04(chan, NvSubGdiRect, 0x0c00, iter_len);
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-		OUT_RINGp(chan, data, iter_len);
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+		PUSH_NVSQ(push, NV04A, 0x0c00, data, iter_len);
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 		data += iter_len;
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 		dsize -= iter_len;
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 	}
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-	FIRE_RING(chan);
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+	PUSH_KICK(push);
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 	return 0;
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 }
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@@ -137,6 +136,7 @@
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 	struct nouveau_drm *drm = nouveau_drm(dev);
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 	struct nouveau_channel *chan = drm->channel;
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 	struct nvif_device *device = &drm->client.device;
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+	struct nvif_push *push = chan->chan.push;
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 	int surface_fmt, pattern_fmt, rect_fmt;
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 	int ret;
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@@ -168,110 +168,90 @@
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 		return -EINVAL;
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 	}
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-	ret = nvif_object_init(&chan->user, 0x0062,
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+	ret = nvif_object_ctor(&chan->user, "fbconCtxSurf2d", 0x0062,
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 			       device->info.family >= NV_DEVICE_INFO_V0_CELSIUS ?
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 			       0x0062 : 0x0042, NULL, 0, &nfbdev->surf2d);
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 	if (ret)
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 		return ret;
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-	ret = nvif_object_init(&chan->user, 0x0019, 0x0019, NULL, 0,
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-			       &nfbdev->clip);
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+	ret = nvif_object_ctor(&chan->user, "fbconCtxClip", 0x0019, 0x0019,
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+			       NULL, 0, &nfbdev->clip);
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 	if (ret)
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 		return ret;
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-	ret = nvif_object_init(&chan->user, 0x0043, 0x0043, NULL, 0,
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-			       &nfbdev->rop);
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+	ret = nvif_object_ctor(&chan->user, "fbconCtxRop", 0x0043, 0x0043,
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+			       NULL, 0, &nfbdev->rop);
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 	if (ret)
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 		return ret;
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-	ret = nvif_object_init(&chan->user, 0x0044, 0x0044, NULL, 0,
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-			       &nfbdev->patt);
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+	ret = nvif_object_ctor(&chan->user, "fbconCtxPatt", 0x0044, 0x0044,
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+			       NULL, 0, &nfbdev->patt);
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 	if (ret)
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 		return ret;
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-	ret = nvif_object_init(&chan->user, 0x004a, 0x004a, NULL, 0,
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-			       &nfbdev->gdi);
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+	ret = nvif_object_ctor(&chan->user, "fbconGdiRectText", 0x004a, 0x004a,
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+			       NULL, 0, &nfbdev->gdi);
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 	if (ret)
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 		return ret;
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-	ret = nvif_object_init(&chan->user, 0x005f,
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+	ret = nvif_object_ctor(&chan->user, "fbconImageBlit", 0x005f,
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 			       device->info.chipset >= 0x11 ? 0x009f : 0x005f,
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 			       NULL, 0, &nfbdev->blit);
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 	if (ret)
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 		return ret;
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-	if (RING_SPACE(chan, 49 + (device->info.chipset >= 0x11 ? 4 : 0))) {
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+	if (PUSH_WAIT(push, 49 + (device->info.chipset >= 0x11 ? 4 : 0))) {
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 		nouveau_fbcon_gpu_lockup(info);
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 		return 0;
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 	}
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-	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
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-	OUT_RING(chan, nfbdev->surf2d.handle);
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-	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0184, 2);
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-	OUT_RING(chan, chan->vram.handle);
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-	OUT_RING(chan, chan->vram.handle);
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-	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 4);
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-	OUT_RING(chan, surface_fmt);
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-	OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16));
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-	OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
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-	OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
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+	PUSH_NVSQ(push, NV042, 0x0000, nfbdev->surf2d.handle);
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+	PUSH_NVSQ(push, NV042, 0x0184, chan->vram.handle,
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+			       0x0188, chan->vram.handle);
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+	PUSH_NVSQ(push, NV042, 0x0300, surface_fmt,
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+			       0x0304, info->fix.line_length | (info->fix.line_length << 16),
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+			       0x0308, info->fix.smem_start - dev->mode_config.fb_base,
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+			       0x030c, info->fix.smem_start - dev->mode_config.fb_base);
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-	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
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-	OUT_RING(chan, nfbdev->rop.handle);
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-	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 1);
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-	OUT_RING(chan, 0x55);
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+	PUSH_NVSQ(push, NV043, 0x0000, nfbdev->rop.handle);
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+	PUSH_NVSQ(push, NV043, 0x0300, 0x55);
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218
 
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-	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
225
-	OUT_RING(chan, nfbdev->patt.handle);
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-	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 8);
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-	OUT_RING(chan, pattern_fmt);
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+	PUSH_NVSQ(push, NV044, 0x0000, nfbdev->patt.handle);
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+	PUSH_NVSQ(push, NV044, 0x0300, pattern_fmt,
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 #ifdef __BIG_ENDIAN
229
-	OUT_RING(chan, 2);
222
+			       0x0304, 2,
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 #else
231
-	OUT_RING(chan, 1);
224
+			       0x0304, 1,
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225
 #endif
233
-	OUT_RING(chan, 0);
234
-	OUT_RING(chan, 1);
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-	OUT_RING(chan, ~0);
236
-	OUT_RING(chan, ~0);
237
-	OUT_RING(chan, ~0);
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-	OUT_RING(chan, ~0);
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+			       0x0308, 0,
227
+			       0x030c, 1,
228
+			       0x0310, ~0,
229
+			       0x0314, ~0,
230
+			       0x0318, ~0,
231
+			       0x031c, ~0);
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232
 
240
-	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
241
-	OUT_RING(chan, nfbdev->clip.handle);
242
-	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 2);
243
-	OUT_RING(chan, 0);
244
-	OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual);
233
+	PUSH_NVSQ(push, NV019, 0x0000, nfbdev->clip.handle);
234
+	PUSH_NVSQ(push, NV019, 0x0300, 0,
235
+			       0x0304, (info->var.yres_virtual << 16) | info->var.xres_virtual);
245
236
 
246
-	BEGIN_NV04(chan, NvSubImageBlit, 0x0000, 1);
247
-	OUT_RING(chan, nfbdev->blit.handle);
248
-	BEGIN_NV04(chan, NvSubImageBlit, 0x019c, 1);
249
-	OUT_RING(chan, nfbdev->surf2d.handle);
250
-	BEGIN_NV04(chan, NvSubImageBlit, 0x02fc, 1);
251
-	OUT_RING(chan, 3);
252
-	if (device->info.chipset >= 0x11 /*XXX: oclass == 0x009f*/) {
253
-		BEGIN_NV04(chan, NvSubImageBlit, 0x0120, 3);
254
-		OUT_RING(chan, 0);
255
-		OUT_RING(chan, 1);
256
-		OUT_RING(chan, 2);
237
+	PUSH_NVSQ(push, NV05F, 0x0000, nfbdev->blit.handle);
238
+	PUSH_NVSQ(push, NV05F, 0x019c, nfbdev->surf2d.handle);
239
+	PUSH_NVSQ(push, NV05F, 0x02fc, 3);
240
+	if (nfbdev->blit.oclass == 0x009f) {
241
+		PUSH_NVSQ(push, NV09F, 0x0120, 0,
242
+				       0x0124, 1,
243
+				       0x0128, 2);
257
244
 	}
258
245
 
259
-	BEGIN_NV04(chan, NvSubGdiRect, 0x0000, 1);
260
-	OUT_RING(chan, nfbdev->gdi.handle);
261
-	BEGIN_NV04(chan, NvSubGdiRect, 0x0198, 1);
262
-	OUT_RING(chan, nfbdev->surf2d.handle);
263
-	BEGIN_NV04(chan, NvSubGdiRect, 0x0188, 2);
264
-	OUT_RING(chan, nfbdev->patt.handle);
265
-	OUT_RING(chan, nfbdev->rop.handle);
266
-	BEGIN_NV04(chan, NvSubGdiRect, 0x0304, 1);
267
-	OUT_RING(chan, 1);
268
-	BEGIN_NV04(chan, NvSubGdiRect, 0x0300, 1);
269
-	OUT_RING(chan, rect_fmt);
270
-	BEGIN_NV04(chan, NvSubGdiRect, 0x02fc, 1);
271
-	OUT_RING(chan, 3);
246
+	PUSH_NVSQ(push, NV04A, 0x0000, nfbdev->gdi.handle);
247
+	PUSH_NVSQ(push, NV04A, 0x0198, nfbdev->surf2d.handle);
248
+	PUSH_NVSQ(push, NV04A, 0x0188, nfbdev->patt.handle,
249
+			       0x018c, nfbdev->rop.handle);
250
+	PUSH_NVSQ(push, NV04A, 0x0304, 1);
251
+	PUSH_NVSQ(push, NV04A, 0x0300, rect_fmt);
252
+	PUSH_NVSQ(push, NV04A, 0x02fc, 3);
272
253
 
273
-	FIRE_RING(chan);
274
-
254
+	PUSH_KICK(push);
275
255
 	return 0;
276
256
 }
277
257