kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/drivers/gpu/drm/nouveau/nouveau_dma.h
..
..
@@ -45,17 +45,6 @@
45
45
  */
46
46
 #define NOUVEAU_DMA_SKIPS (128 / 4)
47
47
 
48
-/* Hardcoded object assignments to subchannels (subchannel id). */
49
-enum {
50
-	NvSubCtxSurf2D  = 0,
51
-	NvSubSw		= 1,
52
-	NvSubImageBlit  = 2,
53
-	NvSubGdiRect    = 3,
54
-
55
-	NvSub2D		= 3, /* DO NOT CHANGE - hardcoded for kepler gr fifo */
56
-	NvSubCopy	= 4, /* DO NOT CHANGE - hardcoded for kepler gr fifo */
57
-};
58
-
59
48
 /* Object handles - for stuff that's doesn't use handle == oclass. */
60
49
 enum {
61
50
 	NvDmaFB		= 0x80000002,
..
..
@@ -65,23 +54,6 @@
65
54
 	NvEvoSema0	= 0x80000010,
66
55
 	NvEvoSema1	= 0x80000011,
67
56
 };
68
-
69
-#define NV_MEMORY_TO_MEMORY_FORMAT                                    0x00000039
70
-#define NV_MEMORY_TO_MEMORY_FORMAT_NAME                               0x00000000
71
-#define NV_MEMORY_TO_MEMORY_FORMAT_SET_REF                            0x00000050
72
-#define NV_MEMORY_TO_MEMORY_FORMAT_NOP                                0x00000100
73
-#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY                             0x00000104
74
-#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE                 0x00000000
75
-#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE_LE_AWAKEN       0x00000001
76
-#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY                         0x00000180
77
-#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE                         0x00000184
78
-#define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN                          0x0000030c
79
-
80
-#define NV50_MEMORY_TO_MEMORY_FORMAT                                  0x00005039
81
-#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK200                           0x00000200
82
-#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK21C                           0x0000021c
83
-#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH                   0x00000238
84
-#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH                  0x0000023c
85
57
 
86
58
 static __must_check inline int
87
59
 RING_SPACE(struct nouveau_channel *chan, int size)
..
..
@@ -100,39 +72,6 @@
100
72
 OUT_RING(struct nouveau_channel *chan, int data)
101
73
 {
102
74
 	nouveau_bo_wr32(chan->push.buffer, chan->dma.cur++, data);
103
-}
104
-
105
-extern void
106
-OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords);
107
-
108
-static inline void
109
-BEGIN_NV04(struct nouveau_channel *chan, int subc, int mthd, int size)
110
-{
111
-	OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd);
112
-}
113
-
114
-static inline void
115
-BEGIN_NI04(struct nouveau_channel *chan, int subc, int mthd, int size)
116
-{
117
-	OUT_RING(chan, 0x40000000 | (subc << 13) | (size << 18) | mthd);
118
-}
119
-
120
-static inline void
121
-BEGIN_NVC0(struct nouveau_channel *chan, int subc, int mthd, int size)
122
-{
123
-	OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2));
124
-}
125
-
126
-static inline void
127
-BEGIN_NIC0(struct nouveau_channel *chan, int subc, int mthd, int size)
128
-{
129
-	OUT_RING(chan, 0x60000000 | (size << 16) | (subc << 13) | (mthd >> 2));
130
-}
131
-
132
-static inline void
133
-BEGIN_IMC0(struct nouveau_channel *chan, int subc, int mthd, u16 data)
134
-{
135
-	OUT_RING(chan, 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2));
136
75
 }
137
76
 
138
77
 #define WRITE_PUT(val) do {                                                    \
..
..
@@ -163,25 +102,6 @@
163
102
 {
164
103
 	chan->dma.cur = chan->dma.put;
165
104
 }
166
-
167
-/* FIFO methods */
168
-#define NV01_SUBCHAN_OBJECT                                          0x00000000
169
-#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH                          0x00000010
170
-#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW                           0x00000014
171
-#define NV84_SUBCHAN_SEMAPHORE_SEQUENCE                              0x00000018
172
-#define NV84_SUBCHAN_SEMAPHORE_TRIGGER                               0x0000001c
173
-#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL                 0x00000001
174
-#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG                    0x00000002
175
-#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL                0x00000004
176
-#define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD                         0x00001000
177
-#define NV84_SUBCHAN_UEVENT                                          0x00000020
178
-#define NV84_SUBCHAN_WRCACHE_FLUSH                                   0x00000024
179
-#define NV10_SUBCHAN_REF_CNT                                         0x00000050
180
-#define NV11_SUBCHAN_DMA_SEMAPHORE                                   0x00000060
181
-#define NV11_SUBCHAN_SEMAPHORE_OFFSET                                0x00000064
182
-#define NV11_SUBCHAN_SEMAPHORE_ACQUIRE                               0x00000068
183
-#define NV11_SUBCHAN_SEMAPHORE_RELEASE                               0x0000006c
184
-#define NV40_SUBCHAN_YIELD                                           0x00000080
185
105
 
186
106
 /* NV_SW object class */
187
107
 #define NV_SW_DMA_VBLSEM                                             0x0000018c