kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/drivers/gpu/drm/nouveau/dispnv50/head827d.c
..
..
@@ -22,85 +22,128 @@
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 #include "head.h"
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 #include "core.h"
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24
 
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-static void
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+#include <nvif/push507c.h>
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+
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+#include <nvhw/class/cl827d.h>
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+
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+static int
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 head827d_curs_clr(struct nv50_head *head)
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 {
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-	struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
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-	u32 *push;
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-	if ((push = evo_wait(core, 4))) {
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-		evo_mthd(push, 0x0880 + head->base.index * 0x400, 1);
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-		evo_data(push, 0x05000000);
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-		evo_mthd(push, 0x089c + head->base.index * 0x400, 1);
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-		evo_data(push, 0x00000000);
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-		evo_kick(push, core);
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-	}
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+	struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
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+	const int i = head->base.index;
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+	int ret;
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+
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+	if ((ret = PUSH_WAIT(push, 4)))
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+		return ret;
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+
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+	PUSH_MTHD(push, NV827D, HEAD_SET_CONTROL_CURSOR(i),
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+		  NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) |
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+		  NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, FORMAT, A8R8G8B8) |
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+		  NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, SIZE, W64_H64));
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+
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+	PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_CURSOR(i), 0x00000000);
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+	return 0;
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 }
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47
 
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-static void
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+static int
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 head827d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
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50
 {
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-	struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
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-	u32 *push;
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-	if ((push = evo_wait(core, 5))) {
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-		evo_mthd(push, 0x0880 + head->base.index * 0x400, 2);
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-		evo_data(push, 0x80000000 | asyh->curs.layout << 26 |
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-					    asyh->curs.format << 24);
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-		evo_data(push, asyh->curs.offset >> 8);
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-		evo_mthd(push, 0x089c + head->base.index * 0x400, 1);
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-		evo_data(push, asyh->curs.handle);
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-		evo_kick(push, core);
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-	}
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+	struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
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+	const int i = head->base.index;
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+	int ret;
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+
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+	if ((ret = PUSH_WAIT(push, 5)))
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+		return ret;
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+
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+	PUSH_MTHD(push, NV827D, HEAD_SET_CONTROL_CURSOR(i),
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+		  NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |
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+		  NVVAL(NV827D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) |
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+		  NVVAL(NV827D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) |
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+		  NVVAL(NV827D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_X, 0) |
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+		  NVVAL(NV827D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_Y, 0) |
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+		  NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, COMPOSITION, ALPHA_BLEND) |
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+		  NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, SUB_OWNER, NONE),
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+
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+				HEAD_SET_OFFSET_CURSOR(i), asyh->curs.offset >> 8);
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+
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+	PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle);
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+	return 0;
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 }
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72
 
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-static void
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+static int
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 head827d_core_set(struct nv50_head *head, struct nv50_head_atom *asyh)
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 {
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-	struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
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-	u32 *push;
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-	if ((push = evo_wait(core, 9))) {
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-		evo_mthd(push, 0x0860 + head->base.index * 0x400, 1);
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-		evo_data(push, asyh->core.offset >> 8);
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-		evo_mthd(push, 0x0868 + head->base.index * 0x400, 4);
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-		evo_data(push, asyh->core.h << 16 | asyh->core.w);
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-		evo_data(push, asyh->core.layout << 20 |
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-			       (asyh->core.pitch >> 8) << 8 |
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-			       asyh->core.blocks << 8 |
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-			       asyh->core.blockh);
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-		evo_data(push, asyh->core.format << 8);
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-		evo_data(push, asyh->core.handle);
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-		evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1);
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-		evo_data(push, asyh->core.y << 16 | asyh->core.x);
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-		evo_kick(push, core);
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-	}
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+	struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
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+	const int i = head->base.index;
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+	int ret;
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+
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+	if ((ret = PUSH_WAIT(push, 9)))
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+		return ret;
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+
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+	PUSH_MTHD(push, NV827D, HEAD_SET_OFFSET(i, 0),
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+		  NVVAL(NV827D, HEAD_SET_OFFSET, ORIGIN, asyh->core.offset >> 8));
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+
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+	PUSH_MTHD(push, NV827D, HEAD_SET_SIZE(i),
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+		  NVVAL(NV827D, HEAD_SET_SIZE, WIDTH, asyh->core.w) |
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+		  NVVAL(NV827D, HEAD_SET_SIZE, HEIGHT, asyh->core.h),
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+
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+				HEAD_SET_STORAGE(i),
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+		  NVVAL(NV827D, HEAD_SET_STORAGE, BLOCK_HEIGHT, asyh->core.blockh) |
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+		  NVVAL(NV827D, HEAD_SET_STORAGE, PITCH, asyh->core.pitch >> 8) |
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+		  NVVAL(NV827D, HEAD_SET_STORAGE, PITCH, asyh->core.blocks) |
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+		  NVVAL(NV827D, HEAD_SET_STORAGE, MEMORY_LAYOUT, asyh->core.layout),
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+
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+				HEAD_SET_PARAMS(i),
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+		  NVVAL(NV827D, HEAD_SET_PARAMS, FORMAT, asyh->core.format) |
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+		  NVDEF(NV827D, HEAD_SET_PARAMS, SUPER_SAMPLE, X1_AA) |
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+		  NVDEF(NV827D, HEAD_SET_PARAMS, GAMMA, LINEAR),
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+
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+				HEAD_SET_CONTEXT_DMAS_ISO(i, 0),
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+		  NVVAL(NV827D, HEAD_SET_CONTEXT_DMAS_ISO, HANDLE, asyh->core.handle));
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+
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+	PUSH_MTHD(push, NV827D, HEAD_SET_VIEWPORT_POINT_IN(i, 0),
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+		  NVVAL(NV827D, HEAD_SET_VIEWPORT_POINT_IN, X, asyh->core.x) |
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+		  NVVAL(NV827D, HEAD_SET_VIEWPORT_POINT_IN, Y, asyh->core.y));
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+	return 0;
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 }
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109
 
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-static void
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+static int
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 head827d_olut_clr(struct nv50_head *head)
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 {
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-	struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
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-	u32 *push;
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-	if ((push = evo_wait(core, 4))) {
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-		evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1);
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-		evo_data(push, 0x00000000);
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-		evo_mthd(push, 0x085c + (head->base.index * 0x400), 1);
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-		evo_data(push, 0x00000000);
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-		evo_kick(push, core);
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-	}
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+	struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
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+	const int i = head->base.index;
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+	int ret;
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+
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+	if ((ret = PUSH_WAIT(push, 4)))
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+		return ret;
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+
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+	PUSH_MTHD(push, NV827D, HEAD_SET_BASE_LUT_LO(i),
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+		  NVDEF(NV827D, HEAD_SET_BASE_LUT_LO, ENABLE, DISABLE));
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+
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+	PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_LUT(i), 0x00000000);
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+	return 0;
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 }
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-static void
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+static int
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 head827d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
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 {
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-	struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
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-	u32 *push;
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-	if ((push = evo_wait(core, 5))) {
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-		evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2);
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-		evo_data(push, 0x80000000 | asyh->olut.mode << 30);
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-		evo_data(push, asyh->olut.offset >> 8);
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-		evo_mthd(push, 0x085c + (head->base.index * 0x400), 1);
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-		evo_data(push, asyh->olut.handle);
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-		evo_kick(push, core);
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-	}
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+	struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
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+	const int i = head->base.index;
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+	int ret;
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+
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+	if ((ret = PUSH_WAIT(push, 5)))
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+		return ret;
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+
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+	PUSH_MTHD(push, NV827D, HEAD_SET_BASE_LUT_LO(i),
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+		  NVDEF(NV827D, HEAD_SET_BASE_LUT_LO, ENABLE, ENABLE) |
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+		  NVVAL(NV827D, HEAD_SET_BASE_LUT_LO, MODE, asyh->olut.mode) |
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+		  NVVAL(NV827D, HEAD_SET_BASE_LUT_LO, ORIGIN, 0),
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+
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+				HEAD_SET_BASE_LUT_HI(i),
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+		  NVVAL(NV827D, HEAD_SET_BASE_LUT_HI, ORIGIN, asyh->olut.offset >> 8));
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+
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+	PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_LUT(i), asyh->olut.handle);
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+	return 0;
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 }
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148
 
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149
 const struct nv50_head_func
..
..
@@ -108,6 +151,7 @@
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 	.view = head507d_view,
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 	.mode = head507d_mode,
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 	.olut = head507d_olut,
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+	.olut_size = 256,
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 	.olut_set = head827d_olut_set,
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 	.olut_clr = head827d_olut_clr,
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 	.core_calc = head507d_core_calc,