kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/drivers/gpu/drm/nouveau/dispnv50/base827c.c
..
..
@@ -21,27 +21,60 @@
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  */
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 #include "base.h"
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-static void
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+#include <nvif/push507c.h>
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+
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+#include <nvhw/class/cl827c.h>
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+
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+static int
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 base827c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
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 {
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-	u32 *push;
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-	if ((push = evo_wait(&wndw->wndw, 10))) {
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-		evo_mthd(push, 0x0084, 1);
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-		evo_data(push, asyw->image.mode << 8 |
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-			       asyw->image.interval << 4);
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-		evo_mthd(push, 0x00c0, 1);
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-		evo_data(push, asyw->image.handle[0]);
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-		evo_mthd(push, 0x0800, 5);
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-		evo_data(push, asyw->image.offset[0] >> 8);
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-		evo_data(push, 0x00000000);
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-		evo_data(push, asyw->image.h << 16 | asyw->image.w);
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-		evo_data(push, asyw->image.layout << 20 |
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-			       (asyw->image.pitch[0] >> 8) << 8 |
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-			       asyw->image.blocks[0] << 8 |
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-			       asyw->image.blockh);
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-		evo_data(push, asyw->image.format << 8);
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-		evo_kick(push, &wndw->wndw);
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+	struct nvif_push *push = wndw->wndw.push;
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+	int ret;
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+
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+	if ((ret = PUSH_WAIT(push, 13)))
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+		return ret;
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+
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+	PUSH_MTHD(push, NV827C, SET_PRESENT_CONTROL,
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+		  NVVAL(NV827C, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) |
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+		  NVVAL(NV827C, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval));
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+
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+	PUSH_MTHD(push, NV827C, SET_CONTEXT_DMAS_ISO(0), asyw->image.handle, 1);
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+
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+	if (asyw->image.format == NV827C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16) {
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+		PUSH_MTHD(push, NV827C, SET_PROCESSING,
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+			  NVDEF(NV827C, SET_PROCESSING, USE_GAIN_OFS, ENABLE),
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+
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+					SET_CONVERSION,
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+			  NVVAL(NV827C, SET_CONVERSION, GAIN, 0) |
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+			  NVVAL(NV827C, SET_CONVERSION, OFS, 0x64));
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+	} else {
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+		PUSH_MTHD(push, NV827C, SET_PROCESSING,
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+			  NVDEF(NV827C, SET_PROCESSING, USE_GAIN_OFS, DISABLE),
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+
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+					SET_CONVERSION,
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+			  NVVAL(NV827C, SET_CONVERSION, GAIN, 0) |
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+			  NVVAL(NV827C, SET_CONVERSION, OFS, 0));
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 	}
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+
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+	PUSH_MTHD(push, NV827C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8,
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+				SURFACE_SET_OFFSET(0, 1), 0x00000000,
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+
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+				SURFACE_SET_SIZE(0),
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+		  NVVAL(NV827C, SURFACE_SET_SIZE, WIDTH, asyw->image.w) |
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+		  NVVAL(NV827C, SURFACE_SET_SIZE, HEIGHT, asyw->image.h),
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+
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+				SURFACE_SET_STORAGE(0),
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+		  NVVAL(NV827C, SURFACE_SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) |
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+		  NVVAL(NV827C, SURFACE_SET_STORAGE, PITCH, asyw->image.pitch[0] >> 8) |
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+		  NVVAL(NV827C, SURFACE_SET_STORAGE, PITCH, asyw->image.blocks[0]) |
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+		  NVVAL(NV827C, SURFACE_SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout),
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+
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+				SURFACE_SET_PARAMS(0),
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+		  NVVAL(NV827C, SURFACE_SET_PARAMS, FORMAT, asyw->image.format) |
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+		  NVDEF(NV827C, SURFACE_SET_PARAMS, SUPER_SAMPLE, X1_AA) |
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+		  NVDEF(NV827C, SURFACE_SET_PARAMS, GAMMA, LINEAR) |
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+		  NVDEF(NV827C, SURFACE_SET_PARAMS, LAYOUT, FRM));
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+	return 0;
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 }
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 static const struct nv50_wndw_func