kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
..
..
@@ -1,15 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
1
2
 /*
2
3
  * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 and
6
- * only version 2 as published by the Free Software Foundation.
7
- *
8
- * This program is distributed in the hope that it will be useful,
9
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
10
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11
- * GNU General Public License for more details.
12
- *
13
4
  */
14
5
 
15
6
 #define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
..
..
@@ -44,14 +35,7 @@
44
35
 
45
36
 #define DPU_ENC_WR_PTR_START_TIMEOUT_US 20000
46
37
 
47
-static inline int _dpu_encoder_phys_cmd_get_idle_timeout(
48
-		struct dpu_encoder_phys_cmd *cmd_enc)
49
-{
50
-	return KICKOFF_TIMEOUT_MS;
51
-}
52
-
53
-static inline bool dpu_encoder_phys_cmd_is_master(
54
-		struct dpu_encoder_phys *phys_enc)
38
+static bool dpu_encoder_phys_cmd_is_master(struct dpu_encoder_phys *phys_enc)
55
39
 {
56
40
 	return (phys_enc->split_role != ENC_ROLE_SLAVE) ? true : false;
57
41
 }
..
..
@@ -61,8 +45,7 @@
61
45
 		const struct drm_display_mode *mode,
62
46
 		struct drm_display_mode *adj_mode)
63
47
 {
64
-	if (phys_enc)
65
-		DPU_DEBUG_CMDENC(to_dpu_encoder_phys_cmd(phys_enc), "\n");
48
+	DPU_DEBUG_CMDENC(to_dpu_encoder_phys_cmd(phys_enc), "\n");
66
49
 	return true;
67
50
 }
68
51
 
..
..
@@ -74,11 +57,8 @@
74
57
 	struct dpu_hw_ctl *ctl;
75
58
 	struct dpu_hw_intf_cfg intf_cfg = { 0 };
76
59
 
77
-	if (!phys_enc)
78
-		return;
79
-
80
60
 	ctl = phys_enc->hw_ctl;
81
-	if (!ctl || !ctl->ops.setup_intf_cfg)
61
+	if (!ctl->ops.setup_intf_cfg)
82
62
 		return;
83
63
 
84
64
 	intf_cfg.intf = phys_enc->intf_idx;
..
..
@@ -95,7 +75,7 @@
95
75
 	int new_cnt;
96
76
 	u32 event = DPU_ENCODER_FRAME_EVENT_DONE;
97
77
 
98
-	if (!phys_enc || !phys_enc->hw_pp)
78
+	if (!phys_enc->hw_pp)
99
79
 		return;
100
80
 
101
81
 	DPU_ATRACE_BEGIN("pp_done_irq");
..
..
@@ -122,7 +102,7 @@
122
102
 	struct dpu_encoder_phys *phys_enc = arg;
123
103
 	struct dpu_encoder_phys_cmd *cmd_enc;
124
104
 
125
-	if (!phys_enc || !phys_enc->hw_pp)
105
+	if (!phys_enc->hw_pp)
126
106
 		return;
127
107
 
128
108
 	DPU_ATRACE_BEGIN("rd_ptr_irq");
..
..
@@ -140,13 +120,8 @@
140
120
 static void dpu_encoder_phys_cmd_ctl_start_irq(void *arg, int irq_idx)
141
121
 {
142
122
 	struct dpu_encoder_phys *phys_enc = arg;
143
-	struct dpu_encoder_phys_cmd *cmd_enc;
144
-
145
-	if (!phys_enc || !phys_enc->hw_ctl)
146
-		return;
147
123
 
148
124
 	DPU_ATRACE_BEGIN("ctl_start_irq");
149
-	cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
150
125
 
151
126
 	atomic_add_unless(&phys_enc->pending_ctlstart_cnt, -1, 0);
152
127
 
..
..
@@ -158,9 +133,6 @@
158
133
 static void dpu_encoder_phys_cmd_underrun_irq(void *arg, int irq_idx)
159
134
 {
160
135
 	struct dpu_encoder_phys *phys_enc = arg;
161
-
162
-	if (!phys_enc)
163
-		return;
164
136
 
165
137
 	if (phys_enc->parent_ops->handle_underrun_virt)
166
138
 		phys_enc->parent_ops->handle_underrun_virt(phys_enc->parent,
..
..
@@ -196,33 +168,14 @@
196
168
 {
197
169
 	struct dpu_encoder_phys_cmd *cmd_enc =
198
170
 		to_dpu_encoder_phys_cmd(phys_enc);
199
-	struct dpu_rm *rm = &phys_enc->dpu_kms->rm;
200
-	struct dpu_rm_hw_iter iter;
201
-	int i, instance;
202
171
 
203
-	if (!phys_enc || !mode || !adj_mode) {
172
+	if (!mode || !adj_mode) {
204
173
 		DPU_ERROR("invalid args\n");
205
174
 		return;
206
175
 	}
207
176
 	phys_enc->cached_mode = *adj_mode;
208
177
 	DPU_DEBUG_CMDENC(cmd_enc, "caching mode:\n");
209
178
 	drm_mode_debug_printmodeline(adj_mode);
210
-
211
-	instance = phys_enc->split_role == ENC_ROLE_SLAVE ? 1 : 0;
212
-
213
-	/* Retrieve previously allocated HW Resources. Shouldn't fail */
214
-	dpu_rm_init_hw_iter(&iter, phys_enc->parent->base.id, DPU_HW_BLK_CTL);
215
-	for (i = 0; i <= instance; i++) {
216
-		if (dpu_rm_get_hw(rm, &iter))
217
-			phys_enc->hw_ctl = (struct dpu_hw_ctl *)iter.hw;
218
-	}
219
-
220
-	if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) {
221
-		DPU_ERROR_CMDENC(cmd_enc, "failed to init ctl: %ld\n",
222
-				PTR_ERR(phys_enc->hw_ctl));
223
-		phys_enc->hw_ctl = NULL;
224
-		return;
225
-	}
226
179
 
227
180
 	_dpu_encoder_phys_cmd_setup_irq_hw_idx(phys_enc);
228
181
 }
..
..
@@ -235,7 +188,7 @@
235
188
 	u32 frame_event = DPU_ENCODER_FRAME_EVENT_ERROR;
236
189
 	bool do_log = false;
237
190
 
238
-	if (!phys_enc || !phys_enc->hw_pp || !phys_enc->hw_ctl)
191
+	if (!phys_enc->hw_pp)
239
192
 		return -EINVAL;
240
193
 
241
194
 	cmd_enc->pp_timeout_report_cnt++;
..
..
@@ -262,7 +215,6 @@
262
215
 			  atomic_read(&phys_enc->pending_kickoff_cnt));
263
216
 
264
217
 		dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_RDPTR);
265
-		dpu_dbg_dump(false, __func__, true, true);
266
218
 	}
267
219
 
268
220
 	atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
..
..
@@ -285,11 +237,6 @@
285
237
 	struct dpu_encoder_wait_info wait_info;
286
238
 	int ret;
287
239
 
288
-	if (!phys_enc) {
289
-		DPU_ERROR("invalid encoder\n");
290
-		return -EINVAL;
291
-	}
292
-
293
240
 	wait_info.wq = &phys_enc->pending_kickoff_wq;
294
241
 	wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
295
242
 	wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
..
..
@@ -311,7 +258,7 @@
311
258
 	int ret = 0;
312
259
 	int refcount;
313
260
 
314
-	if (!phys_enc || !phys_enc->hw_pp) {
261
+	if (!phys_enc->hw_pp) {
315
262
 		DPU_ERROR("invalid encoder\n");
316
263
 		return -EINVAL;
317
264
 	}
..
..
@@ -352,13 +299,6 @@
352
299
 static void dpu_encoder_phys_cmd_irq_control(struct dpu_encoder_phys *phys_enc,
353
300
 		bool enable)
354
301
 {
355
-	struct dpu_encoder_phys_cmd *cmd_enc;
356
-
357
-	if (!phys_enc)
358
-		return;
359
-
360
-	cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
361
-
362
302
 	trace_dpu_enc_phys_cmd_irq_ctrl(DRMID(phys_enc->parent),
363
303
 			phys_enc->hw_pp->idx - PINGPONG_0,
364
304
 			enable, atomic_read(&phys_enc->vblank_refcount));
..
..
@@ -391,10 +331,9 @@
391
331
 	struct drm_display_mode *mode;
392
332
 	bool tc_enable = true;
393
333
 	u32 vsync_hz;
394
-	struct msm_drm_private *priv;
395
334
 	struct dpu_kms *dpu_kms;
396
335
 
397
-	if (!phys_enc || !phys_enc->hw_pp) {
336
+	if (!phys_enc->hw_pp) {
398
337
 		DPU_ERROR("invalid encoder\n");
399
338
 		return;
400
339
 	}
..
..
@@ -409,11 +348,6 @@
409
348
 	}
410
349
 
411
350
 	dpu_kms = phys_enc->dpu_kms;
412
-	if (!dpu_kms || !dpu_kms->dev || !dpu_kms->dev->dev_private) {
413
-		DPU_ERROR("invalid device\n");
414
-		return;
415
-	}
416
-	priv = dpu_kms->dev->dev_private;
417
351
 
418
352
 	/*
419
353
 	 * TE default: dsi byte clock calculated base on 70 fps;
..
..
@@ -431,7 +365,8 @@
431
365
 		return;
432
366
 	}
433
367
 
434
-	tc_cfg.vsync_count = vsync_hz / (mode->vtotal * mode->vrefresh);
368
+	tc_cfg.vsync_count = vsync_hz /
369
+				(mode->vtotal * drm_mode_vrefresh(mode));
435
370
 
436
371
 	/* enable external TE after kickoff to avoid premature autorefresh */
437
372
 	tc_cfg.hw_vsync_mode = 0;
..
..
@@ -451,7 +386,7 @@
451
386
 	DPU_DEBUG_CMDENC(cmd_enc,
452
387
 		"tc %d vsync_clk_speed_hz %u vtotal %u vrefresh %u\n",
453
388
 		phys_enc->hw_pp->idx - PINGPONG_0, vsync_hz,
454
-		mode->vtotal, mode->vrefresh);
389
+		mode->vtotal, drm_mode_vrefresh(mode));
455
390
 	DPU_DEBUG_CMDENC(cmd_enc,
456
391
 		"tc %d enable %u start_pos %u rd_ptr_irq %u\n",
457
392
 		phys_enc->hw_pp->idx - PINGPONG_0, tc_enable, tc_cfg.start_pos,
..
..
@@ -475,9 +410,8 @@
475
410
 	struct dpu_encoder_phys_cmd *cmd_enc =
476
411
 		to_dpu_encoder_phys_cmd(phys_enc);
477
412
 
478
-	if (!phys_enc || !phys_enc->hw_ctl || !phys_enc->hw_pp
479
-			|| !phys_enc->hw_ctl->ops.setup_intf_cfg) {
480
-		DPU_ERROR("invalid arg(s), enc %d\n", phys_enc != 0);
413
+	if (!phys_enc->hw_pp || !phys_enc->hw_ctl->ops.setup_intf_cfg) {
414
+		DPU_ERROR("invalid arg(s), enc %d\n", phys_enc != NULL);
481
415
 		return;
482
416
 	}
483
417
 
..
..
@@ -505,8 +439,8 @@
505
439
 	struct dpu_hw_ctl *ctl;
506
440
 	u32 flush_mask = 0;
507
441
 
508
-	if (!phys_enc || !phys_enc->hw_ctl || !phys_enc->hw_pp) {
509
-		DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0);
442
+	if (!phys_enc->hw_pp) {
443
+		DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != NULL);
510
444
 		return;
511
445
 	}
512
446
 
..
..
@@ -515,14 +449,11 @@
515
449
 	_dpu_encoder_phys_cmd_pingpong_config(phys_enc);
516
450
 
517
451
 	if (!dpu_encoder_phys_cmd_is_master(phys_enc))
518
-		goto skip_flush;
452
+		return;
519
453
 
520
454
 	ctl = phys_enc->hw_ctl;
521
455
 	ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->intf_idx);
522
456
 	ctl->ops.update_pending_flush(ctl, flush_mask);
523
-
524
-skip_flush:
525
-	return;
526
457
 }
527
458
 
528
459
 static void dpu_encoder_phys_cmd_enable(struct dpu_encoder_phys *phys_enc)
..
..
@@ -530,7 +461,7 @@
530
461
 	struct dpu_encoder_phys_cmd *cmd_enc =
531
462
 		to_dpu_encoder_phys_cmd(phys_enc);
532
463
 
533
-	if (!phys_enc || !phys_enc->hw_pp) {
464
+	if (!phys_enc->hw_pp) {
534
465
 		DPU_ERROR("invalid phys encoder\n");
535
466
 		return;
536
467
 	}
..
..
@@ -549,8 +480,7 @@
549
480
 static void _dpu_encoder_phys_cmd_connect_te(
550
481
 		struct dpu_encoder_phys *phys_enc, bool enable)
551
482
 {
552
-	if (!phys_enc || !phys_enc->hw_pp ||
553
-			!phys_enc->hw_pp->ops.connect_external_te)
483
+	if (!phys_enc->hw_pp || !phys_enc->hw_pp->ops.connect_external_te)
554
484
 		return;
555
485
 
556
486
 	trace_dpu_enc_phys_cmd_connect_te(DRMID(phys_enc->parent), enable);
..
..
@@ -568,7 +498,7 @@
568
498
 {
569
499
 	struct dpu_hw_pingpong *hw_pp;
570
500
 
571
-	if (!phys_enc || !phys_enc->hw_pp)
501
+	if (!phys_enc->hw_pp)
572
502
 		return -EINVAL;
573
503
 
574
504
 	if (!dpu_encoder_phys_cmd_is_master(phys_enc))
..
..
@@ -586,7 +516,7 @@
586
516
 	struct dpu_encoder_phys_cmd *cmd_enc =
587
517
 		to_dpu_encoder_phys_cmd(phys_enc);
588
518
 
589
-	if (!phys_enc || !phys_enc->hw_pp) {
519
+	if (!phys_enc->hw_pp) {
590
520
 		DPU_ERROR("invalid encoder\n");
591
521
 		return;
592
522
 	}
..
..
@@ -609,44 +539,24 @@
609
539
 	struct dpu_encoder_phys_cmd *cmd_enc =
610
540
 		to_dpu_encoder_phys_cmd(phys_enc);
611
541
 
612
-	if (!phys_enc) {
613
-		DPU_ERROR("invalid encoder\n");
614
-		return;
615
-	}
616
542
 	kfree(cmd_enc);
617
543
 }
618
544
 
619
545
 static void dpu_encoder_phys_cmd_get_hw_resources(
620
546
 		struct dpu_encoder_phys *phys_enc,
621
-		struct dpu_encoder_hw_resources *hw_res,
622
-		struct drm_connector_state *conn_state)
547
+		struct dpu_encoder_hw_resources *hw_res)
623
548
 {
624
-	struct dpu_encoder_phys_cmd *cmd_enc =
625
-		to_dpu_encoder_phys_cmd(phys_enc);
626
-
627
-	if (!phys_enc) {
628
-		DPU_ERROR("invalid encoder\n");
629
-		return;
630
-	}
631
-
632
-	if ((phys_enc->intf_idx - INTF_0) >= INTF_MAX) {
633
-		DPU_ERROR("invalid intf idx:%d\n", phys_enc->intf_idx);
634
-		return;
635
-	}
636
-
637
-	DPU_DEBUG_CMDENC(cmd_enc, "\n");
638
549
 	hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_CMD;
639
550
 }
640
551
 
641
552
 static void dpu_encoder_phys_cmd_prepare_for_kickoff(
642
-		struct dpu_encoder_phys *phys_enc,
643
-		struct dpu_encoder_kickoff_params *params)
553
+		struct dpu_encoder_phys *phys_enc)
644
554
 {
645
555
 	struct dpu_encoder_phys_cmd *cmd_enc =
646
556
 			to_dpu_encoder_phys_cmd(phys_enc);
647
557
 	int ret;
648
558
 
649
-	if (!phys_enc || !phys_enc->hw_pp) {
559
+	if (!phys_enc->hw_pp) {
650
560
 		DPU_ERROR("invalid encoder\n");
651
561
 		return;
652
562
 	}
..
..
@@ -680,11 +590,6 @@
680
590
 	struct dpu_encoder_wait_info wait_info;
681
591
 	int ret;
682
592
 
683
-	if (!phys_enc || !phys_enc->hw_ctl) {
684
-		DPU_ERROR("invalid argument(s)\n");
685
-		return -EINVAL;
686
-	}
687
-
688
593
 	wait_info.wq = &phys_enc->pending_kickoff_wq;
689
594
 	wait_info.atomic_cnt = &phys_enc->pending_ctlstart_cnt;
690
595
 	wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
..
..
@@ -704,12 +609,6 @@
704
609
 		struct dpu_encoder_phys *phys_enc)
705
610
 {
706
611
 	int rc;
707
-	struct dpu_encoder_phys_cmd *cmd_enc;
708
-
709
-	if (!phys_enc)
710
-		return -EINVAL;
711
-
712
-	cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
713
612
 
714
613
 	rc = _dpu_encoder_phys_cmd_wait_for_idle(phys_enc);
715
614
 	if (rc) {
..
..
@@ -727,9 +626,6 @@
727
626
 	int rc = 0;
728
627
 	struct dpu_encoder_phys_cmd *cmd_enc;
729
628
 
730
-	if (!phys_enc)
731
-		return -EINVAL;
732
-
733
629
 	cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
734
630
 
735
631
 	/* only required for master controller */
..
..
@@ -738,7 +634,7 @@
738
634
 
739
635
 	/* required for both controllers */
740
636
 	if (!rc && cmd_enc->serialize_wait4pp)
741
-		dpu_encoder_phys_cmd_prepare_for_kickoff(phys_enc, NULL);
637
+		dpu_encoder_phys_cmd_prepare_for_kickoff(phys_enc);
742
638
 
743
639
 	return rc;
744
640
 }
..
..
@@ -750,9 +646,6 @@
750
646
 	struct dpu_encoder_phys_cmd *cmd_enc;
751
647
 	struct dpu_encoder_wait_info wait_info;
752
648
 
753
-	if (!phys_enc)
754
-		return -EINVAL;
755
-
756
649
 	cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
757
650
 
758
651
 	/* only required for master controller */
..
..
@@ -761,7 +654,7 @@
761
654
 
762
655
 	wait_info.wq = &cmd_enc->pending_vblank_wq;
763
656
 	wait_info.atomic_cnt = &cmd_enc->pending_vblank_cnt;
764
-	wait_info.timeout_ms = _dpu_encoder_phys_cmd_get_idle_timeout(cmd_enc);
657
+	wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
765
658
 
766
659
 	atomic_inc(&cmd_enc->pending_vblank_cnt);
767
660
 
..
..
@@ -774,9 +667,6 @@
774
667
 static void dpu_encoder_phys_cmd_handle_post_kickoff(
775
668
 		struct dpu_encoder_phys *phys_enc)
776
669
 {
777
-	if (!phys_enc)
778
-		return;
779
-
780
670
 	/**
781
671
 	 * re-enable external TE, either for the first time after enabling
782
672
 	 * or if disabled for Autorefresh
..
..
@@ -787,9 +677,6 @@
787
677
 static void dpu_encoder_phys_cmd_trigger_start(
788
678
 		struct dpu_encoder_phys *phys_enc)
789
679
 {
790
-	if (!phys_enc)
791
-		return;
792
-
793
680
 	dpu_encoder_helper_trigger_start(phys_enc);
794
681
 }
795
682
 
..
..
@@ -810,7 +697,6 @@
810
697
 	ops->wait_for_vblank = dpu_encoder_phys_cmd_wait_for_vblank;
811
698
 	ops->trigger_start = dpu_encoder_phys_cmd_trigger_start;
812
699
 	ops->needs_single_flush = dpu_encoder_phys_cmd_needs_single_flush;
813
-	ops->hw_reset = dpu_encoder_helper_hw_reset;
814
700
 	ops->irq_control = dpu_encoder_phys_cmd_irq_control;
815
701
 	ops->restore = dpu_encoder_phys_cmd_enable_helper;
816
702
 	ops->prepare_idle_pc = dpu_encoder_phys_cmd_prepare_idle_pc;
..
..
@@ -823,7 +709,6 @@
823
709
 {
824
710
 	struct dpu_encoder_phys *phys_enc = NULL;
825
711
 	struct dpu_encoder_phys_cmd *cmd_enc = NULL;
826
-	struct dpu_hw_mdp *hw_mdp;
827
712
 	struct dpu_encoder_irq *irq;
828
713
 	int i, ret = 0;
829
714
 
..
..
@@ -833,17 +718,10 @@
833
718
 	if (!cmd_enc) {
834
719
 		ret = -ENOMEM;
835
720
 		DPU_ERROR("failed to allocate\n");
836
-		goto fail;
721
+		return ERR_PTR(ret);
837
722
 	}
838
723
 	phys_enc = &cmd_enc->base;
839
-
840
-	hw_mdp = dpu_rm_get_mdp(&p->dpu_kms->rm);
841
-	if (IS_ERR_OR_NULL(hw_mdp)) {
842
-		ret = PTR_ERR(hw_mdp);
843
-		DPU_ERROR("failed to get mdptop\n");
844
-		goto fail_mdp_init;
845
-	}
846
-	phys_enc->hw_mdptop = hw_mdp;
724
+	phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
847
725
 	phys_enc->intf_idx = p->intf_idx;
848
726
 
849
727
 	dpu_encoder_phys_cmd_init_ops(&phys_enc->ops);
..
..
@@ -897,9 +775,4 @@
897
775
 	DPU_DEBUG_CMDENC(cmd_enc, "created\n");
898
776
 
899
777
 	return phys_enc;
900
-
901
-fail_mdp_init:
902
-	kfree(cmd_enc);
903
-fail:
904
-	return ERR_PTR(ret);
905
778
 }