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hc
2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f 
 kernel/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
....@@ -1,15 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
134  */
145 
156 #ifndef __DPU_ENCODER_PHYS_H__
....@@ -22,8 +13,8 @@
2213 #include "dpu_hw_pingpong.h"
2314 #include "dpu_hw_ctl.h"
2415 #include "dpu_hw_top.h"
25
-#include "dpu_hw_cdm.h"
2616 #include "dpu_encoder.h"
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+#include "dpu_crtc.h"
2718 
2819 #define DPU_ENCODER_NAME_MAX	16
2920 
....@@ -114,10 +105,6 @@
114105  * @handle_post_kickoff:	Do any work necessary post-kickoff work
115106  * @trigger_start:		Process start event on physical encoder
116107  * @needs_single_flush:		Whether encoder slaves need to be flushed
117
- * @setup_misr:		Sets up MISR, enable and disables based on sysfs
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- * @collect_misr:		Collects MISR data on frame update
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- * @hw_reset:			Issue HW recovery such as CTL reset and clear
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- *				DPU_ENC_ERR_NEEDS_HW_RESET state
121108  * @irq_control:		Handler to enable/disable all the encoder IRQs
122109  * @prepare_idle_pc:		phys encoder can update the vsync_enable status
123110  *                              on idle power collapse prepare
....@@ -143,22 +130,15 @@
143130 			    struct drm_connector_state *conn_state);
144131 	void (*destroy)(struct dpu_encoder_phys *encoder);
145132 	void (*get_hw_resources)(struct dpu_encoder_phys *encoder,
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-			struct dpu_encoder_hw_resources *hw_res,
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-			struct drm_connector_state *conn_state);
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+				 struct dpu_encoder_hw_resources *hw_res);
148134 	int (*control_vblank_irq)(struct dpu_encoder_phys *enc, bool enable);
149135 	int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc);
150136 	int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc);
151137 	int (*wait_for_vblank)(struct dpu_encoder_phys *phys_enc);
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-	void (*prepare_for_kickoff)(struct dpu_encoder_phys *phys_enc,
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-			struct dpu_encoder_kickoff_params *params);
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+	void (*prepare_for_kickoff)(struct dpu_encoder_phys *phys_enc);
154139 	void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc);
155140 	void (*trigger_start)(struct dpu_encoder_phys *phys_enc);
156141 	bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc);
157
-
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-	void (*setup_misr)(struct dpu_encoder_phys *phys_encs,
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-				bool enable, u32 frame_count);
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-	u32 (*collect_misr)(struct dpu_encoder_phys *phys_enc);
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-	void (*hw_reset)(struct dpu_encoder_phys *phys_enc);
162142 	void (*irq_control)(struct dpu_encoder_phys *phys, bool enable);
163143 	void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
164144 	void (*restore)(struct dpu_encoder_phys *phys);
....@@ -210,16 +190,14 @@
210190  * @parent_ops:		Callbacks exposed by the parent to the phys_enc
211191  * @hw_mdptop:		Hardware interface to the top registers
212192  * @hw_ctl:		Hardware interface to the ctl registers
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- * @hw_cdm:		Hardware interface to the cdm registers
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- * @cdm_cfg:		Chroma-down hardware configuration
215193  * @hw_pp:		Hardware interface to the ping pong registers
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+ * @hw_intf:		Hardware interface to the intf registers
216195  * @dpu_kms:		Pointer to the dpu_kms top level
217196  * @cached_mode:	DRM mode cached at mode_set time, acted on in enable
218197  * @enabled:		Whether the encoder has enabled and running a mode
219198  * @split_role:		Role to play in a split-panel configuration
220199  * @intf_mode:		Interface mode
221200  * @intf_idx:		Interface index on dpu hardware
222
- * @topology_name:	topology selected for the display
223201  * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
224202  * @enable_state:	Enable state tracking
225203  * @vblank_refcount:	Reference count of vblank request
....@@ -241,15 +219,13 @@
241219 	const struct dpu_encoder_virt_ops *parent_ops;
242220 	struct dpu_hw_mdp *hw_mdptop;
243221 	struct dpu_hw_ctl *hw_ctl;
244
-	struct dpu_hw_cdm *hw_cdm;
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-	struct dpu_hw_cdm_cfg cdm_cfg;
246222 	struct dpu_hw_pingpong *hw_pp;
223
+	struct dpu_hw_intf *hw_intf;
247224 	struct dpu_kms *dpu_kms;
248225 	struct drm_display_mode cached_mode;
249226 	enum dpu_enc_split_role split_role;
250227 	enum dpu_intf_mode intf_mode;
251228 	enum dpu_intf intf_idx;
252
-	enum dpu_rm_topology_name topology_name;
253229 	spinlock_t *enc_spinlock;
254230 	enum dpu_enc_enable_state enable_state;
255231 	atomic_t vblank_refcount;
....@@ -266,19 +242,6 @@
266242 	atomic_inc_return(&phys->pending_ctlstart_cnt);
267243 	return atomic_inc_return(&phys->pending_kickoff_cnt);
268244 }
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-
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-/**
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- * struct dpu_encoder_phys_vid - sub-class of dpu_encoder_phys to handle video
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- *	mode specific operations
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- * @base:	Baseclass physical encoder structure
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- * @hw_intf:	Hardware interface to the intf registers
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- * @timing_params: Current timing parameter
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- */
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-struct dpu_encoder_phys_vid {
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-	struct dpu_encoder_phys base;
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-	struct dpu_hw_intf *hw_intf;
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-	struct intf_timing_params timing_params;
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-};
282245 
283246 /**
284247  * struct dpu_encoder_phys_cmd - sub-class of dpu_encoder_phys to handle command
....@@ -355,23 +318,18 @@
355318  */
356319 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc);
357320 
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-/**
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- * dpu_encoder_helper_hw_reset - issue ctl hw reset
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- *	This helper function may be optionally specified by physical
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- *	encoders if they require ctl hw reset. If state is currently
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- *	DPU_ENC_ERR_NEEDS_HW_RESET, it is set back to DPU_ENC_ENABLED.
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- * @phys_enc: Pointer to physical encoder structure
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- */
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-void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc);
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-
367321 static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
368322 		struct dpu_encoder_phys *phys_enc)
369323 {
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+	struct dpu_crtc_state *dpu_cstate;
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+
370326 	if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
371327 		return BLEND_3D_NONE;
372328 
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+	dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
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+
373331 	if (phys_enc->split_role == ENC_ROLE_SOLO &&
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-	    phys_enc->topology_name == DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE)
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+	    dpu_cstate->num_mixers == CRTC_DUAL_MIXERS)
375333 		return BLEND_3D_H_ROW_INT;
376334 
377335 	return BLEND_3D_NONE;