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| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
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1 | 2 | /* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. |
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2 | | - * |
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3 | | - * This program is free software; you can redistribute it and/or modify |
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4 | | - * it under the terms of the GNU General Public License version 2 and |
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5 | | - * only version 2 as published by the Free Software Foundation. |
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6 | | - * |
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7 | | - * This program is distributed in the hope that it will be useful, |
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8 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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9 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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10 | | - * GNU General Public License for more details. |
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11 | | - * |
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12 | 3 | */ |
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13 | 4 | #ifndef __A5XX_GPU_H__ |
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14 | 5 | #define __A5XX_GPU_H__ |
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.. | .. |
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40 | 31 | struct msm_ringbuffer *next_ring; |
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41 | 32 | |
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42 | 33 | struct drm_gem_object *preempt_bo[MSM_GPU_MAX_RINGS]; |
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| 34 | + struct drm_gem_object *preempt_counters_bo[MSM_GPU_MAX_RINGS]; |
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43 | 35 | struct a5xx_preempt_record *preempt[MSM_GPU_MAX_RINGS]; |
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44 | 36 | uint64_t preempt_iova[MSM_GPU_MAX_RINGS]; |
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45 | 37 | |
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46 | 38 | atomic_t preempt_state; |
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47 | 39 | struct timer_list preempt_timer; |
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| 40 | + |
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| 41 | + struct drm_gem_object *shadow_bo; |
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| 42 | + uint64_t shadow_iova; |
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| 43 | + uint32_t *shadow; |
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| 44 | + |
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| 45 | + /* True if the microcode supports the WHERE_AM_I opcode */ |
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| 46 | + bool has_whereami; |
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48 | 47 | }; |
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49 | 48 | |
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50 | 49 | #define to_a5xx_gpu(x) container_of(x, struct a5xx_gpu, base) |
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51 | 50 | |
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52 | 51 | #ifdef CONFIG_DEBUG_FS |
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53 | | -int a5xx_debugfs_init(struct msm_gpu *gpu, struct drm_minor *minor); |
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| 52 | +void a5xx_debugfs_init(struct msm_gpu *gpu, struct drm_minor *minor); |
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54 | 53 | #endif |
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55 | 54 | |
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56 | 55 | /* |
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.. | .. |
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149 | 148 | return -ETIMEDOUT; |
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150 | 149 | } |
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151 | 150 | |
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| 151 | +#define shadowptr(a5xx_gpu, ring) ((a5xx_gpu)->shadow_iova + \ |
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| 152 | + ((ring)->id * sizeof(uint32_t))) |
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| 153 | + |
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152 | 154 | bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring); |
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153 | 155 | void a5xx_set_hwcg(struct msm_gpu *gpu, bool state); |
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154 | 156 | |
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.. | .. |
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158 | 160 | void a5xx_preempt_irq(struct msm_gpu *gpu); |
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159 | 161 | void a5xx_preempt_fini(struct msm_gpu *gpu); |
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160 | 162 | |
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| 163 | +void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, bool sync); |
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| 164 | + |
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161 | 165 | /* Return true if we are in a preempt state */ |
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162 | 166 | static inline bool a5xx_in_preempt(struct a5xx_gpu *a5xx_gpu) |
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163 | 167 | { |
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