kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
..
..
@@ -1,22 +1,17 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (c) 2015 MediaTek Inc.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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4
  */
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5
 
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-#include <drm/drmP.h>
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+#include <drm/drm_fourcc.h>
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+
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8
 #include <linux/clk.h>
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9
 #include <linux/component.h>
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+#include <linux/module.h>
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11
 #include <linux/of_device.h>
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 #include <linux/of_irq.h>
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 #include <linux/platform_device.h>
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+#include <linux/soc/mediatek/mtk-cmdq.h>
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15
 
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 #include "mtk_drm_crtc.h"
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 #include "mtk_drm_ddp_comp.h"
..
..
@@ -27,6 +22,8 @@
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22
 #define DISP_REG_OVL_EN				0x000c
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 #define DISP_REG_OVL_RST			0x0014
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 #define DISP_REG_OVL_ROI_SIZE			0x0020
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+#define DISP_REG_OVL_DATAPATH_CON		0x0024
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+#define OVL_BGCLR_SEL_IN				BIT(2)
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 #define DISP_REG_OVL_ROI_BGCLR			0x0028
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 #define DISP_REG_OVL_SRC_CON			0x002c
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 #define DISP_REG_OVL_CON(n)			(0x0030 + 0x20 * (n))
..
..
@@ -39,7 +36,9 @@
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 #define DISP_REG_OVL_ADDR_MT8173		0x0f40
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 #define DISP_REG_OVL_ADDR(ovl, n)		((ovl)->data->addr + 0x20 * (n))
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38
 
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-#define	OVL_RDMA_MEM_GMC	0x40402020
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+#define GMC_THRESHOLD_BITS	16
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+#define GMC_THRESHOLD_HIGH	((1 << GMC_THRESHOLD_BITS) / 4)
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+#define GMC_THRESHOLD_LOW	((1 << GMC_THRESHOLD_BITS) / 8)
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42
 
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 #define OVL_CON_BYTE_SWAP	BIT(24)
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 #define OVL_CON_MTX_YUV_TO_RGB	(6 << 16)
..
..
@@ -54,9 +53,13 @@
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 					OVL_CON_CLRFMT_RGB : 0)
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 #define	OVL_CON_AEN		BIT(8)
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 #define	OVL_CON_ALPHA		0xff
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+#define	OVL_CON_VIRT_FLIP	BIT(9)
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+#define	OVL_CON_HORZ_FLIP	BIT(10)
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58
 
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 struct mtk_disp_ovl_data {
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 	unsigned int addr;
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+	unsigned int gmc_bits;
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+	unsigned int layer_nr;
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 	bool fmt_rgb565_is_0;
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 };
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65
 
..
..
@@ -122,42 +125,90 @@
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125
 
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 static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w,
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 			   unsigned int h, unsigned int vrefresh,
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-			   unsigned int bpc)
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+			   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
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 {
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 	if (w != 0 && h != 0)
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-		writel_relaxed(h << 16 | w, comp->regs + DISP_REG_OVL_ROI_SIZE);
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-	writel_relaxed(0x0, comp->regs + DISP_REG_OVL_ROI_BGCLR);
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+		mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, comp,
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+				      DISP_REG_OVL_ROI_SIZE);
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+	mtk_ddp_write_relaxed(cmdq_pkt, 0x0, comp, DISP_REG_OVL_ROI_BGCLR);
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-	writel(0x1, comp->regs + DISP_REG_OVL_RST);
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-	writel(0x0, comp->regs + DISP_REG_OVL_RST);
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+	mtk_ddp_write(cmdq_pkt, 0x1, comp, DISP_REG_OVL_RST);
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+	mtk_ddp_write(cmdq_pkt, 0x0, comp, DISP_REG_OVL_RST);
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 }
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 static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp)
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 {
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-	return 4;
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+	struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
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+
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+	return ovl->data->layer_nr;
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 }
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145
 
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-static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx)
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+static unsigned int mtk_ovl_supported_rotations(struct mtk_ddp_comp *comp)
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 {
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-	unsigned int reg;
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-
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-	writel(0x1, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
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-	writel(OVL_RDMA_MEM_GMC, comp->regs + DISP_REG_OVL_RDMA_GMC(idx));
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-
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-	reg = readl(comp->regs + DISP_REG_OVL_SRC_CON);
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-	reg = reg | BIT(idx);
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-	writel(reg, comp->regs + DISP_REG_OVL_SRC_CON);
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+	return DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
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+	       DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
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 }
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151
 
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-static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx)
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+static int mtk_ovl_layer_check(struct mtk_ddp_comp *comp, unsigned int idx,
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+			       struct mtk_plane_state *mtk_state)
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 {
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-	unsigned int reg;
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+	struct drm_plane_state *state = &mtk_state->base;
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+	unsigned int rotation = 0;
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-	reg = readl(comp->regs + DISP_REG_OVL_SRC_CON);
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-	reg = reg & ~BIT(idx);
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-	writel(reg, comp->regs + DISP_REG_OVL_SRC_CON);
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+	rotation = drm_rotation_simplify(state->rotation,
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+					 DRM_MODE_ROTATE_0 |
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+					 DRM_MODE_REFLECT_X |
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+					 DRM_MODE_REFLECT_Y);
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+	rotation &= ~DRM_MODE_ROTATE_0;
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163
 
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-	writel(0x0, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
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+	/* We can only do reflection, not rotation */
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+	if ((rotation & DRM_MODE_ROTATE_MASK) != 0)
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+		return -EINVAL;
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+
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+	/*
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+	 * TODO: Rotating/reflecting YUV buffers is not supported at this time.
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+	 *	 Only RGB[AX] variants are supported.
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+	 */
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+	if (state->fb->format->is_yuv && rotation != 0)
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+		return -EINVAL;
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+
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+	state->rotation = rotation;
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+
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+	return 0;
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+}
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+
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+static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx,
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+			     struct cmdq_pkt *cmdq_pkt)
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+{
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+	unsigned int gmc_thrshd_l;
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+	unsigned int gmc_thrshd_h;
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+	unsigned int gmc_value;
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+	struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
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+
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+	mtk_ddp_write(cmdq_pkt, 0x1, comp,
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+		      DISP_REG_OVL_RDMA_CTRL(idx));
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+	gmc_thrshd_l = GMC_THRESHOLD_LOW >>
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+		      (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
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+	gmc_thrshd_h = GMC_THRESHOLD_HIGH >>
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+		      (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
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+	if (ovl->data->gmc_bits == 10)
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+		gmc_value = gmc_thrshd_h | gmc_thrshd_h << 16;
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+	else
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+		gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 |
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+			    gmc_thrshd_h << 16 | gmc_thrshd_h << 24;
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+	mtk_ddp_write(cmdq_pkt, gmc_value,
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+		      comp, DISP_REG_OVL_RDMA_GMC(idx));
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+	mtk_ddp_write_mask(cmdq_pkt, BIT(idx), comp,
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+			   DISP_REG_OVL_SRC_CON, BIT(idx));
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+}
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+
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+static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx,
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+			      struct cmdq_pkt *cmdq_pkt)
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+{
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+	mtk_ddp_write_mask(cmdq_pkt, 0, comp,
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+			   DISP_REG_OVL_SRC_CON, BIT(idx));
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+	mtk_ddp_write(cmdq_pkt, 0, comp,
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+		      DISP_REG_OVL_RDMA_CTRL(idx));
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 }
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213
 
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 static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
..
..
@@ -197,7 +248,8 @@
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 }
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 static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
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-				 struct mtk_plane_state *state)
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+				 struct mtk_plane_state *state,
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+				 struct cmdq_pkt *cmdq_pkt)
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 {
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 	struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
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 	struct mtk_plane_pending_state *pending = &state->pending;
..
..
@@ -208,21 +260,55 @@
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 	unsigned int src_size = (pending->height << 16) | pending->width;
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 	unsigned int con;
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262
 
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-	if (!pending->enable)
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-		mtk_ovl_layer_off(comp, idx);
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+	if (!pending->enable) {
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+		mtk_ovl_layer_off(comp, idx, cmdq_pkt);
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+		return;
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+	}
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 	con = ovl_fmt_convert(ovl, fmt);
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-	if (idx != 0)
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+	if (state->base.fb && state->base.fb->format->has_alpha)
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 		con |= OVL_CON_AEN | OVL_CON_ALPHA;
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-	writel_relaxed(con, comp->regs + DISP_REG_OVL_CON(idx));
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-	writel_relaxed(pitch, comp->regs + DISP_REG_OVL_PITCH(idx));
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-	writel_relaxed(src_size, comp->regs + DISP_REG_OVL_SRC_SIZE(idx));
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-	writel_relaxed(offset, comp->regs + DISP_REG_OVL_OFFSET(idx));
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-	writel_relaxed(addr, comp->regs + DISP_REG_OVL_ADDR(ovl, idx));
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+	if (pending->rotation & DRM_MODE_REFLECT_Y) {
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+		con |= OVL_CON_VIRT_FLIP;
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+		addr += (pending->height - 1) * pending->pitch;
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+	}
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-	if (pending->enable)
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-		mtk_ovl_layer_on(comp, idx);
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+	if (pending->rotation & DRM_MODE_REFLECT_X) {
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+		con |= OVL_CON_HORZ_FLIP;
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+		addr += pending->pitch - 1;
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+	}
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+
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+	mtk_ddp_write_relaxed(cmdq_pkt, con, comp,
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+			      DISP_REG_OVL_CON(idx));
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+	mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp,
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+			      DISP_REG_OVL_PITCH(idx));
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+	mtk_ddp_write_relaxed(cmdq_pkt, src_size, comp,
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+			      DISP_REG_OVL_SRC_SIZE(idx));
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+	mtk_ddp_write_relaxed(cmdq_pkt, offset, comp,
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+			      DISP_REG_OVL_OFFSET(idx));
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+	mtk_ddp_write_relaxed(cmdq_pkt, addr, comp,
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+			      DISP_REG_OVL_ADDR(ovl, idx));
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+
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+	mtk_ovl_layer_on(comp, idx, cmdq_pkt);
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+}
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+
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+static void mtk_ovl_bgclr_in_on(struct mtk_ddp_comp *comp)
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+{
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+	unsigned int reg;
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+
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+	reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
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+	reg = reg | OVL_BGCLR_SEL_IN;
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+	writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
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+}
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+
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+static void mtk_ovl_bgclr_in_off(struct mtk_ddp_comp *comp)
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+{
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+	unsigned int reg;
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+
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+	reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
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+	reg = reg & ~OVL_BGCLR_SEL_IN;
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+	writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
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 }
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313
 
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 static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = {
..
..
@@ -231,10 +317,12 @@
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 	.stop = mtk_ovl_stop,
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 	.enable_vblank = mtk_ovl_enable_vblank,
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 	.disable_vblank = mtk_ovl_disable_vblank,
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+	.supported_rotations = mtk_ovl_supported_rotations,
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 	.layer_nr = mtk_ovl_layer_nr,
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-	.layer_on = mtk_ovl_layer_on,
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-	.layer_off = mtk_ovl_layer_off,
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+	.layer_check = mtk_ovl_layer_check,
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 	.layer_config = mtk_ovl_layer_config,
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+	.bgclr_in_on = mtk_ovl_bgclr_in_on,
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+	.bgclr_in_off = mtk_ovl_bgclr_in_off,
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 };
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 static int mtk_disp_ovl_bind(struct device *dev, struct device *master,
..
..
@@ -284,7 +372,12 @@
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 	if (irq < 0)
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 		return irq;
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374
 
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-	comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_OVL);
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+	priv->data = of_device_get_match_data(dev);
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+
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+	comp_id = mtk_ddp_comp_get_id(dev->of_node,
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+				      priv->data->layer_nr == 4 ?
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+				      MTK_DISP_OVL :
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+				      MTK_DISP_OVL_2L);
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 	if (comp_id < 0) {
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 		dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
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 		return comp_id;
..
..
@@ -293,11 +386,12 @@
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 	ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
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 				&mtk_disp_ovl_funcs);
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388
 	if (ret) {
296
-		dev_err(dev, "Failed to initialize component: %d\n", ret);
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+		if (ret != -EPROBE_DEFER)
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+			dev_err(dev, "Failed to initialize component: %d\n",
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+				ret);
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+
297
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 		return ret;
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 	}
299
-
300
-	priv->data = of_device_get_match_data(dev);
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395
 
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 	platform_set_drvdata(pdev, priv);
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397
 
..
..
@@ -324,11 +418,15 @@
324
418
 
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419
 static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = {
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 	.addr = DISP_REG_OVL_ADDR_MT2701,
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+	.gmc_bits = 8,
422
+	.layer_nr = 4,
327
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 	.fmt_rgb565_is_0 = false,
328
424
 };
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425
 
330
426
 static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
331
427
 	.addr = DISP_REG_OVL_ADDR_MT8173,
428
+	.gmc_bits = 8,
429
+	.layer_nr = 4,
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 	.fmt_rgb565_is_0 = true,
333
431
 };
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