kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/drivers/gpu/drm/i915/gvt/mmio.c
..
..
@@ -39,6 +39,7 @@
39
39
 /**
40
40
  * intel_vgpu_gpa_to_mmio_offset - translate a GPA to MMIO offset
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41
  * @vgpu: a vGPU
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+ * @gpa: guest physical address
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43
  *
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44
  * Returns:
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45
  * Zero on success, negative error code if failed
..
..
@@ -56,7 +57,7 @@
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57
 	(reg >= gvt->device_info.gtt_start_offset \
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58
 	 && reg < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt))
58
59
 
59
-static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, uint64_t pa,
60
+static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, u64 pa,
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61
 		void *p_data, unsigned int bytes, bool read)
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62
 {
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63
 	struct intel_gvt *gvt = NULL;
..
..
@@ -98,10 +99,11 @@
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  * Returns:
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100
  * Zero on success, negative error code if failed
100
101
  */
101
-int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa,
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+int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
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103
 		void *p_data, unsigned int bytes)
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104
 {
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 	struct intel_gvt *gvt = vgpu->gvt;
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+	struct drm_i915_private *i915 = gvt->gt->i915;
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107
 	unsigned int offset = 0;
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108
 	int ret = -EINVAL;
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109
 
..
..
@@ -113,15 +115,17 @@
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115
 
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 	offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
115
117
 
116
-	if (WARN_ON(bytes > 8))
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+	if (drm_WARN_ON(&i915->drm, bytes > 8))
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119
 		goto err;
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120
 
119
121
 	if (reg_is_gtt(gvt, offset)) {
120
-		if (WARN_ON(!IS_ALIGNED(offset, 4) && !IS_ALIGNED(offset, 8)))
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+		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4) &&
123
+				!IS_ALIGNED(offset, 8)))
121
124
 			goto err;
122
-		if (WARN_ON(bytes != 4 && bytes != 8))
125
+		if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8))
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126
 			goto err;
124
-		if (WARN_ON(!reg_is_gtt(gvt, offset + bytes - 1)))
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+		if (drm_WARN_ON(&i915->drm,
128
+				!reg_is_gtt(gvt, offset + bytes - 1)))
125
129
 			goto err;
126
130
 
127
131
 		ret = intel_vgpu_emulate_ggtt_mmio_read(vgpu, offset,
..
..
@@ -131,16 +135,16 @@
131
135
 		goto out;
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136
 	}
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137
 
134
-	if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) {
138
+	if (drm_WARN_ON_ONCE(&i915->drm, !reg_is_mmio(gvt, offset))) {
135
139
 		ret = intel_gvt_hypervisor_read_gpa(vgpu, pa, p_data, bytes);
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140
 		goto out;
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 	}
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142
 
139
-	if (WARN_ON(!reg_is_mmio(gvt, offset + bytes - 1)))
143
+	if (drm_WARN_ON(&i915->drm, !reg_is_mmio(gvt, offset + bytes - 1)))
140
144
 		goto err;
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145
 
142
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 	if (!intel_gvt_mmio_is_unalign(gvt, offset)) {
143
-		if (WARN_ON(!IS_ALIGNED(offset, bytes)))
147
+		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, bytes)))
144
148
 			goto err;
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149
 	}
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150
 
..
..
@@ -170,10 +174,11 @@
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  * Returns:
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175
  * Zero on success, negative error code if failed
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176
  */
173
-int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa,
177
+int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
174
178
 		void *p_data, unsigned int bytes)
175
179
 {
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 	struct intel_gvt *gvt = vgpu->gvt;
181
+	struct drm_i915_private *i915 = gvt->gt->i915;
177
182
 	unsigned int offset = 0;
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183
 	int ret = -EINVAL;
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184
 
..
..
@@ -186,15 +191,17 @@
186
191
 
187
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 	offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
188
193
 
189
-	if (WARN_ON(bytes > 8))
194
+	if (drm_WARN_ON(&i915->drm, bytes > 8))
190
195
 		goto err;
191
196
 
192
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 	if (reg_is_gtt(gvt, offset)) {
193
-		if (WARN_ON(!IS_ALIGNED(offset, 4) && !IS_ALIGNED(offset, 8)))
198
+		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4) &&
199
+				!IS_ALIGNED(offset, 8)))
194
200
 			goto err;
195
-		if (WARN_ON(bytes != 4 && bytes != 8))
201
+		if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8))
196
202
 			goto err;
197
-		if (WARN_ON(!reg_is_gtt(gvt, offset + bytes - 1)))
203
+		if (drm_WARN_ON(&i915->drm,
204
+				!reg_is_gtt(gvt, offset + bytes - 1)))
198
205
 			goto err;
199
206
 
200
207
 		ret = intel_vgpu_emulate_ggtt_mmio_write(vgpu, offset,
..
..
@@ -204,7 +211,7 @@
204
211
 		goto out;
205
212
 	}
206
213
 
207
-	if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) {
214
+	if (drm_WARN_ON_ONCE(&i915->drm, !reg_is_mmio(gvt, offset))) {
208
215
 		ret = intel_gvt_hypervisor_write_gpa(vgpu, pa, p_data, bytes);
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216
 		goto out;
210
217
 	}
..
..
@@ -228,7 +235,7 @@
228
235
 /**
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236
  * intel_vgpu_reset_mmio - reset virtual MMIO space
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237
  * @vgpu: a vGPU
231
- *
238
+ * @dmlr: whether this is device model level reset
232
239
  */
233
240
 void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
234
241
 {
..
..
@@ -238,14 +245,16 @@
238
245
 
239
246
 	if (dmlr) {
240
247
 		memcpy(vgpu->mmio.vreg, mmio, info->mmio_size);
241
-		memcpy(vgpu->mmio.sreg, mmio, info->mmio_size);
242
248
 
243
249
 		vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0;
244
250
 
245
251
 		/* set the bit 0:2(Core C-State ) to C0 */
246
252
 		vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0;
247
253
 
248
-		if (IS_BROXTON(vgpu->gvt->dev_priv)) {
254
+		/* uc reset hw expect GS_MIA_IN_RESET */
255
+		vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;
256
+
257
+		if (IS_BROXTON(vgpu->gvt->gt->i915)) {
249
258
 			vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &=
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259
 				    ~(BIT(0) | BIT(1));
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260
 			vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
..
..
@@ -271,6 +280,11 @@
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280
 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
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281
 				    BXT_PHY_CMNLANE_POWERDOWN_ACK |
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282
 				    BXT_PHY_LANE_POWERDOWN_ACK;
283
+			vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
284
+				SKL_FUSE_DOWNLOAD_STATUS |
285
+				SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |
286
+				SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |
287
+				SKL_FUSE_PG_DIST_STATUS(SKL_PG2);
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288
 		}
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289
 	} else {
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290
 #define GVT_GEN8_MMIO_RESET_OFFSET		(0x44200)
..
..
@@ -279,7 +293,6 @@
279
293
 		 * touched
280
294
 		 */
281
295
 		memcpy(vgpu->mmio.vreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
282
-		memcpy(vgpu->mmio.sreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
283
296
 	}
284
297
 
285
298
 }
..
..
@@ -295,11 +308,9 @@
295
308
 {
296
309
 	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
297
310
 
298
-	vgpu->mmio.vreg = vzalloc(array_size(info->mmio_size, 2));
311
+	vgpu->mmio.vreg = vzalloc(info->mmio_size);
299
312
 	if (!vgpu->mmio.vreg)
300
313
 		return -ENOMEM;
301
-
302
-	vgpu->mmio.sreg = vgpu->mmio.vreg + info->mmio_size;
303
314
 
304
315
 	intel_vgpu_reset_mmio(vgpu, true);
305
316
 
..
..
@@ -314,5 +325,5 @@
314
325
 void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu)
315
326
 {
316
327
 	vfree(vgpu->mmio.vreg);
317
-	vgpu->mmio.vreg = vgpu->mmio.sreg = NULL;
328
+	vgpu->mmio.vreg = NULL;
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329
 }