kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/drivers/gpu/drm/i915/gvt/interrupt.c
..
..
@@ -126,7 +126,7 @@
126
126
 	[FDI_RX_INTERRUPTS_TRANSCODER_C] = "FDI RX Interrupts Combined C",
127
127
 	[AUDIO_CP_CHANGE_TRANSCODER_C] = "Audio CP Change Transcoder C",
128
128
 	[AUDIO_CP_REQUEST_TRANSCODER_C] = "Audio CP Request Transcoder C",
129
-	[ERR_AND_DBG] = "South Error and Debug Interupts Combined",
129
+	[ERR_AND_DBG] = "South Error and Debug Interrupts Combined",
130
130
 	[GMBUS] = "Gmbus",
131
131
 	[SDVO_B_HOTPLUG] = "SDVO B hotplug",
132
132
 	[CRT_HOTPLUG] = "CRT Hotplug",
..
..
@@ -245,6 +245,7 @@
245
245
 	unsigned int reg, void *p_data, unsigned int bytes)
246
246
 {
247
247
 	struct intel_gvt *gvt = vgpu->gvt;
248
+	struct drm_i915_private *i915 = gvt->gt->i915;
248
249
 	struct intel_gvt_irq_ops *ops = gvt->irq.ops;
249
250
 	struct intel_gvt_irq_info *info;
250
251
 	u32 ier = *(u32 *)p_data;
..
..
@@ -255,7 +256,7 @@
255
256
 	vgpu_vreg(vgpu, reg) = ier;
256
257
 
257
258
 	info = regbase_to_irq_info(gvt, ier_to_regbase(reg));
258
-	if (WARN_ON(!info))
259
+	if (drm_WARN_ON(&i915->drm, !info))
259
260
 		return -EINVAL;
260
261
 
261
262
 	if (info->has_upstream_irq)
..
..
@@ -282,6 +283,7 @@
282
283
 int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
283
284
 	void *p_data, unsigned int bytes)
284
285
 {
286
+	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
285
287
 	struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt,
286
288
 		iir_to_regbase(reg));
287
289
 	u32 iir = *(u32 *)p_data;
..
..
@@ -289,7 +291,7 @@
289
291
 	trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),
290
292
 		       (vgpu_vreg(vgpu, reg) ^ iir));
291
293
 
292
-	if (WARN_ON(!info))
294
+	if (drm_WARN_ON(&i915->drm, !info))
293
295
 		return -EINVAL;
294
296
 
295
297
 	vgpu_vreg(vgpu, reg) &= ~iir;
..
..
@@ -319,6 +321,7 @@
319
321
 static void update_upstream_irq(struct intel_vgpu *vgpu,
320
322
 		struct intel_gvt_irq_info *info)
321
323
 {
324
+	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
322
325
 	struct intel_gvt_irq *irq = &vgpu->gvt->irq;
323
326
 	struct intel_gvt_irq_map *map = irq->irq_map;
324
327
 	struct intel_gvt_irq_info *up_irq_info = NULL;
..
..
@@ -340,7 +343,8 @@
340
343
 		if (!up_irq_info)
341
344
 			up_irq_info = irq->info[map->up_irq_group];
342
345
 		else
343
-			WARN_ON(up_irq_info != irq->info[map->up_irq_group]);
346
+			drm_WARN_ON(&i915->drm, up_irq_info !=
347
+				    irq->info[map->up_irq_group]);
344
348
 
345
349
 		bit = map->up_irq_bit;
346
350
 
..
..
@@ -350,7 +354,7 @@
350
354
 			clear_bits |= (1 << bit);
351
355
 	}
352
356
 
353
-	if (WARN_ON(!up_irq_info))
357
+	if (drm_WARN_ON(&i915->drm, !up_irq_info))
354
358
 		return;
355
359
 
356
360
 	if (up_irq_info->group == INTEL_GVT_IRQ_INFO_MASTER) {
..
..
@@ -536,7 +540,7 @@
536
540
 	SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1);
537
541
 	SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1);
538
542
 
539
-	if (HAS_BSD2(gvt->dev_priv)) {
543
+	if (HAS_ENGINE(gvt->gt, VCS1)) {
540
544
 		SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT,
541
545
 			INTEL_GVT_IRQ_INFO_GT1);
542
546
 		SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW,
..
..
@@ -568,7 +572,7 @@
568
572
 	SET_BIT_INFO(irq, 22, DP_C_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
569
573
 	SET_BIT_INFO(irq, 23, DP_D_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
570
574
 
571
-	if (IS_BROADWELL(gvt->dev_priv)) {
575
+	if (IS_BROADWELL(gvt->gt->i915)) {
572
576
 		SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_PCH);
573
577
 		SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_PCH);
574
578
 		SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_PCH);
..
..
@@ -581,9 +585,7 @@
581
585
 
582
586
 		SET_BIT_INFO(irq, 4, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
583
587
 		SET_BIT_INFO(irq, 5, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
584
-	} else if (IS_SKYLAKE(gvt->dev_priv)
585
-			|| IS_KABYLAKE(gvt->dev_priv)
586
-			|| IS_BROXTON(gvt->dev_priv)) {
588
+	} else if (INTEL_GEN(gvt->gt->i915) >= 9) {
587
589
 		SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_DE_PORT);
588
590
 		SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_DE_PORT);
589
591
 		SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_DE_PORT);
..
..
@@ -620,13 +622,14 @@
620
622
 void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu,
621
623
 	enum intel_gvt_event_type event)
622
624
 {
625
+	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
623
626
 	struct intel_gvt *gvt = vgpu->gvt;
624
627
 	struct intel_gvt_irq *irq = &gvt->irq;
625
628
 	gvt_event_virt_handler_t handler;
626
629
 	struct intel_gvt_irq_ops *ops = gvt->irq.ops;
627
630
 
628
631
 	handler = get_event_virt_handler(irq, event);
629
-	WARN_ON(!handler);
632
+	drm_WARN_ON(&i915->drm, !handler);
630
633
 
631
634
 	handler(irq, event, vgpu);
632
635
 
..
..
@@ -674,7 +677,7 @@
674
677
 	hrtimer_cancel(&irq->vblank_timer.timer);
675
678
 }
676
679
 
677
-#define VBLNAK_TIMER_PERIOD 16000000
680
+#define VBLANK_TIMER_PERIOD 16000000
678
681
 
679
682
 /**
680
683
  * intel_gvt_init_irq - initialize GVT-g IRQ emulation subsystem
..
..
@@ -706,7 +709,7 @@
706
709
 
707
710
 	hrtimer_init(&vblank_timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
708
711
 	vblank_timer->timer.function = vblank_timer_fn;
709
-	vblank_timer->period = VBLNAK_TIMER_PERIOD;
712
+	vblank_timer->period = VBLANK_TIMER_PERIOD;
710
713
 
711
714
 	return 0;
712
715
 }