kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/drivers/gpu/drm/i915/gvt/cfg_space.c
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@@ -56,6 +56,10 @@
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 /**
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  * vgpu_pci_cfg_mem_write - write virtual cfg space memory
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+ * @vgpu: target vgpu
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+ * @off: offset
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+ * @src: src ptr to write
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+ * @bytes: number of bytes
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  *
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  * Use this function to write virtual cfg space memory.
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  * For standard cfg space, only RW bits can be changed,
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@@ -66,6 +70,7 @@
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 {
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 	u8 *cfg_base = vgpu_cfg_space(vgpu);
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 	u8 mask, new, old;
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+	pci_power_t pwr;
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 	int i = 0;
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 	for (; i < bytes && (off + i < sizeof(pci_cfg_space_rw_bmp)); i++) {
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@@ -87,10 +92,23 @@
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 	/* For other configuration space directly copy as it is. */
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 	if (i < bytes)
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 		memcpy(cfg_base + off + i, src + i, bytes - i);
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+
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+	if (off == vgpu->cfg_space.pmcsr_off && vgpu->cfg_space.pmcsr_off) {
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+		pwr = (pci_power_t __force)(*(u16*)(&vgpu_cfg_space(vgpu)[off])
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+			& PCI_PM_CTRL_STATE_MASK);
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+		if (pwr == PCI_D3hot)
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+			vgpu->d3_entered = true;
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+		gvt_dbg_core("vgpu-%d power status changed to %d\n",
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+			     vgpu->id, pwr);
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+	}
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 }
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 /**
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  * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space read
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+ * @vgpu: target vgpu
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+ * @offset: offset
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+ * @p_data: return data ptr
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+ * @bytes: number of bytes to read
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  *
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  * Returns:
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  * Zero on success, negative error code if failed.
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@@ -98,10 +116,13 @@
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 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,
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 	void *p_data, unsigned int bytes)
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 {
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-	if (WARN_ON(bytes > 4))
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+	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
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+
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+	if (drm_WARN_ON(&i915->drm, bytes > 4))
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 		return -EINVAL;
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-	if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size))
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+	if (drm_WARN_ON(&i915->drm,
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+			offset + bytes > vgpu->gvt->device_info.cfg_space_size))
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 		return -EINVAL;
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 	memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes);
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@@ -278,6 +299,10 @@
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 /**
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  * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space write
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+ * @vgpu: target vgpu
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+ * @offset: offset
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+ * @p_data: write data ptr
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+ * @bytes: number of bytes to write
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  *
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  * Returns:
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  * Zero on success, negative error code if failed.
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@@ -285,34 +310,36 @@
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 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
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 	void *p_data, unsigned int bytes)
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 {
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+	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
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 	int ret;
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-	if (WARN_ON(bytes > 4))
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+	if (drm_WARN_ON(&i915->drm, bytes > 4))
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 		return -EINVAL;
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-	if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size))
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+	if (drm_WARN_ON(&i915->drm,
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+			offset + bytes > vgpu->gvt->device_info.cfg_space_size))
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 		return -EINVAL;
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 	/* First check if it's PCI_COMMAND */
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 	if (IS_ALIGNED(offset, 2) && offset == PCI_COMMAND) {
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-		if (WARN_ON(bytes > 2))
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+		if (drm_WARN_ON(&i915->drm, bytes > 2))
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 			return -EINVAL;
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 		return emulate_pci_command_write(vgpu, offset, p_data, bytes);
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 	}
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 	switch (rounddown(offset, 4)) {
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 	case PCI_ROM_ADDRESS:
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-		if (WARN_ON(!IS_ALIGNED(offset, 4)))
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+		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))
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 			return -EINVAL;
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 		return emulate_pci_rom_bar_write(vgpu, offset, p_data, bytes);
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 	case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5:
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-		if (WARN_ON(!IS_ALIGNED(offset, 4)))
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+		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))
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 			return -EINVAL;
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 		return emulate_pci_bar_write(vgpu, offset, p_data, bytes);
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 	case INTEL_GVT_PCI_SWSCI:
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-		if (WARN_ON(!IS_ALIGNED(offset, 4)))
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+		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))
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 			return -EINVAL;
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 		ret = intel_vgpu_emulate_opregion_request(vgpu, *(u32 *)p_data);
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 		if (ret)
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@@ -320,7 +347,7 @@
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 		break;
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 	case INTEL_GVT_PCI_OPREGION:
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-		if (WARN_ON(!IS_ALIGNED(offset, 4)))
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+		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))
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 			return -EINVAL;
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 		ret = intel_vgpu_opregion_base_write_handler(vgpu,
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 						   *(u32 *)p_data);
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@@ -349,6 +376,7 @@
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 	struct intel_gvt *gvt = vgpu->gvt;
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 	const struct intel_gvt_device_info *info = &gvt->device_info;
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 	u16 *gmch_ctl;
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+	u8 next;
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 	memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space,
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 	       info->cfg_space_size);
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@@ -379,11 +407,24 @@
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 	memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4);
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 	vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size =
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-				pci_resource_len(gvt->dev_priv->drm.pdev, 0);
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+		pci_resource_len(gvt->gt->i915->drm.pdev, 0);
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 	vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size =
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-				pci_resource_len(gvt->dev_priv->drm.pdev, 2);
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+		pci_resource_len(gvt->gt->i915->drm.pdev, 2);
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 	memset(vgpu_cfg_space(vgpu) + PCI_ROM_ADDRESS, 0, 4);
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+
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+	/* PM Support */
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+	vgpu->cfg_space.pmcsr_off = 0;
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+	if (vgpu_cfg_space(vgpu)[PCI_STATUS] & PCI_STATUS_CAP_LIST) {
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+		next = vgpu_cfg_space(vgpu)[PCI_CAPABILITY_LIST];
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+		do {
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+			if (vgpu_cfg_space(vgpu)[next + PCI_CAP_LIST_ID] == PCI_CAP_ID_PM) {
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+				vgpu->cfg_space.pmcsr_off = next + PCI_PM_CTRL;
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+				break;
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+			}
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+			next = vgpu_cfg_space(vgpu)[next + PCI_CAP_LIST_NEXT];
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+		} while (next);
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+	}
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 }
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 /**