kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h
..
..
@@ -13,6 +13,7 @@
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 #define CONFIG_REG					0xc
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 #define CONFIG_CEC					BIT(28)
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 #define CONFIG_AUD_UD					BIT(23)
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+#define CONFIG_HDCP14					BIT(8)
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 #define CORE_TIMESTAMP_HHMM				0x14
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 #define CORE_TIMESTAMP_MMDD				0x18
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 #define CORE_TIMESTAMP_YYYY				0x1c
..
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@@ -139,7 +140,7 @@
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 #define FRAME_COMPOSER_CONFIG8				0x860
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 #define FRAME_COMPOSER_CONFIG9				0x864
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 #define KEEPOUT_REKEY_CFG				GENMASK(9, 8)
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-#define KEEPOUT_REKEY_ALWAYS				0x2
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+#define KEEPOUT_REKEY_ALWAYS				(0x2 << 8)
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 #define FRAME_COMPOSER_CONTROL0				0x86c
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 /* Video Monitor Registers */
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 #define VIDEO_MONITOR_CONFIG0				0x880
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@@ -155,9 +156,13 @@
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 #define HDCP2_BYPASS					BIT(0)
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 #define HDCP2LOGIC_ESM_GPIO_IN				0x8e4
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 #define HDCP2LOGIC_ESM_GPIO_OUT				0x8e8
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+#define HDCP2_AUTHENTICATION_SUCCESS			BIT(6)
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 /* HDCP14 Registers */
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 #define HDCP14_CONFIG0					0x900
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+#define HDCP14_OESS_ESSS_OVR_VALUE                      BIT(14)
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+#define HDCP14_OESS_ESSS_OVR_EN                         BIT(13)
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 #define HDCP14_CONFIG1					0x904
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+#define HDCP14_SHA1_MSG_CORRECT_P                       BIT(3)
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 #define HDCP14_CONFIG2					0x908
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 #define HDCP14_CONFIG3					0x90c
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 #define HDCP14_KEY_SEED					0x914
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@@ -169,7 +174,10 @@
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 #define HDCP14_AN_H					0x92c
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 #define HDCP14_AN_L					0x930
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 #define HDCP14_STATUS0					0x934
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+#define HDCP14_RPT_DEVICE_COUNT                         0xFE00
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 #define HDCP14_STATUS1					0x938
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+#define HDCP14_RCV_REPEATER                             BIT(6)
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+#define HDCP14_RCV_KSV_FIFO_READY                       BIT(5)
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 /* Scrambler Registers */
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 #define SCRAMB_CONFIG0					0x960
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 /* Video Configuration Registers */
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@@ -792,6 +800,7 @@
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 #define AVP_1_INT_STATUS				0x3820
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 #define AVP_1_INT_MASK_N				0x3824
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 #define HDCP14_AUTH_CHG_MASK_N				BIT(6)
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+#define HDCP14_KSV_LIST_DONE_MASK_N		        BIT(1)
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 #define AVP_1_INT_CLEAR					0x3828
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 #define AVP_1_INT_FORCE					0x382c
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 #define AVP_2_INT_STATUS				0x3830
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@@ -802,6 +811,7 @@
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 #define AVP_3_INT_MASK_N				0x3844
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 #define AVP_3_INT_CLEAR					0x3848
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 #define AVP_3_INT_FORCE					0x384c
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+#define HDCP2_ESM_P0_GPIO_OUT_2_CHG_IRQ			BIT(17)
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 #define AVP_4_INT_STATUS				0x3850
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 #define AVP_4_INT_MASK_N				0x3854
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 #define AVP_4_INT_CLEAR					0x3858
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@@ -832,4 +842,9 @@
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 #define EARCRX_1_INT_CLEAR				0x4828
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 #define EARCRX_1_INT_FORCE				0x482c
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+#define HDMI_HDCP14_MEM_KSV0				0x4f08
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+#define HDMI_HDCP14_MEM_BSTATUS0			0x5958
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+#define HDMI_HDCP14_MEM_M0_1				0x5960
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+#define HDMI_HDCP14_MEM_M0_7				0x597c
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+
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 #endif /* __DW_HDMI_QP_H__ */