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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | 3 | * Xilinx gpio driver for xps/axi_gpio IP. |
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3 | 4 | * |
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4 | 5 | * Copyright 2008 - 2013 Xilinx, Inc. |
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5 | | - * |
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6 | | - * This program is free software; you can redistribute it and/or modify |
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7 | | - * it under the terms of the GNU General Public License version 2 |
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8 | | - * as published by the Free Software Foundation. |
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9 | | - * |
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10 | | - * You should have received a copy of the GNU General Public License |
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11 | | - * along with this program; if not, write to the Free Software |
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12 | | - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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13 | 6 | */ |
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14 | 7 | |
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15 | 8 | #include <linux/bitops.h> |
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.. | .. |
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18 | 11 | #include <linux/module.h> |
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19 | 12 | #include <linux/of_device.h> |
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20 | 13 | #include <linux/of_platform.h> |
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21 | | -#include <linux/of_gpio.h> |
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22 | 14 | #include <linux/io.h> |
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23 | 15 | #include <linux/gpio/driver.h> |
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24 | 16 | #include <linux/slab.h> |
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.. | .. |
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40 | 32 | |
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41 | 33 | /** |
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42 | 34 | * struct xgpio_instance - Stores information about GPIO device |
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43 | | - * @mmchip: OF GPIO chip for memory mapped banks |
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| 35 | + * @gc: GPIO chip |
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| 36 | + * @regs: register block |
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44 | 37 | * @gpio_width: GPIO width for every channel |
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45 | 38 | * @gpio_state: GPIO state shadow register |
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46 | 39 | * @gpio_dir: GPIO direction shadow register |
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47 | 40 | * @gpio_lock: Lock used for synchronization |
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48 | 41 | */ |
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49 | 42 | struct xgpio_instance { |
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50 | | - struct of_mm_gpio_chip mmchip; |
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| 43 | + struct gpio_chip gc; |
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| 44 | + void __iomem *regs; |
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51 | 45 | unsigned int gpio_width[2]; |
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52 | 46 | u32 gpio_state[2]; |
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53 | 47 | u32 gpio_dir[2]; |
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.. | .. |
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91 | 85 | */ |
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92 | 86 | static int xgpio_get(struct gpio_chip *gc, unsigned int gpio) |
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93 | 87 | { |
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94 | | - struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); |
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95 | 88 | struct xgpio_instance *chip = gpiochip_get_data(gc); |
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96 | 89 | u32 val; |
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97 | 90 | |
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98 | | - val = xgpio_readreg(mm_gc->regs + XGPIO_DATA_OFFSET + |
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| 91 | + val = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET + |
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99 | 92 | xgpio_regoffset(chip, gpio)); |
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100 | 93 | |
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101 | 94 | return !!(val & BIT(xgpio_offset(chip, gpio))); |
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.. | .. |
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113 | 106 | static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) |
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114 | 107 | { |
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115 | 108 | unsigned long flags; |
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116 | | - struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); |
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117 | 109 | struct xgpio_instance *chip = gpiochip_get_data(gc); |
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118 | 110 | int index = xgpio_index(chip, gpio); |
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119 | 111 | int offset = xgpio_offset(chip, gpio); |
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.. | .. |
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126 | 118 | else |
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127 | 119 | chip->gpio_state[index] &= ~BIT(offset); |
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128 | 120 | |
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129 | | - xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET + |
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| 121 | + xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + |
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130 | 122 | xgpio_regoffset(chip, gpio), chip->gpio_state[index]); |
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131 | 123 | |
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132 | 124 | spin_unlock_irqrestore(&chip->gpio_lock[index], flags); |
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.. | .. |
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145 | 137 | unsigned long *bits) |
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146 | 138 | { |
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147 | 139 | unsigned long flags; |
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148 | | - struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); |
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149 | 140 | struct xgpio_instance *chip = gpiochip_get_data(gc); |
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150 | 141 | int index = xgpio_index(chip, 0); |
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151 | 142 | int offset, i; |
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.. | .. |
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156 | 147 | for (i = 0; i < gc->ngpio; i++) { |
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157 | 148 | if (*mask == 0) |
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158 | 149 | break; |
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| 150 | + /* Once finished with an index write it out to the register */ |
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159 | 151 | if (index != xgpio_index(chip, i)) { |
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160 | | - xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET + |
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161 | | - xgpio_regoffset(chip, i), |
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| 152 | + xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + |
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| 153 | + index * XGPIO_CHANNEL_OFFSET, |
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162 | 154 | chip->gpio_state[index]); |
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163 | 155 | spin_unlock_irqrestore(&chip->gpio_lock[index], flags); |
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164 | 156 | index = xgpio_index(chip, i); |
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.. | .. |
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173 | 165 | } |
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174 | 166 | } |
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175 | 167 | |
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176 | | - xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET + |
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177 | | - xgpio_regoffset(chip, i), chip->gpio_state[index]); |
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| 168 | + xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + |
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| 169 | + index * XGPIO_CHANNEL_OFFSET, chip->gpio_state[index]); |
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178 | 170 | |
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179 | 171 | spin_unlock_irqrestore(&chip->gpio_lock[index], flags); |
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180 | 172 | } |
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.. | .. |
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191 | 183 | static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) |
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192 | 184 | { |
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193 | 185 | unsigned long flags; |
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194 | | - struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); |
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195 | 186 | struct xgpio_instance *chip = gpiochip_get_data(gc); |
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196 | 187 | int index = xgpio_index(chip, gpio); |
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197 | 188 | int offset = xgpio_offset(chip, gpio); |
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.. | .. |
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200 | 191 | |
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201 | 192 | /* Set the GPIO bit in shadow register and set direction as input */ |
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202 | 193 | chip->gpio_dir[index] |= BIT(offset); |
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203 | | - xgpio_writereg(mm_gc->regs + XGPIO_TRI_OFFSET + |
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| 194 | + xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + |
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204 | 195 | xgpio_regoffset(chip, gpio), chip->gpio_dir[index]); |
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205 | 196 | |
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206 | 197 | spin_unlock_irqrestore(&chip->gpio_lock[index], flags); |
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.. | .. |
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223 | 214 | static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) |
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224 | 215 | { |
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225 | 216 | unsigned long flags; |
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226 | | - struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); |
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227 | 217 | struct xgpio_instance *chip = gpiochip_get_data(gc); |
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228 | 218 | int index = xgpio_index(chip, gpio); |
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229 | 219 | int offset = xgpio_offset(chip, gpio); |
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.. | .. |
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235 | 225 | chip->gpio_state[index] |= BIT(offset); |
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236 | 226 | else |
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237 | 227 | chip->gpio_state[index] &= ~BIT(offset); |
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238 | | - xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET + |
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| 228 | + xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + |
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239 | 229 | xgpio_regoffset(chip, gpio), chip->gpio_state[index]); |
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240 | 230 | |
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241 | 231 | /* Clear the GPIO bit in shadow register and set direction as output */ |
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242 | 232 | chip->gpio_dir[index] &= ~BIT(offset); |
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243 | | - xgpio_writereg(mm_gc->regs + XGPIO_TRI_OFFSET + |
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| 233 | + xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + |
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244 | 234 | xgpio_regoffset(chip, gpio), chip->gpio_dir[index]); |
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245 | 235 | |
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246 | 236 | spin_unlock_irqrestore(&chip->gpio_lock[index], flags); |
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.. | .. |
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250 | 240 | |
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251 | 241 | /** |
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252 | 242 | * xgpio_save_regs - Set initial values of GPIO pins |
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253 | | - * @mm_gc: Pointer to memory mapped GPIO chip structure |
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| 243 | + * @chip: Pointer to GPIO instance |
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254 | 244 | */ |
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255 | | -static void xgpio_save_regs(struct of_mm_gpio_chip *mm_gc) |
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| 245 | +static void xgpio_save_regs(struct xgpio_instance *chip) |
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256 | 246 | { |
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257 | | - struct xgpio_instance *chip = |
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258 | | - container_of(mm_gc, struct xgpio_instance, mmchip); |
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259 | | - |
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260 | | - xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET, chip->gpio_state[0]); |
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261 | | - xgpio_writereg(mm_gc->regs + XGPIO_TRI_OFFSET, chip->gpio_dir[0]); |
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| 247 | + xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET, chip->gpio_state[0]); |
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| 248 | + xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET, chip->gpio_dir[0]); |
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262 | 249 | |
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263 | 250 | if (!chip->gpio_width[1]) |
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264 | 251 | return; |
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265 | 252 | |
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266 | | - xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET + XGPIO_CHANNEL_OFFSET, |
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| 253 | + xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + XGPIO_CHANNEL_OFFSET, |
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267 | 254 | chip->gpio_state[1]); |
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268 | | - xgpio_writereg(mm_gc->regs + XGPIO_TRI_OFFSET + XGPIO_CHANNEL_OFFSET, |
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| 255 | + xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + XGPIO_CHANNEL_OFFSET, |
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269 | 256 | chip->gpio_dir[1]); |
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270 | | -} |
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271 | | - |
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272 | | -/** |
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273 | | - * xgpio_remove - Remove method for the GPIO device. |
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274 | | - * @pdev: pointer to the platform device |
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275 | | - * |
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276 | | - * This function remove gpiochips and frees all the allocated resources. |
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277 | | - * |
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278 | | - * Return: 0 always |
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279 | | - */ |
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280 | | -static int xgpio_remove(struct platform_device *pdev) |
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281 | | -{ |
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282 | | - struct xgpio_instance *chip = platform_get_drvdata(pdev); |
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283 | | - |
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284 | | - of_mm_gpiochip_remove(&chip->mmchip); |
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285 | | - |
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286 | | - return 0; |
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287 | 257 | } |
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288 | 258 | |
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289 | 259 | /** |
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.. | .. |
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347 | 317 | spin_lock_init(&chip->gpio_lock[1]); |
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348 | 318 | } |
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349 | 319 | |
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350 | | - chip->mmchip.gc.ngpio = chip->gpio_width[0] + chip->gpio_width[1]; |
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351 | | - chip->mmchip.gc.parent = &pdev->dev; |
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352 | | - chip->mmchip.gc.direction_input = xgpio_dir_in; |
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353 | | - chip->mmchip.gc.direction_output = xgpio_dir_out; |
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354 | | - chip->mmchip.gc.get = xgpio_get; |
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355 | | - chip->mmchip.gc.set = xgpio_set; |
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356 | | - chip->mmchip.gc.set_multiple = xgpio_set_multiple; |
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| 320 | + chip->gc.base = -1; |
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| 321 | + chip->gc.ngpio = chip->gpio_width[0] + chip->gpio_width[1]; |
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| 322 | + chip->gc.parent = &pdev->dev; |
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| 323 | + chip->gc.direction_input = xgpio_dir_in; |
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| 324 | + chip->gc.direction_output = xgpio_dir_out; |
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| 325 | + chip->gc.get = xgpio_get; |
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| 326 | + chip->gc.set = xgpio_set; |
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| 327 | + chip->gc.set_multiple = xgpio_set_multiple; |
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357 | 328 | |
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358 | | - chip->mmchip.save_regs = xgpio_save_regs; |
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| 329 | + chip->gc.label = dev_name(&pdev->dev); |
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359 | 330 | |
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360 | | - /* Call the OF gpio helper to setup and register the GPIO device */ |
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361 | | - status = of_mm_gpiochip_add_data(np, &chip->mmchip, chip); |
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| 331 | + chip->regs = devm_platform_ioremap_resource(pdev, 0); |
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| 332 | + if (IS_ERR(chip->regs)) { |
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| 333 | + dev_err(&pdev->dev, "failed to ioremap memory resource\n"); |
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| 334 | + return PTR_ERR(chip->regs); |
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| 335 | + } |
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| 336 | + |
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| 337 | + xgpio_save_regs(chip); |
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| 338 | + |
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| 339 | + status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip); |
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362 | 340 | if (status) { |
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363 | | - pr_err("%pOF: error in probe function with status %d\n", |
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364 | | - np, status); |
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| 341 | + dev_err(&pdev->dev, "failed to add GPIO chip\n"); |
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365 | 342 | return status; |
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366 | 343 | } |
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367 | 344 | |
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.. | .. |
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377 | 354 | |
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378 | 355 | static struct platform_driver xgpio_plat_driver = { |
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379 | 356 | .probe = xgpio_probe, |
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380 | | - .remove = xgpio_remove, |
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381 | 357 | .driver = { |
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382 | 358 | .name = "gpio-xilinx", |
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383 | 359 | .of_match_table = xgpio_of_match, |
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