.. | .. |
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557 | 557 | * Device [8086:2fc0] |
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558 | 558 | * Erratum HSE43 |
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559 | 559 | * CONFIG_TDP_NOMINAL CSR Implemented at Incorrect Offset |
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560 | | - * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v3-spec-update.html |
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| 560 | + * https://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v3-spec-update.html |
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561 | 561 | * |
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562 | 562 | * Devices [8086:6f60,6fa0,6fc0] |
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563 | 563 | * Erratum BDF2 |
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564 | 564 | * PCI BARs in the Home Agent Will Return Non-Zero Values During Enumeration |
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565 | | - * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v4-spec-update.html |
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| 565 | + * https://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v4-spec-update.html |
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566 | 566 | */ |
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567 | 567 | static void pci_invalid_bar(struct pci_dev *dev) |
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568 | 568 | { |
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.. | .. |
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587 | 587 | static void pci_fixup_amd_ehci_pme(struct pci_dev *dev) |
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588 | 588 | { |
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589 | 589 | dev_info(&dev->dev, "PME# does not work under D3, disabling it\n"); |
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590 | | - dev->pme_support &= ~((PCI_PM_CAP_PME_D3 | PCI_PM_CAP_PME_D3cold) |
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| 590 | + dev->pme_support &= ~((PCI_PM_CAP_PME_D3hot | PCI_PM_CAP_PME_D3cold) |
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591 | 591 | >> PCI_PM_CAP_PME_SHIFT); |
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592 | 592 | } |
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593 | 593 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7808, pci_fixup_amd_ehci_pme); |
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