kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/arch/x86/kernel/acpi/cstate.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (C) 2005 Intel Corporation
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  * 	Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
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@@ -51,6 +52,33 @@
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 	if (c->x86_vendor == X86_VENDOR_INTEL &&
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 	    (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f)))
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 			flags->bm_control = 0;
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+	/*
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+	 * For all recent Centaur CPUs, the ucode will make sure that each
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+	 * core can keep cache coherence with each other while entering C3
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+	 * type state. So, set bm_check to 1 to indicate that the kernel
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+	 * doesn't need to execute a cache flush operation (WBINVD) when
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+	 * entering C3 type state.
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+	 */
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+	if (c->x86_vendor == X86_VENDOR_CENTAUR) {
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+		if (c->x86 > 6 || (c->x86 == 6 && c->x86_model == 0x0f &&
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+		    c->x86_stepping >= 0x0e))
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+			flags->bm_check = 1;
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+	}
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+
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+	if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
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+		/*
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+		 * All Zhaoxin CPUs that support C3 share cache.
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+		 * And caches should not be flushed by software while
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+		 * entering C3 type state.
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+		 */
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+		flags->bm_check = 1;
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+		/*
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+		 * On all recent Zhaoxin platforms, ARB_DISABLE is a nop.
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+		 * So, set bm_control to zero to indicate that ARB_DISABLE
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+		 * is not required while entering C3 type state.
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+		 */
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+		flags->bm_control = 0;
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+	}
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 }
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 EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
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